DEVELOPMENT OF ANTI-RIGGING VOTING SYSTEM USING SMART CARD TECHNOLOGY

A Project Report Submitted in the Partial Fulfillment of the Requirements for the Award of the Degree of
BACHELOR OF TECHNOLOGY IN

ELECTRONICS AND COMMUNICATION ENGINEERING

SUBMITTED BY

NAME OF THE STUDENT(s) ROLL NO(s)

(Font metrics:14pt Weight: Bold Type: Times New Roman)

Department of Electronics and Communication Engineering

QIS INSTITUTE OF TECHNOLOGY

( Affiliated to JNTU, Kakinada ) 2011

QIS INSTITUTE OF TECHNOLOGY (address of clg)

CERTIFICATE

This is to certify that the project work entitled Title of the project done by Name of the student bearing Reg.No. _________________, student of Department of Electronics and Communication Engineering , is a record of bonafide work carried out by him/her. This project is done as a partial fulfillment of obtaining Bachelor of Technology Degree to be awarded by Jawaharlal Nehru Technological University, Kakinada. The matter embodied in this project report has not been submitted to any other university for the award of any other degree.

<NAME > <DESIGNATION >

Head, Department of E.C.E

( INTERNAL GUIDE)

INDEX

CONTENTS:

1. Abbreviations 2. Introduction 3. Block Diagram 4. Block Diagram Description 5. Schematic 6. Schematic Description 7. Hardware Components 9. software 10. Conclusion (or) Synopsis Microcontroller SMART CARD BUZZER LCD POWER SUPPLY LINEAR KEYPAD EEPROM

8. Circuit Description

11. Future Aspects

12. Bibliography

ABBREVIATIONS SYMBOL ACC B PSW SP DPTR DPL DPH P0 P1 P2 P3 IP IE TMOD TCON T2CON T2MOD TH0 TL0 TH1 TL1 TH2 TL2 SCON SBUF PCON NAME Accumulator B register Program status word Stack pointer Data pointer 2 bytes Low byte High byte Port0 Port1 Port2 Port3 Interrupt priority control Interrupt enable control Timer/counter mode control Timer/counter control Timer/counter 2 control Timer/counter mode2 control Timer/counter 0high byte Timer/counter 0 low byte Timer/counter 1 high byte Timer/counter 1 low byte Timer/counter 2 high byte Timer/counter 2 low byte Serial control Serial data buffer Power control

INTRODUCTION

expand. With the introduction of the OQO Model 2 with the Windows XP operating system and ports such as a USB port both features usually belong to "general purpose computers", the line of nomenclature blurs even more.

EMBEDDED SYSTEM:

An embedded system is a special-purpose system in which the computer is completely encapsulated by or dedicated to the device or system it controls. Unlike a general-purpose computer, such as a personal computer, an embedded system performs one or a few predefined tasks, usually with very specific requirements. Since the system is dedicated to specific tasks, design engineers can optimize it, reducing the size and cost of the product. Embedded systems are often mass-produced, benefiting from economies of scale.

Physically, embedded systems ranges from portable devices such as digital watches and MP3 players, to large stationary installations like traffic lights, factory controllers, or the systems controlling nuclear power plants.

In terms of complexity embedded systems can range from very simple with a single microcontroller chip, to very complex with multiple units, peripherals and networks mounted inside a large chassis or enclosure. Examples of Embedded Systems: Avionics, such as and inertial other

Personal

digital

assistants

(PDAs) or handheld computers are generally considered embedded devices because of the nature of their hardware design, even though they are more expandable in software terms. This line of definition continues to blur as devices

guidance systems, flight control hardware/software

integrated systems in aircraft and missiles Cellular telephones and telephone switches Engine controllers and antilock brake controllers for automobiles Home automation products, such as thermostats, air conditioners, sprinklers, and security monitoring systems Handheld calculators Handheld computers Household appliances, including microwave ovens, washing machines, television sets, DVD players and recorders Medical equipment Personal digital assistant Videogame consoles Computer peripherals such as routers and printers. Industrial controllers for remote machine operation. The Smart Card Reader is an electronic device that reads smart cards. Communication is done via protocols and you can read and write to a fixed address on the card. The main objective of this

which is implemented using smart card technology. A smart card is used as a voter id card which provides authentication and identification for a person. In this project microcontroller is used which forms the control unit. Every citizen of India is given with a smart card. Whenever user wants to vote he needs to insert his smart card in smart card reader while voting. Then the voter is asked to vote for his favorite candidate through keypad. So, user need to press the key corresponding to his favorite candidate. This system even allows the election commission to see the no. of votes given for each candidate and is displayed in LCD which got interfaced to microcontroller.

project is anti-rigging voting system

insert the smartcard into card driver it reads the data and send it to the microcontroller. The microcontroller is used to monitor all the control operations. When the smart card is read successfully the keys will be activated

Block diagram:

Power supply

LCD

smart card reader

Micro controller

Keypad

Buzzer

EEPROM

Block diagram explanation: The application of the project is to access the different provided to vote using the smart cards. Whenever we

and permission to vote will be given. So rigging is eliminated using the smartcards.

terminals we are taking the output to the rectifier. The bridge rectifier converts the AC coming from the secondary of the transformer into pulsating DC. The output of this rectifier is further given to the smoother circuit which is capacitor in our project. The smoothing circuit eliminates the ripples from the pulsating DC and gives the pure DC to the RPS to get a constant output DC voltage. The RPS regulates the voltage as per our requirement. Microcontroller:

Schematic:

Schematic explanation: Power Supply: The main aim of this power supply is to convert the 230V AC into 5V DC in order to give supply for the TTL or CMOS devices. In this process we are using a step down transformer, a bridge rectifier, a smoothing circuit and the RPS. At the primary of the transformer we are giving the 230V AC supply. The secondary is connected to the opposite terminals of the Bridge rectifier as the input. From other set of opposite

Port 1 is used to interface the keypad as shown in the diagram.p3.0 and p3.1 are connected to the transmit and receive pin are max 232(12.11) MAX232: This is used to convert the voltage levels from TTL/CMOS to RS level and vice versa. It consists of TTL/CMOS input and output pins to TTL devices and RS input and output pins to connect smartcard .MAX232 TTL input pin (i.e. pin11) is connected to pin11 namely TX of microcontroller and RS output pin (i.e. pin12) is

connected to pin10 namely RX of microcontroller. And the supply connections are given from the Power supply output 7805 to the VCC and VSS pins of the MAX232.

BUZZER: Buzzer is connected to the port P2.4.

EEPROM: EEPROM will be connected to the port P2.0,P2.1. DB-9 connector: It is a 9-pin connector consists of transmit and receive pins along with some hand-shaking lines. LCD: The data pins(pin no 7 to 14) are connected to the port 0 through the pull up resistances respectively as shown in the figure.Now the command pins(4,5,6)pin n1 and 3 of LCD are connected to preset. are connected to the port p2.5,p2.6,p2.7 respectively. KEYS: KEYS are connected to the port P1.0 to P1.7 &P3.5 to P3.7.

HARDWARE COMPONENTS MICROCONTROLLER

Features: Compatible with MCS-51 Products 4K Bytes of In-System Programmable (ISP) Flash Memory 4.0V to 5.5V Operating Range 128 x 8-bit Internal RAM 32 Programmable I/O Lines Two 16-bit Timer/Counters Six Interrupt Sources Full Duplex UART Serial Channel Low-power Idle and Power-down Modes

chip oscillator, and clock circuitry. In Description: The AT89S51 is a low-power, high-performance CMOS 8-bit microcontroller with 4K bytes of insystem programmable Flash memory. The device is manufactured using Atmels high-density nonvolatile addition, the AT89S51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset.

memory technology and is compatible with the industry- standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed conventional in-system nonvolatile or by a memory

programmer. By combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic chip, the Atmel AT89S51 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.

The AT89S51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-

Pin Description: VCC: Supply voltage. GND: Ground. Port 0: Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull-ups are required during program verification. Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 1 also receives the low-order

address bytes during Flash programming and verification.

Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers cansink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some

control

signals

during

Flash

externally being pulled low will source current (IIL) because of the pull-ups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S51, as shown in the following table.

programming and verification. Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are

RST: Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives High for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled. ALE/PROG: Address Latch Enable (ALE) is an output pulse for latching the

low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH.

With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode. PSEN: Program Store Enable (PSEN) is the read strobe to external program memory. When the AT89S51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. EA/VPP: External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped

to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming. XTAL1: Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2: Output from the inverting oscillator amplifier Special Function Registers: A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 1. Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.

User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.

Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the five interrupt sources in the IP register.

Dual Data Pointer Registers: To facilitate accessing both

accessing the respective Data Pointer Register.

internal and external data memory, two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H- 83H and DP1 at 84H85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1. The user should always initialize the DPS bit to the appropriate value before Power off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to 1 during power up. It can be set and rest under software control and is not affected by reset.

Memory Organization: MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed. Program Memory: If the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89S51, if EA is connected to VCC, program fetches to addresses 0000H through FFFH are directed to internal memory and fetches to addresses 1000H through FFFFH are directed to external memory. Data Memory:

The AT89S51 implements 128 bytes of on-chip RAM. The 128 bytes are accessible via direct and indirect addressing modes. Stack operations are examples of indirect addressing, so the 128 bytes of data RAM are available as stack space. Watchdog Timer (One-time Enabled with Reset-out): The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST

register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent WDT on the external clock frequency. There is no way to disable the except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST pin. Using the WDT: To enable the WDT, a user must write 01EH and 0E1H in sequence to the DTRST register (SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH), and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycles. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output

RESET pulse at the RST pin. The RESET pulse duration is 98xTOSC, where TOSC=1/FOSC. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset. WDT During Power-down and Idle: In Power-down mode the

oscillator stops, which means the WDT also stops. While in Power down mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated mode. external When interrupt, which is enabled prior to entering Power-down Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever the AT89S51 is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset

during the interrupt service for the interrupt used to exit Power-down mode. To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to reset the WDT just before entering Power-down mode. Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the AT89S51 while in IDLE mode, the user should always set up a timer that will periodically exit IDLE, service the WDT, and IDLE mode. With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE. UART: The UART in the AT89S51 operates the same way as the UART in the AT89C51. Timer 0 and 1: reenter

Timer 0 and Timer 1 in the AT89S51 operate the same way as Timer 0 and Timer 1 in the AT89C51. Interrupts: The AT89S51 has a total of five interrupt vectors: two external interrupts (INT0 and INT1), two timer interrupts (Timers 0 and 1), and the serial port interrupt. These interrupts are all shown in Figure 1. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once. Note that Table 4 shows that bit position IE.6 is unimplemented. In the AT89S51, bit position IE.5 is also unimplemented. User software should not write 1s to these bit positions, since they may be used in future AT89 products. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle.

Oscillator Characteristics: XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator, as shown in

Figure 2. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven, as shown in

Figure 3. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-

two

flip-flop,

but

minimum

and

maximum voltage high and low time specifications must be observed.

Idle Mode: In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special function registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a

hardware reset. Note that when idle mode is terminated by a hardware reset, the device normally resumes program execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a

port pin when idle mode is terminated by a reset, the instruction following the one that invokes idle mode should not write to a port pin or to external memory.

and Special Function Registers retain their values until the Power-down mode is terminated. Exit from Power-down mode can be initiated either by a hardware reset or by activation of an enabled external interrupt into INT0 or

Power-down Mode: In the Power-down mode, the oscillator is stopped, and the instruction that invokes Powerdown is the last instruction executed. The on-chip RAM

INT1. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.

Program Memory Lock Bits: The AT89S51 has three lock bits that can be left unprogrammed (U) or

can be programmed (P) to obtain the additional features listed in the following table.

When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value and holds that value until reset is activated. The latched value of EA must agree with the current logic level at that pin in order for the device to function properly. Programming the Flash Parallel Mode: The AT89S51 is shipped with the on-chip Flash memory array ready to be programmed. The programming interface needs a high-voltage (12-volt) program enable signal and is compatible with conventional third-party Flash or EPROM programmers. The AT89S51 code memory array is programmed byteby-byte.

Programming Algorithm: Before programming the

AT89S51, the address, data, and control signals should be set up according to the Flash programming mode table and Figures 13 and 14. To program the AT89S51, take the following steps: 1. Input the desired memory location on the address lines. 2. Input the appropriate data byte on the data lines. 3. Activate the correct combination of control signals. 4. Raise EA/VPP to 12V. 5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The bytewrite cycle is self-timed and typically takes no more than 50 s. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached.

Data Polling: The AT89S51 features Data

Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 000H, 100H, and 200H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows. (000H) = 1EH indicates manufactured by Atmel (100H) = 51H indicates 89S51 (200H) = 06H Chip Erase: progress of byte In the parallel programming

Polling to indicate the end of a byte write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written data on P0.7. Once the write cycle has been completed, true data is valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated. Ready/Busy: The

programming can also be monitored by the RDY/BSY output signal. P3.0 is pulled low after ALE goes high during programming to indicate BUSY. P3.0 is pulled high again when programming is done to indicate READY. Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The status of the individual lock bits can be verified directly by reading them back.

mode, a chip erase operation is initiated by using the proper combination of control signals and by pulsing ALE/PROG low for a duration of 200 ns - 500 ns. In the serial programming mode, a chip erase operation is initiated by issuing the Chip Erase instruction. In this mode, chip erase is self-timed and takes about 500 ms. During chip erase, a serial read from any address location will return 00H at the data output.

Programming the Flash Serial Mode: The Code memory array can be programmed using the serial ISP interface while RST is pulled to VCC. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RST is set high, the Programming Enable instruction needs to be executed first before other operations can be executed. Before a reprogramming sequence can occur, a Chip Erase operation is required. The Chip Erase operation turns the content of every memory location in the Code array into FFH. Either an external system clock can be supplied at pin XTAL1 or a crystal needs to be connected across pins XTAL1 and XTAL2. The maximum serial clock (SCK) frequency should be less than 1/16 of the crystal frequency. With a 33 MHz oscillator clock, the maximum SCK frequency is 2 MHz. mode,

To program and verify the AT89S51 in the serial programming the following sequence is recommended: 1. Power-up sequence: Apply power between VCC and GND pins. Set RST pin to H. If a crystal is not connected across pins XTAL1 and XTAL2, apply a 3 MHz to 33 MHz clock to XTAL1 pin and wait for at least 10 milliseconds. 2. Enable serial programming by sending the Programming Enable serial instruction to pin MOSI/P1.5. The frequency of the shift clock supplied at pin SCK/P1.7 needs to be less than the CPU clock at XTAL1 Divided by 16. 3. The Code array is programmed one byte at a time in either the Byte or Page mode. The write cycle is self-timed and typically takes less than 0.5 ms at 5V. 4. Any memory location can be verified

Serial Programming Algorithm:

by using the Read instruction that returns the content at the selected address at serial output MISO/P1.6.

5. At the end of a programming session, RST can be set low to commence normal device operation. Power-off sequence (if needed): Set XTAL1 to L (if a crystal is not used). Set RST to L. Turn VCC power off. Data Polling: The Data Polling feature is also available in the serial mode. In this mode, during a write cycle an attempted read of the last byte written will result in the complement of the MSB of the serial output byte on MISO. Serial Programming Instruction Set:

The

Instruction

Set

for

Serial

Programming follows a 4-byte protocol and is shown in Table 8 on page 18. Programming Interface Parallel Mode: Every code byte in the Flash array can be programmed by using the appropriate combination of control signals. The write operation cycle is self-timed and once initiated, will automatically time itself to Completion. All major programming vendors offer worldwide support for the Atmel microcontroller series. Please contact your local programming vendor for the appropriate software revision.

After Reset signal is high, SCK should be low for at least 64 system clocks before it goes high to clock in the enable data bytes. No pulsing of Reset signal is necessary. SCK should be no faster than 1/16 of the system clock at XTAL1. For Page Read/Write, the data always starts from byte 0 to 255. After the

command byte and upper address byte are latched, each byte thereafter is treated as data until all 256 bytes are shifted in/out. Then the next instruction will be ready to be decoded.

*NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not

implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Liquid Crystal Display

Introduction to LCD: In recent years the LCD is finding widespread use replacing LED s (sevensegment LED or other multi segment LED s). This is due to the following reasons: 1. The declining prices of LCD s. 2. The ability to display numbers, characters and graphics. This is 5.

in

contract

to LED s, which are limited to numbers and a few characters. 3. Incorporation of a refreshing controller into the LCD, there by relieving the CPU of the task of refreshing the LCD. In the contrast, the LED must be refreshed by the CPU to keep displaying the data. 4. Ease of programming for characters and graphics.

USES: The LCD s used exclusively in watches, calculators and measuring instruments is the simple seven-segment displays, having a limited amount of numeric data. The recent advances in

technology

have resulted in better

legibility, more information displaying capability and a wider temperature range. These have resulted in the LCD s being extensively used in telecommunications and entertainment electronics. The LCD s has even started

replacing the cathode ray tubes (CRTs) used for the display of text and graphics, and also in small TV applications.

Character Table: EnglishEuropean (RS in Datasheet) Module dimension: 80.0mm x 36.0mm x 13.2mm(MAX) View area: 66.0 x 16.0 mm Active area: 56.2 x 11.5 mm Dot size: 0.56 x 0.66 mm Dot pitch: 0.60 x 0.70 mm Character size: 2.96 x 5.46 mm Character pitch: 3.55 x 5.94 mm LCD type: STN, Positive, Transflective, Yellow/Green Duty: 1/16 View direction: Wide viewing angle Backlight Type: yellow/green LED RoHS Compliant: lead free Operating Temperature: -20C to + 70C

Specifications:

Number of Characters: 16 characters x 2 Lines

LCD PIN DIAGRAM:

LCD pin description: The LCD discussed in this section has 14 pins. The TABLE 1: Pin description for LCD: Pin 1 2 3 Symbol Vss Vcc VEE

function of each pin is given in table.

I/O ----

Description Ground +5V power supply Power supply to

control contrast 4 RS I RS=0 to select

command register RS=1 to select data register 5 R/W I R/W=0 for write R/W=1 for read 6 7 8 9 10 E DB0 DB1 DB2 DB3 I/O I/O I/O I/O I/O Enable The 8-bit data bus The 8-bit data bus The 8-bit data bus The 8-bit data bus

11 12 13 14

DB4 DB5 DB6 DB7

I/O I/O I/O I/O

The 8-bit data bus The 8-bit data bus The 8-bit data bus The 8-bit data bus

TABLE 2: LCD Command Codes Code (hex) Command to LCD Instruction Register

1 2 4 6 5 7 8 A C E F 10 14 18 1C 80

Clear display screen Return home Decrement cursor Increment cursor Shift display right Shift display left Display off, cursor off Display off, cursor on Display on, cursor off Display on, cursor on Display on, cursor blinking Shift cursor position to left Shift cursor position to right Shift the entire display to the left Shift the entire display to the right Force cursor to beginning of 1st line

C0 38

Force cursor to beginning of 2nd line 2 lines and 5x7 matrix

LCD INTERFACING:

Sending

commands

and

data

to

LCDs

with

time

delay:

To send any command from table 2 to the LCD, make pin RS=0. For data, make RS=1.Then place a high to low

pulse on the E pin to enable the internal latch of the LCD.

In this project we are using LCD to display the number of votes gained by the each party.

over RS-232) the low logic voltage has to be "bumped up", and a negative voltage has to be generated, too. RS-232 TTL Logic:

MAX-232: Introduction: Logic Signal Voltage Serial RS-232 (V.24) communication works with voltages (between -15V ... -3V and used to transmit a binary '1' and +3V ... +15V to transmit a binary '0') which are not compatible with today's computer logic voltages. On the other hand, classic TTL computer logic operates between 0V ... +5V (roughly 0V ... +0.8V referred to as low for binary '0', +2V ... +5V for high binary '1' ). Modern low-power logic operates in the range of 0V ... +3.3V or even lower. So, the maximum RS-232 signal levels are far too high for today's computer logic electronics, and the negative RS232 voltage can't be grokked at all by the computer logic. Therefore, to receive serial data from an RS-232 interface the voltage has to be reduced, and the 0 and 1 voltage levels inverted. In the other direction (sending data from some logic

-------------------------------------------------15V...-3V <-> +2V ... +5V <-> 1

+3V...+15V <-> 0V ... +0.8V <-> 0 All this can be done with conventional analog electronics, e.g. a particular power supply and a couple of transistors or the once popular 1488 (transmitter) and 1489 (receiver) ICs. However, since more than a decade it has become standard in amateur electronics to do the necessary signal level conversion with an integrated circuit (IC) from the MAX232 family (typically a MAX232A or some clone). In fact, it is hard to find some RS-232 circuitry some clone. The MAX232 & MAX232A: in amateur electronics without a MAX232A or

MAX232, and the MAX232A only needs external capacitors 1/10th the capacity of what the original MAX232 needs. It should be noted that the MAX232 (A) is just a driver/receiver. It does not generate the necessary RS-232 sequence of marks and spaces with the right A MAX232 integrated circuit The MAX232 from Maxim was the first IC which in one package contains the necessary drivers (two) and receivers (also two), to adapt the RS-232 signal voltage levels to TTL logic. It became popular, because it just needs one voltage necessary (+5V) and generates voltage the levels RS-232 timing, it does not decode the RS-232 signal, to it does signal not provide a serial/parallel conversion. All it does is convert voltage levels. Generating serial data with the right timing and decoding serial data has to be done by additional circuitry, e.g. by a 16550 UART or one of these small micro controllers (e.g. Atmel AVR, Microchip PIC) getting more and more popular. The MAX232 and MAX232A were once rather expensive ICs, but today they are cheap. It has also helped that many companies now produce clones (ie. Sipex). These clones sometimes need different external circuitry, e.g. the capacities of the external capacitors The MAX232 has a successor, the MAX232A. The ICs are almost identical, however, the MAX232A is much more often used than the original vary. It is recommended to check the data sheet of the particular manufacturer of an IC instead of relying on Maxim's original data sheet.

(approx. -10V and +10V) internally. This greatly simplified the design of circuitry. Circuitry designers no longer need to design and build a power supply with three voltages (e.g. -12V, +5V, and +12V), but could just provide one +5V power supply, e.g. with the help of a simple 78x05 voltage converter.

The original manufacturer (and now some clone manufacturers, too) offers a large series of similar ICs, with different numbers of receivers and drivers, voltages, built-in or external capacitors, etc. E.g. The MAX232 and MAX232A need external capacitors for the internal voltage pump, while the MAX233 has these capacitors built-in. The MAX233 is also between three and ten times more MAX232(A) DIP Package:

expensive in electronic shops than the MAX232A because of its internal capacitors. It is also more difficult to get the MAX233 than the garden variety MAX232A. A similar IC, the MAX3232 is nowadays available for low-power 3V logic.

MAX232(A) DIP Package Pin Layout: Nbr Name Purpose Signal Voltage Capacitor Value Capacitor Value MAX232A

MAX232 1 C1+ + connector for capacitor capacitor C1 output of voltage pump should 1F 100nF

stand at least 16V +10V, should least 16V should capacitor stand

V+

at 1F to VCC

100nF to VCC

C1-

- connector for capacitor capacitor C1

stand at least 16V should

1F

100nF

C2+

+ connector for capacitor capacitor C2

stand at least 16V should

1F

100nF

C2-

- connector for capacitor capacitor C2 output of voltage pump / inverter

stand at least 16V -10V, should least 16V RS-232 capacitor stand

1F

100nF

V-

at 1F to GND

100nF to GND

7 8 9 10 11 12 13 14 15 16

T2out Driver 2 output R2in R2out T2in T1in R1out R1in

Receiver 2 input RS-232 Receiver output Driver 2 input Driver 1 input Receiver output 1 2 TTL TTL TTL TTL

Receiver 1 input RS-232 RS-232 0V +5V 1F to VCC see above 100nF to VCC see above

T1out Driver 1 output GND VCC Ground Power supply

V+(2) is also connected to VCC via a capacitor (C3). V-(6) is connected to GND via a capacitor (C4). And GND(16) and VCC(15) are also

Typically a pair of a driver/receiver of the MAX232 is used for

TX and RX

and the second one for connected by a capacitor (C5), as close as possible to the pins.

CTS and RTS.

There are not enough drivers/receivers in the MAX232 to also connect the DTR, DSR, and DCD signals. Usually these

A Typical Application: The MAX232 (A) has two receivers (converts from RS-232 to TTL voltage levels) and two drivers (converts from TTL logic to RS-232 voltage levels). This means only two of the RS-232 signals can be converted in each direction. The old MC1488/1498 combo provided four drivers and receivers.

signals can be omitted when e.g. communicating with a PC's serial interface. If the DTE really requires these signals either a second MAX232 is needed, or some other IC from the MAX232 family can be used (if it can be found in consumer electronic shops at all). An alternative for DTR/DSR is also given below.

The circuitry is completed by connecting five capacitors to the IC as it follows. The MAX232 needs 1.0F capacitors, the MAX232A needs 0.1F capacitors. MAX232 differences. clones It is show similar to recommended

least 16V capacitor types should be used. If electrolytic or tantalic capacitors are used, the polarity has to be observed. The first pin as listed in the following table is always where the plus pole of the capacitor should be connected to.

consult the corresponding data sheet. At

Capacitor C1 C2 C3 C4 C5

+ Pin 1 4 2 GND 16

- Pin 3 5 16 6 GND

Remark

This looks non-intuitive, but because pin 6 is on -10V, GND gets the + connector, and not the -

The 5V power supply is connected to +5V: Pin 16

GND: Pin 15 EEPROM:

EEPROM

(also

written

Functions of EEPROM: There are different types of electrical interfaces to EEPROM devices. Main categories of these interface types are :

E2PROM and pronounced e-e-prom or simply e-squared), which stands for Electrically Erasable Programmable Read-Only Memory, is a type of nonvolatile memory used in computers and other electronic devices to store small amounts of data that must be saved when power is removed, e.g., calibration tables or device configuration. When larger amounts of more static data are to be stored (such as in USB flash drives) other memory types like flash memory are more economical. EEPROMs are realized as arrays of floating-gate transistors. History: In 1983, Greek American George Perlegos at Intel developed the Intel 2816, which was built on earlier EPROM technology, but used a thin gate oxide layer so that the chip could erase its own bits without requiring a UV source. Perlegos and others later left Intel to form Seeq Technology, which used on-device charge pumps to supply the high voltages necessary for programming EEPROMs.[1]

Serial bus Parallel bus

How the device is operated depends on the electrical interface.

Serial bus devices: Most common serial interface types are SPI, IC and 1-Wire. These three interfaces require between 2 and 4 controls signals for operation, resulting in a memory device in an 8 pin (or less) package. The serial EEPROM typically operates in three phases: OP-Code Phase, Address Phase and Data Phase. The OP-Code is usually the first 8-bits input to the serial input pin of the EEPROM device (or with most IC devices, is implicit); followed by 8 to 24 bits of addressing depending on the depth of the device, then data to be read or written. Each EEPROM device typically has its own set of OP-Code instructions to map

to different functions. Some of the common operations on SPI EEPROM devices are:

Failure modes: There are two limitations of stored information; endurance, and data retention. During rewrites, the gate oxide in the floating-gate accumulates transistors trapped gradually The electrons.

Write Enable (WREN) Write Disable (WRDI) Read Status Register (RDSR) Write Status Register (WRSR) Read Data (READ) Write Data (WRITE)

electric field of the trapped electrons adds to the electrons in the floating gate, lowering the window between threshold voltages for zeros vs ones. After sufficient number of rewrite cycles, the difference becomes too small to be recognizable, the cell is stuck in programmed state, and endurance failure occurs. The manufacturers usually specify minimal number of rewrites devices being 106 or more. During storage, the electrons injected into the floating gate may drift through the insulator, especially at increased temperature, and cause charge loss, reverting the cell into erased state. The manufacturers usually guarantee data retention of 10 years or more.[2] Related types Flash memory is a later form of EEPROM. In the industry, there is a convention to reserve the term EEPROM to byte-wise writeable memories

Other operations supported by some EEPROM devices are:

Program Sector Erase Chip Erase commands

Parallel bus devices: Parallel EEPROM

typically have an 8-bit data bus and an address bus wide enough to cover the complete memory. Most devices have chip select and write protect pins. Some microcontrollers also have integrated parallel EEPROM. Operation of a parallel EEPROM is simple and fast when compared to serial EEPROM, but these devices are larger due to the higher pin count (up to 32 pins or more) and have been decreasing in popularity in favor of serial EEPROM or Flash.

compared to block-wise writable flash memories. EEPROM takes more die area than flash memory for the same capacity because each cell usually needs both a read, write and erase transistor, while in flash memory the erase circuits are shared by large blocks of cells (often 5128). Newer technologies non-volatile such as memory FeRAM and

EPROMs can't be erased electrically, and are programmed via hot carrier injection onto the floating gate. Erase is via an ultraviolet light source, although in UV practice light, many and EPROMs are are encapsulated in plastic that is opaque to "one-time programmable". Most NOR Flash memory is a hybrid styleprogramming is through Hot carrier injection and erase is through Fowler-Nordheim tunneling. LINEAR KEYPAD: This section basically consists of a Linear keypad. Basically a keypad can be classified in to two categories. 1. Linear keypad 2. Matrix keypad Linear keypad: This keypad has n no. of key connected to n data lines of microcontroller. This keypad is used where one needs to connect less no. of keys. In this project, a Linear keypad is used with three switches being connected because the no. of switches used is less (less than 8). Generally, in linear keypads, one end of the switch is connected to

MRAM are slowly replacing EEPROMs in some applications, but are expected to remain a small fraction of the EEPROM market for the foreseeable future. Comparison with EPROM and EEPROM/Flash The difference between EPROM and EEPROM lies in the way that the memory programs and erases. EEPROM can be programmed and erased electrically using field emission (more commonly known in the industry as "Fowler-Nordheim tunneling").

microcontroller (configured as i/p) and other end of the switch is connected to the common ground. So whenever a key of Linear keypad is pressed, the logic on the microcontroller pin will go LOW. Matrix keypad: This keypad has keys arranged in the form of rows and columns. That is why the name Matrix keypad. According to this keypad, in order to find the key being pressed the keypad need to be scanned by making rows as input or columns as output or vice versa. This keypad is used in the places where one needs to connect more no. of keys with less no. of data lines.

completely different. First of all, it has an inside -- a normal credit card is a simple piece of plastic. The inside of a smart card usually contains an Embedded Microprocessor or EEPROM (memory) or some times both. The microprocessor is under a gold contact pad on one side of the card. Think of the microprocessor as replacing the usual magnetic stripe on a credit card or debit card. BASICS: A smart card is a plastic card with a microprocessor chip embedded in it. The card looks like a normal credit card except for its metal contact (in contact card only), but applications performed could be totally different. Other than normal credit card and bankcard functions, a smart card could act as an electronic wallet where electronic cash is kept. With the appropriate software, it could also be used as a secure access control token ranging from door access control to computer authentication. The term smart card has different meanings in different books [Guthery1998, Rankl1997] because

SMART CARD
Introduction: A smart card, chip card, or integrated circuit card (ICC), is any pocket-sized card with embedded integrated circuits which can process data or Memory. This implies that it can receive input which is processed by way of the ICC applications and delivered as an output. A smart card resembles a credit card in size and shape, but inside it is

smart cards have been used in different applications. SMART CARD: The smart card is defined as a Credit Card with a Brain on it, the brain being a small Embedded of this Computer Chip. Because

that their stored data can be protected against unauthorized access and tampering. Inside a smart card, access to the memory content is controlled by a secure logic circuit within the chip. As access to data can only is performed via a serial interface supervised by the operating system and the secure logic system, confidential data written onto the card is prevented from unauthorized external access. This secret data can only be processed internally by the microprocessor. Due to the high security level of smart cards and its off-line nature, it is extremely difficult to "hack" the value off a card, or otherwise put unauthorized information on the card. Because it is hard pocket, to get a smart the card data is without uniquely authorization, and because it fits in ones appropriate for secure and convenient data storage. Without permission of the card holder, data could not be captured or modified. Therefore, smart card could further enhance the data privacy of user. Therefore, smart card is not only a data store, but also programmable, portable, storage. SMART CARD READER: tamper-resistant memory

Embedded Brain, smart card is also known as chip or integrated circuit (IC) card. Some types of smart card may have a microprocessor embedded, while others may only have a non-volatile memory content included. In general, a plastic card with a chip embedded inside can be considered as a smart card. In either type of smart card, the storage capacity of its memory content is much larger than that in magnetic stripe cards. The total storage capacity of a magnetic stripe card is 125 bytes while the typical storage capacity of a smart card ranges from 1K bytes to 64K bytes. In other words, the memory content of a large capacity smart card can hold the data content of more than 500 magnetic stripe cards. Obviously, large storage capacity is one of the advantages in using smart card, but the single-most important feature of smart card consists of the fact

Smart Card Readers are also known as Card Programmers (because they can write to a card), card terminals, card acceptance device (CAD) or an interface device (IFD). When the smart card and the card reader come into contact, each identifies itself to the other by sending and receiving information. If the messages exchanged do not match, no further processing takes place. Working of Smart Card Reader:
Smart Card Readers are also known as card programmers (because they can write to a card), card terminals, card acceptance device (CAD) or an interface device (IFD). There is a slight difference between the card reader and the terminal. The term 'reader' is generally used to describe a unit that interfaces with a PC for the majority of its processing requirements. In contrast, a 'terminal' is a self-contained processing device. The reader provides a path for your application to send and receive commands from the card. There are many types of readers available, such as serial, PC Card, and standard keyboard models. Unfortunately, the ISO group was unable to provide a standard for communicating with the readers so there is no one-size-fits-all approach to smart card communication.

Each manufacturer provides a different protocol for communication with the reader.

First you have to communicate Second, the reader communicates the card, acting as the

with the reader.

with

intermediary before sending the data to the card.

Third, communication with a

smart card is based on the APDU format. The card will process the data and return it to the reader, which will then return the data to its originating source. The following classes are used for communicating with the reader:

ISO

command

classes

for

communicating with 7816 protocol

Classes for communicating with Classes for converting data to a An application for testing and

the reader

manufacturer-specific format

using the cards for an intended and specific purpose Communicating with a Smart Card Reader: The reader provides a path for your application to send and receive

commands from the card. There are many types of readers available, such as serial, PC Card, and standard keyboard models. Unfortunately, the ISO group was unable to provide a standard for communicating with the readers so there is no one-size-fits-all approach to smart card communication. Each manufacturer provides a different protocol for communication with the reader.

Card

patent

in

France

in

1974

[Rankl1997]. With the advances in microprocessor manufacturing technology, the development cost of the smart card has been greatly reduced. In 1984, a breakthrough was achieved when French Postal services and (PTT) Telecommunications

successfully carried out a field trial with telephone cards. Since then, smart cards are no longer tied to the traditional bankcard market even though the phone First you have to communicate with the reader.

card market is still the largest market of smart cards in 1997. Due to the establishment of the ISO7816 specification in 1987 (a worldwide smart card interface standard), the smart card format is now standardized. Nowadays, smart cards from different vendors could communicate with the host machine using a common set of language. TYPES: According to the definitions of smart card in the Smart card technology], the

Second, the reader communicates with the card, acting as the intermediary before sending the data to the card.

Third, communication with a smart card is based on the APDU format. The card will process the data and return it to the reader, which will then return the data to its originating source.

HISTORY: A Card embedded with a microprocessor was first invented by 2 German engineers in 1967. It was not publicized until Roland Moreno, a French journalist, announced the Smart

word smart card has three different meanings: IC card with ISO 7816 interface Processor IC card Personal identity token containing ICs

Basically, based on their physical characteristics, IC cards can be categorized into 4 main types, memory card, contact CPU card, contact-less card and combi card. Memory Cards: A memory card is a card with only memory and access logic onboard. Similar to the magnetic stripe card, a memory card can only be used for data storage. No data processing capability should be expected. Without the onboard CPU, memory cards use a synchronous communication mechanism between the reader and the card where the communication channel is always under the direct control of the card reader. Data stored on the card can be retrieved with an appropriate command to the card. In traditional memory cards, no security control logic is included. Therefore, unauthorized access to the memory content on the card could not be prevented. While in current memory cards, with the security control logic programmed on the card, access to the protection zone is restricted to users with the proper password only.

Contact CPU Cards: A more sophisticated version of smart card is the contact CPU card. A microprocessor is embedded in the card. With this real brain, program stored inside the chip can be executed. Inside the same chip, there are four other functional blocks: the mask-ROM, Nonvolatile memory, RAM and I/O port [HKSAR1997, Rankl1997]. Except for the microprocessor unit, a memory card contains almost all components that are included in a contact CPU card. Both of them consist of Non-volatile memory, RAM, ROM and I/O unit. Based on ISO 7816 specifications, the external appearance of these contact smart cards is exactly the same. The only difference is the existence of the CPU and the use of ROM. In the CPU card, ROM is masked with the chips operating system which executes the commands issued by the terminal, and returns the corresponding results. Data and application program codes are stored in the non-volatile memory, usually EEPROM, which could be modified after the card manufacturing stage. One of the main features of a CPU card is security. In fact, contact CPU

card has been mainly adopted for secure data transaction. If a user could not successfully authenticate him/herself to the CPU, data kept on the card could not be retrieved. Therefore, even when a smart card is lost, the data stored inside the card will not be exposed if the data is properly stored. Also, as a secure portable computer, a CPU card can process any internal data securely and outputs the calculated result to the terminal. Contact less Cards: Contact less smart card is the one in which the chip communicates with the card reader through RFID induction technology (at data rates of 106 - 848 Kbits/sec). These cards require only close proximity to an antenna to complete transaction. They are often used when transactions must be processed quickly or hands-free, such as on mass transit systems, where smart cards can be used without even removing them from a wallet. Even though contact CPU smart card is more secure than memory card, it may not be suitable for all kinds of applications, especially where massive transactions are involved, such as transportation uses. Because in

public transport uses, personal data must be captured by the reader within a short period of time, contact smart card which requires the user to insert the card to the reader before the data can be captured from the card would not be a suitable choice. With the use of radio frequency, the contact-less smart card can transmit user data from a fairly long distance within a short activation period. The card holder would not have to insert the card into the reader. The whole transaction process could be performed without removing the card from the users wallet. Contact-less smart cards use a technology that enables card readers to provide power for transactions and communications electromagnetic without signal is making used for physical contact with the cards. Usually communication between the card and the reader. The power necessary to run the chip on the card could either be supplied by the battery embedded in the card or transmitted at microwave frequencies from the reader onto the card. Contact-less card is highly suitable for large quantity of card access and data transaction. However, contact-less smart card has not been standardized. There

are about 16 different contacts-less card technologies and card types in the market [ADE]. Each of these cards has its specific advantages, but they may not be compatible with each of its other. high Nevertheless, because

expensive, the later solution is usually chosen. Sometimes, the term combi card is being misused by manufacturers. In general, there are two types of combine contact-contactless smart cards, namely the hybrid card and the combi card. Both cards have contact and contactless parts embedded together in the plastic card. However, in the hybrid card, the contact IC chip and contactless chip are separate modules. No electrical connections have been included for communications between the two chips. These two modules can be considered as separate but co-existing chips on the same card. While in the combi card, the contact and contactless chips could communicate between themselves, thus giving the combi card the capability to talk with external environment via either the contact or contactless method. As the combi cards possess the advantages of both contact and contactless cards, the only reason that is hindering its acceptance is cost. When the cost and technical obstacles are overcome, combi cards will become a popular smart card solution.

production cost and the technology is relatively new, this type of cards has not been widely adopted. Combi - Card: At the current stage, contact and contact-less smart card are using two different communication protocols and development processes. Both cards have their advantages and disadvantages. Contact smart cards have higher level of security and readily-available infrastructure, while contact-less smart card provide a more efficient and convenient transaction environment. In order to provide customers with the advantages of these two cards, two methods could be employed. The first method is to build a hybrid card reader, which could understand the protocols of both types of cards. The second method is to create a card that combines the contact functions with the contactless functions. Because the manufacturing cost of the hybrid reader is very

exist different types of SIM structures In our project the Smart Card used is of the type Contact type cards. Basically this type of Smart Cards got SIM like Structure Embedded on a Plastic card for Physical Structure and Strength. There according to the type of Application, Memory and features involved in the Smart Card. Some of them are shown below.

Types of SIM Structures These Contact type Smart cards have a contact area, comprising several goldplated contact pads, that is about 1cm square. When inserted into a reader, the chip makes contact with electrical connectors that can read information from the chip and write information back.

Electrical signal description:

Smart Card pin-out VCC: Power supply input

RST: Either used it (reset signal supplied from the interface device) or in combination with an internal reset control circuit (optional use by the card). If internal reset is implemented, the voltage supply on Vcc is mandatory. CLK: Clocking or timing signal

cards are normally well inside the telephone industry's 6mA limit. This is allowing financial card terminals to become smaller and cheaper. The reader provides a path for your application to send and receive commands from the card. There are many types of readers available, such as serial, PC-Card, and standard keyboard

(optional use by the card). GND: Ground (reference voltage). VPP: Programming voltage input (deprecated / optional use by the card). I/O: Input or Output for serial data to the integrated circuit inside the card. Contact type Smart Card Reader: Contact smart card readers are used as a communications medium between the smart card and a host, e.g. a computer, a point of sale terminal, or a mobile telephone. Since the chips in the financial cards are the same as those used for mobile phone Subscriber Identity Module (SIM) cards, just programmed differently and embedded in a different shaped piece of PVC, the chip manufacturers are building to the more demanding GSM/3G standards. So, for instance, although EMV allows a chip card to draw 50 mA from its terminal,

models. Unfortunately, the ISO group was unable to provide a standard for communicating with the readers so there is no one-size-fits-all approach to smart card communication. Each manufacturer provides a different protocol for communication with the reader.

First you have to communicate with the reader. Second, the reader communicates with the card, acting as the intermediary before sending the data to the card.

Third, communication with a smart card is based on the APDU format. The card will process the data and return it to the reader, which will then return the data to its originating source.

The following classes are used for communicating with the reader:

next-generation of multi-layer security and three-factor authentication. Another difference in reader types is onboard intelligence and capabilities. An extensive price and performance difference exists between an industrial strength reader that supports a wide variety of card protocols and the less expensive win-card reader that only works with microprocessor cards and performs all processing of the data in the PC. The options in terminal choices are just as varied. Most units have their own operating systems and development tools. They typically support other functions reading, such modem as magnetic-stripe functions and

ISO

command

classes with

for 7816

communicating protocol

Classes for communicating with the reader Classes for converting data to a manufacturer-specific format An application for testing and using the cards for an intended and specific purpose

Readers come in many forms, factors and capabilities. The easiest way to describe a reader is by the method of its interface to a PC. Smart card readers are available that interface to RS232 serial ports, USB ports, PCMCIA slots, floppy disk slots, parallel ports, infrared IRDA ports and keyboards and keyboard wedge readers. Card readers are used to read data from - and write data to - the smart card. Readers can easily be integrated into a PC utilizing Windows 98/Me, 2000, or XP platforms. However, some computer systems already come equipped with a built-in smart card reader. Some card readers come with advanced security features such as secure PIN entry, secure display and an integrated fingerprint scanners for the

transaction printing. To process a smart card the computer has to be equipped with a smart card reader

possessing

the

following

mandatory features: Smart Card Interface Standard ISO 7816 is an international standard interface that describes the for requirements

contact-type smart cards. These standards have multiple parts. For instance, part 1, 2 and 3 are applicable to card readers. Part 1

defines

the

physical

Card Contact Types refers to how the contact between a card reader and a smart card is physically made. There are two primary types of contact: landing contact and friction contact (also known as sliding or wiping). For card readers featuring friction contact, the contact part is fixed. The contact wipes on the card surface and the chip when a card is inserted. For card readers featuring the landing type, the contact part is movable. The contact "lands" on the chip after a card is wholly inserted. In general, card readers of the landing type provide better protection to the card than that of the friction type. Smart card readers are also used as smart card programmers to configure and personalize integrated circuit cards. These programmers not only read data, but also put data into the card memory. This means that not only CPU based smart cards, but also simple memory cards can be programmed using a smart card reader. Of course the card reader must support the appropriate protocol such as the asynchronous T=0, T=1 or synchronous I2C protocols.

characteristics of the card. Part 2 defines dimension and location of smart card chip contacts. Part 3 defines the electronic signals and transmission protocols of the card. Card readers may be referred to as conforming to ISO 7816 1/2/3, or in its simplified term, ISO 7816.

Driver - This refers to the software used by the operating system (OS) of a PC for managing a smart card and applicable card reader. To read a smart ID card, the driver of the card reader must be PC/SC compliant which is supported by most card reader products currently available. It should be noted that different OS would require acquiring different card drivers. readers, In the

compatibility between the driver and the OS has to be determined and ensured. Desirable Features in a Smart Card Reader:

COMMUNICATION PROTOCOLS

Name Description T=0 T=1 T=2 T=3 Asynchronous half-duplex byte-level transmission protocol. Asynchronous half-duplex block-level transmission protocol. Reserved for future full-duplex operations. Reserved for future full-duplex operations.

T=CL APDU transmission via contactless interface ISO 14443. The smart card reader here in this project used is the supports the T=0, T=1 protocols. The smart card here used is of 256 bytes of memory (SLE 4442). The following section gives the some sort of information Features: about the smart card memory and its interfacing commands. End of processing indicated at data output Answer-to-Reset acc. to ISO standard 7816-3 Programming time 2.5 ms per byte for both erasing and writing Minimum of 104 write/erase cycles1) Data retention for minimum of ten years1) Contact configuration and serial interface in accordance with ISO standard 7816 (synchronous transmission)

2568-bitEEPROM organization Byte-wise addressing Irreversible byte-wise write protection of lowest 32 addresses (Byte 0 ... 31)

32 1-bit organization of protection memory Two-wire link protocol

Pin configuration:

Pin description:

COMMAND SET FOR SLE4442 256 bytes Memory

Steps

Command Comd to SR90

Prompt from SR90 Reader

1.

Set Device Type

#0203!

#83! (Positive Ack) #8A! (Invalid Device Type set)

2.

Send Card Status

#01!

#80! (Card Present) #81! (Card Absent)

3.

ATR

#03!

#88A2131091!

4.

Read Data

#10AANN!

#87AANNDDDD! (DDD = Data) #86! (Invalid Command) #82! (No Device Type set) #8D! (Memory Over Flow)

5.

Write Data

#11AANNFFFFFF DD..D! #82! (No Device Type set ) #83! (Positive Ack) #89! (Invalid Security Code) #86! (Invalid Command) #85! (Invalid Parameters #8D! (Memory over Flow) #90!(Already Protected)

6.

Protect Data

#12AANNFFFFFF DD! #83! (Positive Ack) #82! (No Device Type) #89! (Invalid Security Code) #86! (Invalid Command) #85! (Invalid Parameters #8D! (Memory Over Flow)

7. Change Security Code #53FFFFFF555555

#83! (Positive Ack) #89! (Invalid Security Code)

#86! (Invalid Command) #85! (Invalid Parameters 8. Locations Which cant write : 0,1,2,3,6,7

9.

Communication Protocol:

Baud Rate

:9,600 bps

Parity

:None

Stop Bit

:1

Start Bit

:0

Data

:8 bits

AA NN FFFFFF DD

= = = =

Address location of the chip in Hex Number of bytes to read or to write Security Code Data to read /write or protect in BCD format

Note: Please give correct security code while writing your cards other wise they will damage. This card will allow 3 times of writing false security code later it wont accept to write the card but you can read. In our project, the Smart Card Reader communicates with microcontroller through 2 pins namely RX and TX with the help of a Serial Driver. These 2 pins are pin 2, 3 of the 9-pin connector of Smart Card Reader.

With the rapid expansion of Internet technology and electronic commerce, smart cards are now more widely accepted in the commercial market as stored-value and secure storage cards. Moreover, it has also been widely used as an identity card. The smart card has also been used in transportation such as the Octopus card which has been adopted by the MTRC and KCRC to replace of the old Magnetic stripe card. Medical record can also be stored in the smart card. This enables critical information of the patient to be retrieved whenever it is required. With the help of smart card technology, many secure data such as the computer login name and password can also be kept, so user need not remember a large number of passwords. The applications can be classified into 6 main categories: Electronic Payment, Security Loyalty and Authentication, Telecommunications, Transportation, Applications. 1. ELECTRONIC PAYMENT:

Program and Health Care

SMART CARD READER

APPLICATIONS:

Electronic Purse: The Electronic Purse is also known as electronic cash. Funds can be loaded onto a card for use as cash. The electronic cash can be used for small purchases without necessarily requiring the authorization of a PIN. The card is credited from the cardholders bank account or some other ways. When it is used to purchase goods or services, electronic value is deducted from the card and transferred to the retailers account. Similar to a real wallet, the cardholder could credit his/her card at the bank any time when required. Stored Value Cards: Another use of smart cards in electronic commerce is Electronic token. It is an example of the stored-value card. The principle is that some memory in the smart card is set aside to store electronic tokens or electronic tickets. A smart card can store tokens for different services and each of the tokens can be refilled, depending on the types of the memory card. This allows the cost to be distributed over a number of services and over a much longer life span. For example, the card could be used to pay for gas and instead of putting coins

in a parking meter. Consumers load up the card from a vending machine. 2. SECURITY AUTHENTICATION: Cryptographic uses: From the point-of-view of the supplier and system operator, the main requirement of almost all machinereadable card systems is to ensure that the card presented is valid and the cardholder is indeed the person entitled to use that particular card. To verify the cardholders identity, users are required to enter their PIN code (personal identification number). This PIN code is kept in the card rather than on the terminals or host machines. Identification terminal. Identity card: The identification of an individual is one of the most complex processes in the field of Information Technology. It requires both the individual to identify himself and for the system to recognize the incoming connection is generated by a legal user. The system then accepts responsibility for allowing all and authentication procedures take place at the card AND

subsequent knowledge of the system.

actions, that

sage the

in

the has

identify

whether

the

user

is

the

user

authorized cardholder. The card can also be individually personalized to allow access to limited facilities, depending on the holders security clearance. A log of the holders movements, through a security system, can be stored on the card as a security audit trail Digital certificate: The most important security measures we encounter in our daily business have nothing to do with locks and guards. A combination of a signed message and the use of public key cryptosystem, so called digital signature, are typically used. A digitally signed message containing a public key is called a certificate. In addition to a public key, a certificate typically contains a name, address, and other information describing the holder of the corresponding secret key. All of these carry the digital signature of a registry service that records public keys for all members of the community. To become a member of this community, a subscriber must do two things: Provide the directory service with a public key and the associated identification information so that

authorization to do whatever he is asking If a smart card is used, the information stored on the card can be verified locally against a password or PIN before connection is made to the host. This prevents the password from being eavesdropped by perpetrators on the Internet. Some of the smart cards will have personal data stored on the card. For example, the cardholders name, ID number, and date of birth Access control card: The most common devices used to control access to private areas where sensitive work is being carried out or where data is held, are keys, badges and magnetic cards. These all have the same basic disadvantages: they can easily be duplicated and when stolen or passed on, they can allow entry by an unauthorized person. The smart card overcomes these weaknesses by being very difficult to be reproduced and capable of storing digitized personal characteristics. With suitable verification equipment, this data can be used at the point of entry to

other people will be able to verify his/her signature. Obtain the public key of the directory service so that he/she can verify other peoples signatures. Because certificates are extremely

be done on the card without the need for hard wiring the access points to a central computer. The identification of a user is usually done by means of a (Personal Identification Number) PIN. The PIN is verified by the microcomputer of the card with the PIN stored in its RAM. If the comparison is negative, the CPU will refuse to work. The chip also keeps tack of the number of consecutive wrong PIN entries. If this number reaches a pre-set threshold, the card blocks itself against any further use. TRANSPORTATION APPLICATIONS: The smart card can act as electronic money for car drivers who would need to pay a fee before being able to use a road or tunnel. It would then contain a balance that can be increased at payment stations or in the pre-paid process, and is decreased for each use.

tamper resistant, the authenticity of a certificate is a property of the certificate itself, rather than of the authenticity of the channel over which it was received. Computer login: Access to the Computer room and its services can be controlled by the smart card. In terms of network access, smart card can authenticate the user to the host. Furthermore, depending on the environment being protected the network access card can also perform the following functions: Manipulation levels of security. Use of biometric techniques as an added security measure. Maintaining an audit trail of failures and attempted violations. of different authentication codes for different

TELECOMMUNICATION Meanwhile, in terms of access to the computer room itself, PIN checking can APPLICATIONS:

Since 1988, smart card has become an essential component in cellular phone systems. Network data, subscribers information and all mobile network critical data are kept inside the card. With this card, subscribers could make calls from any portable telephone. Moreover, through the IC card, any calls through the mobile phone could be encrypted, and thus ensure privacy. In the future, more and more value-added services, such as electronic banking, could be supported by using this microprocessor card. HEALTH CARE APPLICATIONS: Due to the level of security provided for data storage, IC cards offer a new perspective for healthcare applications. Medical applications of smart cards can be used for storing information including personal data, insurance policy, emergency medical information, hospital admission data and recent medical records. LOYALTY APPLICATIONS: Loyalty program is another important application of smart cards in the shopping model. The preferred customer status together with detailed information on shopping habits is stored

and processed on the smart card. With this information, merchants could derive better shopping model or tailor-make personalized customer shopping profiles. In addition, this shopping habit profile is kept in the customers card; therefore, his/her shopping record could be kept confidential from unauthorized access.

REGULATED POWER SUPPLY The power supplies are

designed to convert high voltage AC mains electricity to a suitable low voltage supply for electronics circuits and other devices. A RPS (Regulated Power Supply) is the Power Supply with Rectification, Filtering and Regulation being done on the AC mains to get a Regulated power supply for Microcontroller and for the other devices being interfaced to it. A power supply can by broken down into a series of blocks, each of which performs a particular function. A d.c power supply which maintains the output voltage constant irrespective of a.c mains fluctuations or load variations is known as Regulated D.C Power Supply

For example a 5V regulated power supply system as shown below:

Transformer: A transformer is an electrical device which is used to convert electrical power from one Electrical circuit to another frequency. Transformers convert AC electricity from one voltage to another with little loss of power. Transformers work only with AC and this is one of the reasons why mains electricity is AC. without change in

Step-up transformers increase in output voltage, step-down transformers decrease in output voltage. Most power supplies use a step-down transformer to reduce the dangerously high mains voltage to a safer low voltage. The input coil is called the primary and the output coil is called the secondary. There is no electrical connection between the two coils; instead they are linked by an alternating magnetic field created in the

soft-iron core of the transformer. The two lines in the middle of the circuit symbol represent the core. Transformers waste very little power so the power out is (almost) equal to the power in. Note that as voltage is stepped down current is stepped up. The ratio of the number of turns on each coil, called

the turns ratio, determines the ratio of the voltages. A step-down transformer has a large number of turns on its primary (input) coil which is connected to the high voltage mains supply, and a small number of turns on its secondary (output) coil to give a low output voltage.

An Electrical Transformer Turns ratio = Vp/ VS = Np/NS Power Out= Power In VS X IS=VP X IP Vp = primary (input) voltage Np = number of turns on primary coil Ip = primary (input) current RECTIFIER: 2. Bridge type full bridge A circuit which is used to convert a.c to dc is known as rectifier. Half wave Rectifier Full wave rectifier 1. Centre tap full wave rectifier. RECTIFIER. The process of conversion a.c to d.c is called rectification. TYPES OF RECTIFIERS:

Comparison of rectifier circuits: Type of Rectifier Parameter Number of diodes 1 PIV of diodes Vm 2Vm Vm 2 4 Half wave Full wave Bridge

D.C output voltage

Vm/

2Vm/

2Vm/

Vdc,at no-load

0.318Vm

0.636Vm

0.636Vm

Ripple factor Ripple frequency Rectification efficiency Transformer Utilization Factor(TUF) RMS voltage Vrms

1.21

0.482

0.482

2f

2f

0.406

0.812

0.812

0.287

0.693

0.812

Vm/2

Vm/2

Vm/2

Full-wave Rectifier: From the above comparison we came to know that full wave bridge rectifier as more advantages than the other two rectifiers. So, in our project we are using full wave bridge rectifier circuit.

Bridge Rectifier: A bridge rectifier makes use of four diodes in a bridge arrangement to achieve full-wave rectification. This is a widely used configuration, both with individual diodes wired as shown and with single component bridges where the diode bridge is wired internally. A bridge rectifier makes use of four diodes in a bridge arrangement as shown in fig (a) to achieve full-wave rectification. This is a widely used configuration, both with individual diodes wired as shown and with single component bridges where the diode bridge is wired internally.

Fig (A)

Operation: During positive half cycle of secondary, the diodes D2 and D3 are in

forward biased while D1 and D4 are in reverse biased as shown in the fig(b).

The current flow direction is shown in the fig (b) with dotted arrows.

Fig (B) During negative half cycle of secondary voltage, the diodes D1 and D4 are in forward biased while D2 and D3 are in reverse biased as shown in the fig(c). The current flow direction is shown in the fig (c) with dotted arrows.

Fig(C) Filter: A Filter is a device which removes the a.c component of rectifier

output but allows the d.c component to reach the load Capacitor Filter: We have seen that the ripple content in the rectified output of half wave rectifier is 121% or that of full-wave or bridge rectifier or bridge rectifier is 48% such high percentages of ripples is not acceptable for most of the applications. Ripples can be removed by one of the following methods of filtering. (a) A capacitor, in parallel to the load, provides an easier by pass for the ripples voltage though it due to low impedance. At ripple frequency and leave the D.C. to appear at the load. (b) An inductor, in series with the load, prevents the passage of the ripple current (due to high impedance at ripple frequency) while allowing the d.c (due to low resistance to d.c) (c) Various combinations of capacitor and inductor, such as L-section filter section filter, multiple section filter etc. which make use of both the properties mentioned in (a) and (b) above. Two cases of capacitor filter, one applied on half wave rectifier and another with full wave rectifier. large

Filtering is performed by a value electrolytic capacitor connected across the DC supply to act as a reservoir, supplying current to the output when the varying DC voltage from the rectifier is falling. The capacitor charges quickly near the peak of the varying DC, and then discharges as it supplies current to the output. Filtering significantly increases the average DC voltage to almost the peak value (1.4 RMS value). To calculate the value of capacitor(C), C = *3*f*r*Rl Where, f = supply frequency, r = ripple factor, Rl = load resistance. Note: In our circuit we are using 1000F hence large value of capacitor is placed to reduce ripples and to improve the DC component. Regulator: Voltage regulator ICs is available with fixed (typically 5, 12 and 15V) or variable output voltages. The maximum current they can pass also rates them. Negative voltage regulators are available, mainly for use in dual supplies. Most regulators include some automatic protection from excessive

current

('overload

protection')

and

effective output impedance improvement of two orders of magnitude, lower quiescent current. The LM78XX is available in the TO-252, TO-220 & TO263packages. Features: Output Current of 1.5A.

overheating ('thermal protection'). Many of the fixed voltage regulators ICs have 3 leads and look like power transistors, such as the 7805 +5V 1A regulator shown on the right. The LM7805 is simple to use. You simply connect the positive lead of your unregulated DC power supply (anything from 9VDC to 24VDC) to the Input pin, connect the negative lead to the Common pin and then when you turn on the power, you get a 5 volt supply from the output pin.

Output Voltage Tolerance of 5%. Internal thermal overload protection. Internal Short-Circuit Limited. Output Voltage 5.0V, 6V, 8V, 9V, 10V, 12V, 15V, 18V, 24V.

Buzzer:
The "Piezoelectric sound components" introduced herein operate on

Fig 6.1.6 A Three Terminal Voltage Regulator 78XX: The Bay Linear LM78XX is integrated linear positive regulator with three terminals. The LM78XX offer several fixed output voltages making them useful in wide range of applications. When used as a zener diode/resistor combination replacement, the LM78XX usually results in an

an innovative principle utilizing natural oscillation of piezoelectric ceramics. These buzzers are offered in lightweight compact sizes from the smallest diameter of 12mm to large Piezo electric sounders. Today, piezoelectric sound components are used in many ways such as home appliances, OA equipment, audio equipment telephones, etc. And they are applied widely, for example, in alarms, speakers, telephone ringers, receivers, transmitters, beep sounds, etc.

piezoelectric diaphragm. A piezoelectric diaphragm consists of a piezoelectric ceramic plate which has electrodes on both sides and a metal plate (brass or stainless steel, etc.). A piezoelectric ceramic plate is attached to a metal plate with adhesives. Fig. 2 shows the oscillating system of a piezoelectric diaphragm. Applying D.C. voltage between electrodes of a piezoelectric diaphragm causes mechanical distortion due FIG: Types of Buzzers to the piezoelectric effect. For a misshaped piezoelectric element, the distortion of the piezoelectric element expands in a radial direction. And the piezoelectric diaphragm bends toward the direction shown in Fig.2 (a). is a

Oscillating System:
Basically, the sound source of a piezoelectric sound component

The metal plate bonded to the piezoelectric element does not expand. Conversely, when the piezoelectric element shrinks, the piezoelectric diaphragm bends in the direction shown in Fig.2 (b). Thus, when AC voltage is applied across electrodes, the bending shown in Fig.2 (a)

and Fig.2 (b) is repeated as shown in Fig.2 (c), producing sound waves in the air. DESIGN PROCEDURES: In general, man's audible frequency range is about 20 Hz to 20kHz. Frequency ranges of 2kHz to 4kHz are most easily heard. For this reason, most piezoelectric

sound components are used in this frequency range, and the resonant frequency (f0) is generally selected in the same range too. As shown in Fig. 3, the resonant frequency depends on methods used to support the

piezoelectric diaphragm. If piezoelectric diaphragms are of the same shape, their values will become smaller in the order of (a), (b) and (c).

In

general,

the

piezoelectric

Communication is done via protocols and you can read and write to a fixed address on the card. The main objective of this

diaphragm is installed in a cavity to produce high sound pressure. The resonant frequency (fcav) of the cavity in is obtained from Formula (1) (Helmholtz's Formula). Since the piezoelectric diaphragm and cavity have proper resonant frequencies, (f0) and (fcav) respectively, sound pressure in specific frequencies can be increased and a specific bandwidth can be provided by controlling both positions.

project is anti-rigging voting system which is implemented using smart card technology. A smart card is used as a voter id card which provides authentication and identification for a person. In this project microcontroller is used which forms the control unit. Every citizen of India is given with a smart card. Whenever user wants to vote he needs to insert his smart card in smart

Circuit Description: The Smart Card Reader is an electronic device that reads smart cards.

card reader while voting. Then the voter is asked to vote for his favorite candidate through keypad. So, user need to press the key corresponding to his favorite candidate. This system even allows the election commission to see the no. of

votes given for each candidate and is displayed in LCD which got interfaced to microcontroller. This project finds its place in places where one wants to provide authentication with great security.

SOFTWARE:
Software components: About Keil:

1. 2.

Click on the Keil u Vision Icon on Desktop The following fig will appear

3. 4.

Click on the Project menu from the title bar Then Click on New Project

5.

Save the Project by typing suitable project name with no extension in u r own folder sited in either C:\ or D:\

6. 7. 8.

Then Click on Save button above. Select the component for u r project. i.e. Atmel Click on the + Symbol beside of Atmel

9.

Select AT89C51 as shown below

10. 11.

Then Click on OK The Following fig will appear

12. Then Click either YES or NOmostly NO. 13. Now your project is ready to USE. 14.
Now double click on the Target1, you would get another option Source group 1 as shown in next page.

15. Click on the file option from menu bar and select new.

16.

The next screen will be as shown in next page, and just maximize it by double clicking on its blue boarder.

17. 18.

Now start writing program in either in C or ASM For a program written in Assembly, then save it with extension . asm and for C based program save it with extension .C

19.

Now right click on Source group 1 and click on Add files to Group Source

20.

Now you will get another window, on which by default C files will appear.

21. 22.

Now select as per your file extension given while saving the file Click only one time on option ADD

23.

Now Press function key F7 to compile. Any error will appear if so happen.

24. 25.

If the file contains no error, then press Control+F5 simultaneously. The new window is as follows

26.

Then Click OK

27.

Now Click on the Peripherals from menu bar, and check your required port as shown in fig below

28.

Drag the port a side and click in the program file.

29. 30.

Now keep Pressing function key F11 slowly and observe. You are running your program successfully

CONCLUSION The project DEVELOPMENT OF ANTI-RIGGING VOTING SYSTEM has been successfully designed and tested. It has been developed by integrating features of all the hardware components used. Presence of every module has been reasoned out and placed carefully thus contributing to the best working of the unit. Secondly, using highly advanced ICs and with the help of growing technology the project has been successfully implemented. Finally we conclude that DEVELOPMENT OF ANTI-RIGGING VOTING SYSTEM is an emerging field and there is a huge scope for research and development. FUTURE ENHANCEMENT: The present project can be further enhanced by providing more security like with finger print module, IRIS etc,

Bibliography

The 8051 Micro controller and Embedded Systems -Muhammad Ali Mazidi Janice Gillispie Mazidi The 8051 Micro controller Architecture, Programming & Applications-Kenneth J.Ayala Fundamentals Of Micro processors and Micro computers -B.Ram Micro processor Architecture, Programming & Applications-Ramesh S. Gaonkar Electronic Components-D.V. Prasad Wireless Communications- Theodore S. Rappaport Mobile Tele Communications-William C.Y. Lee

References on the Web: www.national.com www.atmel.com www.microsoftsearch.com www.geocities.com