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Plot 57A, B & C, Noida Special Economic Zone (NSEZ) Noida, 201305 India Phone: +91.120.3984000 / +91.120.4308300 Fax: 91.120.2568138, 2562231 Web site: www.cadence.com/in India Regional Offices Cadence Design Systems India Pvt Ltd. 2nd Floor, 3B Building, RMZ Ecospace Sarjapur Outer Ring Road Bangalore 560 037 India Phone: +91.80.4184.1111, 6620.1111 Fax: +91.80.4184.1122, 4520.1122 Cadence Design Systems India Pvt Ltd. Suite 702, Aditya Trade Centre Ameerpet Hyderabad - 500038 India Phone: +91-40-2374 0052
Introduction
Talent is of essence in a knowledge-intensive sector like electronic design. India produces a large number of electronics and computer science graduate engineers every year. However, while there is no dearth of manpower, the challenge is finding design aware engineers who are trained specifically in VLSI design and can ramp up quickly. Simply put, the industry is facing a quality gap with regard to talent. Getting fresh graduates ramped up quickly to productivity is a key concern across the industry ecosystem. Several companies have already taken these and other steps to give students real-life experience before they graduate, thereby lessening ramp up time when they enter the industry. When Cadence established its Indian presence over 20 ago, we realized early on the need to nurture and develop
the countrys talent pool through public-private partnerships at various levels. Some of them are mentioned here.
2006
Design and Implementation of Low Cost Power Optimised OTA Based FPAA in 0.35um Mixed-Mode CMOS Process Design & Implementation Of An On-Chip Single Inductor Triple Output DC-DC Buck Converter Reconfigurable Floating Point Unit
Winner
2007
IIT Kharagpur
Winner
2007
I2IT Pune
Runner Up
2008
IIIT Hyderabad
Design of a Low Power Variable-Resolution Flash Type- ADC Low Power AES Crypto Engine With Resistance to DPA Attacks
Winner
2008
VESIT Mumbai
Runner Up
2009
IIT Delhi
Winner
2009
Control Scheme for 1.8V, 2MHz Buck Converter Using Type II PI Controller
Runner Up
2010
IIT Kharagpur
Low Power and High Speed Realization of Modified Fast Radon Transform using FFT
Winner - Master's
IFFT ASIC Implementation of High Speed Vedic CoProcessor Incorporated With a 32 Bit Processor Executing RISC Instruction Set Architecture
Category
2010
VESIT Mumbai
2010
IIT Bombay
General Purpose Ultra Energy Efficient Programmable Analog Signal Conditioning IC ASIC Chip Development of Inverse Delayed Function Model of Neuron
2010
Jadavpur University