LEC-03 Preliminaries

22

LEC-03: Details of Process Execution

Lecture Notes Sections: 1.6 1.6.3

University of Waterloo Dept of Electrical and Computer Engineering E&CE 427 Digital Systems Engineering 2003t1Winter

Schedule wk-01 05

..................................................................................... . VHDL Design and Optimization wk-01 Overview and VHDL wk-02 VHDL Semantics wk-03 Dataow Diagrams; State Machines wk-04 Memory Design; Example Design wk-05 Optimizations Functional Validation Performance Analysis, Prediction, and Optimization Timing Analysis Power Analysis and Reduction Faults and Testing Review

wk-06 wk-07 wk-08 wk-08 10 wk-11 12 wk-13

Overview

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This lecture relates fragments of VHDL code to the basic building blocks of hardware: ip-ops, Boolean gates, arithmetic circuits, etc. The semantics of VHDL are behavioural, not structural, but by understanding the behavioural semantics of VHDL we can derive the relationship between VHDL code and netlists.

Concepts

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Lecture Notes: Sections 1.61.6.3

temporal granularities process modes simulation cycle simulation step

delta cycle simulation round provisional assignment

LEC-03:

1.6

DETAILS OF PROCESS EXECUTION

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1.6
1.6.1
1.6.1.1

Details of Process Execution

Denitions and Algorithm
Temporal Granularities of Simulation

This begins our discussion of the behaviour and execution of processes. There are several different granularities of time to analyze VHDL behaviour. In this course, we will discuss three major granularities: clock cycles, timing simulation, and delta cycles. clock-cycle smallest unit of time is a clock cycle combinational logic has zero delay ip-ops have a delay of one clock cycle used for simulation early in the design cycle fastest simulation run times

timing simulation smallest unit of time is a nano, pico, or fempto second combinational logic and wires have delay as computed by timing analysis tools ip-ops have setup, hold, and clock-to-Q timing parameters used for simulation when ne-tuning design and conrming that timing contraints are satised slow simulation times for large circuits

delta cycles units of time are artifacts of VHDL semantics and simulation software simulation cycles, delta cycles, and simulation steps are inntesimaly small amounts of time VHDL semantics are dened in terms of these concepts

In assignments and exams, you will need to be able to simulate VHDL code at each of the three different levels of temporal granularity. In the laboratories and project, you will use simulation programs for both clock-cycle simulation and timing simulation. We dont have access to a program that will produce deltacycle waveforms, but if anyone is looking for a challenging co-op job or fourth-year design project.... For the remainder of section 1.6, well look at only the delta cycle view of the world.

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1.6.1.2

1.6.1

Denitions and Algorithm

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Process Modes

Each process is in one of the following modes: active, suspended, or postponed. NOTE: postponed This use of the word postponed differs from that in the VHDL Standard. We wont be using postponed processes as dened in the Standard. Suspended

active
s su e

at

Nothing to currently execute A process stays suspended until the event that it is waiting for occurs: either a change in a signal on its sensitivity list or the condition in a wait statement Postponed

pe

tiv

nd

ac

postponed resume

suspended

Wants to execute, but not currently active A process becomes active when the simulator chooses it from the pool of postponed processes Active

Currently executing A process stays active until it hits a wait statement or completes the execution of the last statement in the process, at which point it suspends Figure 1.15: Process modes

1.6.1.3

Simulation Algorithm

The algorithm presented here is a simplication of the actual algorithm in Section 12.6 of the VHDL Standard. The most signicant simplication is that this algorithm does not support delayed assignments. To support delayed assignments, each signals provisional value would be generalized to an event wheel, which holds provisional assignments for multiple times in the future. A somewhat ironic note, only six of the two hundred pages in the VHDL Standard are devoted to the semantics of executing processes.

Initialization

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Simulations start at step 6 with all processes postponed and all signals with a default value (U for std logic).

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1.6.1

Denitions and Algorithm

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The Algorithm

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1. All processes are suspended. 2. Each process looks at the signals that changed value and checks its sensitivity list or wait condition to see if it should resume 3. Update signals with their provisional values 4. Resume all suspended processes whose sensitivity list changed or wait condition became true. 5. If there are no postponed processes, then simulation time increments to the next scheduled event and the simulation continues at Step 1. 6. While there are postponed processes: (a) Pick one or more postponed processes to become active. (b) As a process executes, assignments to signals are provisional new values do not become visible until step 3 in the next simulation cycle (c) A process runs until it hits its sensitivity list or a wait statement, at which point it suspends. (d) Processes that become suspended stay suspended until there are no more postponed or active processes. 7. Calculate the new simulation time: If zero-delay assignments were made in the current simulation cycle then simulation time does not advance else simulation time is set to time of next scheduled event NOTE: Parallel execution In n-threaded execution, at most n processes are active at a time

1.6.1.4

Delta-Cycle Denitions

Denition simulation step: Executing one sequential assignment.

Denition simulation cycle: The operations that occur between the time when all processes are suspended, until all are suspended again.

Denition delta cycle: A simulation cycle that does not advance simulation time. Equivalently: A simulation cycle with zero-delay assignments.

Denition simulation round: A sequence of simulation cycles that all have the same simulation time. Equivalently: a contiguous sequence of delta cycles.

NOTE: Ofcial and unofcial terminology Simulation cycle and delta cycle are ofcial denitions in the VHDL Standard. Simulation step and simulation round are not standard denitions. They are used in E&CE 427 because we need words to associate with the concepts that they describe.

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1.6.2

Example: Process Execution

26

1.6.2

Example: Process Execution

entity bamboozle is begin port ( a, b : in std_logic; e : out std_logic ); end bamboozle; architecture main of bamboozle is signal c, d : std_logic; begin procA : process (a, b) begin c <= a AND b; end process; procB : process (b, c, d) begin d <= NOT c; e <= b AND d; end process; end main;

Figure 1.16: Example circuit for process execution In simulation run, a and b are external inputs with the following scheduled events: a: (0 at 0 ns), (1 at 10 ns), (0 at 15 ns) b: (1 at 0 ns), (0 at 12 ns)

In this example, we will treat the external inputs as if they were driven by an external process. Additional material in slides

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1.6.2

Example: Process Execution

27

process mode (S=suspended, P=postponend A=active) simulation-step pointer (one per process) P procA: process (a, b) begin c <= a AND b; end process; procB: process (b, c, d) begin d <= NOT c; e <= b AND d; end process; 0ns procC: process begin a <= 0; b <= 1; a U wait for 10 ns; b U a <= 1; wait for 2 ns; c U b <= 0; d U wait for 3 ns; e U a <= 0; end process; visible-assignment value

U a U b Uc Ud U e

Legend initial values simulation step

Step 6: Initial conditions (Shown in slides, not in notes) Step 6(a): Activate procA (Shown in slides, not in notes)
A P procA: process (a, b) begin c <= a AND b; end process; procB: process (b, c, d) begin d <= NOT c; e <= b AND d; end process; 0ns procC: process begin a <= 0; a U b <= 1; wait for 10 ns; b U a <= 1; c U U wait for 2 ns; b <= 0; d U wait for 3 ns; e U a <= 0; end process;
U a U b UUc Ud U e

Step 6(b): Provisional assignment to c

LEC-03:

1.6.2

Example: Process Execution

Step 6(c): Suspend procA (Shown in slides, not in notes) Step 6(a): Activate procC (Shown in slides, not in notes) Step 6(b): Provisional assignment to a (Shown in slides, not in notes) Step 6(b): Provisional assignment to b (Shown in slides, not in notes)

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procA: process (a, b) begin c <= a AND b; end process; procB: process (b, c, d) begin d <= NOT c; e <= b AND d; end process; 0ns procC: process begin a <= 0; a U b <= 1; wait for 10 ns; b U a <= 1; c U U wait for 2 ns; b <= 0; d U wait for 3 ns; e U a <= 0; end process;

0U a 1U b UUc Ud U e

Step 6(c): Suspend procC

Step 6(a): Activate procB (Shown in slides, not in notes) Step 6(b): Provisional assignment to d (Shown in slides, not in notes) Step 6(b): Provisional assignment to e (Shown in slides, not in notes) Step 6(c): Suspend procB (Shown in slides, not in notes) All processes suspended; End of simulation cycle (Shown in slides, not in notes) Step 7: Simulation time remains at 0 ns (Shown in slides, not in notes)

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S

1.6.2

Example: Process Execution

29

procA: process (a, b) begin c <= a AND b; 0U UUc UUd end process; a UU procB: process (b, c, d) begin 1U d <= NOT c; b e <= b AND d; end process; 0ns 0ns procC: process begin a <= 0; a U b <= 1; wait for 10 ns; b U a <= 1; c U wait for 2 ns; b <= 0; d U wait for 3 ns; e U a <= 0; end process; Step 1: Beginning of next simulation cycle Note: First simulation cycle compacted into two columns. This is done only in this example to save space and is not standard practice.

procA: process (a, b) begin c <= a AND b; 0U UUc UUd end process; a UU procB: process (b, c, d) begin 1U d <= NOT c; b e <= b AND d; end process; 0ns 0ns procC: process begin a <= 0; a U b <= 1; wait for 10 ns; b U a <= 1; c U wait for 2 ns; b <= 0; d U wait for 3 ns; e U a <= 0; end process; Step 2: Check sensitivity lists for changes

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1.6.2

Example: Process Execution

30

procA: process (a, b) begin c <= a AND b; 0 end process; a Uc Ud procB: process (b, c, d) begin 1 d <= NOT c; b e <= b AND d; end process; 0ns 0ns procC: process begin a <= 0; a U b <= 1; wait for 10 ns; b U a <= 1; c U wait for 2 ns; b <= 0; d U wait for 3 ns; e U a <= 0; end process; Step 3: Update signal values

U e

Step 4: Resume procA and procB (Shown in slides, not in notes) Step 6(a): Activate procA (Shown in slides, not in notes) Step 6(b): Provisional assignment to c (Shown in slides, not in notes) Step 6(c): Suspend procA (Shown in slides, not in notes) Step 6(a): Activate procB (Shown in slides, not in notes) Step 6(b): Provisional assignment to d (Shown in slides, not in notes) Step 6(b): Provisional assignment to e (Shown in slides, not in notes) Step 6(c): Suspend procB (Shown in slides, not in notes)
S procA: process (a, b) begin c <= a AND b; 0 end process; a 0Uc UUd UU procB: process (b, c, d) begin e 1 d <= NOT c; b e <= b AND d; end process; 0ns 0ns 0ns procC: process begin a <= 0; a U b <= 1; wait for 10 ns; b U a <= 1; c U wait for 2 ns; b <= 0; d U U wait for 3 ns; e U U a <= 0; end process; Step 7: All processes suspended; end of simulation cycle

LEC-03:

1.6.2

Example: Process Execution

Step 1: Begin next simulation cycle (Shown in slides, not in notes)

31

procA: process (a, b) begin c <= a AND b; 0 end process; a 0Uc UUd UU procB: process (b, c, d) begin 1 d <= NOT c; b e <= b AND d; end process; 0ns 0ns 0ns procC: process begin a <= 0; a U b <= 1; wait for 10 ns; b U a <= 1; c U wait for 2 ns; b <= 0; U d U wait for 3 ns; U e U a <= 0; end process; Step 2: Check sensitivity lists for changes

Step 3: Update signal values (Shown in slides, not in notes) Step 4: Resume procB (Shown in slides, not in notes) Step 6(a): Activate procB (Shown in slides, not in notes) Step 6(b): Provisional assignment to d (Shown in slides, not in notes) Step 6(b): Provisional assignment to e (Shown in slides, not in notes) Step 6(c): Suspend procB (Shown in slides, not in notes) Step 7: All processes suspended; end of simulation cycle (Shown in slides, not in notes)

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1.6.2

Example: Process Execution

Step 1: Begin next simulation cycle (Shown in slides, not in notes)

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procA: process (a, b) begin c <= a AND b; 0 end process; a 0c 1Ud UU procB: process (b, c, d) begin 1 d <= NOT c; b e <= b AND d; end process; 0ns 0ns 0ns 0ns procC: process begin a <= 0; a U b <= 1; wait for 10 ns; b U a <= 1; c U wait for 2 ns; b <= 0; U d U wait for 3 ns; U U e U a <= 0; end process; Step 2: Check sensitivity lists for changes

Step 3: Update signal values (Shown in slides, not in notes) Step 4: Resume procB (Shown in slides, not in notes) Step 6(a): Activate procB (Shown in slides, not in notes) Step 6(b): Provisional assignment to d (Shown in slides, not in notes) Step 6(b): Provisional assignment to e (Shown in slides, not in notes) Step 6(c): Suspend procB (Shown in slides, not in notes)
S procA: process (a, b) begin c <= a AND b; 0 end process; a 0c 1d 1 procB: process (b, c, d) begin e 1 d <= NOT c; b e <= b AND d; end process; 0ns 0ns 0ns 0ns 0ns 10ns procC: process begin a <= 0; a U b <= 1; wait for 10 ns; b U a <= 1; c U wait for 2 ns; b <= 0; d U U wait for 3 ns; e U U U a <= 0; end process; simulation round Step 7: No changes to "sensitized" signals --- time advances

LEC-03:

1.6.2

Example: Process Execution

Step 1: Begin next simulation cycle (Not shown) Step 2: Check sensitivity lists for changes (Not shown) Step 3: Update signal values (Not shown) Step 4: Resume procC (Shown in slides, not in notes) Step 6(a): Activate procC (Shown in slides, not in notes) Step 6(b): Provisional assignment to a (Shown in slides, not in notes)

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procA: process (a, b) begin c <= a AND b; 10 a 0c 1d end process; 1 procB: process (b, c, d) begin e 1 d <= NOT c; b e <= b AND d; end process; 0ns 0ns 0ns 0ns 0ns 10ns procC: process begin a <= 0; a U b <= 1; wait for 10 ns; b U a <= 1; c U wait for 2 ns; b <= 0; d U U wait for 3 ns; e U U U a <= 0; end process; Step 6(c): Suspend procC; end of simulation cycle

LEC-03:

1.6.2

Example: Process Execution

Step 1: Begin next simulation cycle (Not shown)

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procA: process (a, b) begin c <= a AND b; 10 0c 1d end process; a 1 procB: process (b, c, d) begin 1 d <= NOT c; b e <= b AND d; end process; 0ns 0ns 0ns 0ns 0ns 10ns procC: process begin a <= 0; a U b <= 1; wait for 10 ns; b U a <= 1; c U wait for 2 ns; b <= 0; U d U wait for 3 ns; U U e U a <= 0; end process; Step 2: Check sensitivity lists for changes

Step 3: Update signal values (Shown in slides, not in notes) Step 4: Resume procA (Shown in slides, not in notes)

Note and Questions

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NB: If a signal is updated with the same value it had in the previous simulation cycle, then it does not change, and therefore does not trigger processes to resume.

Question: What are the different granularities of time that occur when doing delta-cycle simulation?

Answer: simulation step, simulation cycle, delta cycle, simulation round

Question: What is the order of granularity, from nest to coarsest, amongst the different granularities related to delta-cycle simulation?

Answer: same order as listed just above

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1.6.3

Example: Need for Provisional Assignments

35

1.6.3

Example: Need for Provisional Assignments

This is an example of processes where updating signals during a simulation cycle leads to different results for different process execution orderings.
architecture main of flotsam is begin p_c: process (a, b) begin c <= a AND b; end process; p_d: process (a, c) begin d <= a XOR c; end process; end main;

a c b

Figure 1.17: Circuit to illustrate need for provisional assignments

1. Start with all signals at 0. 2. Simultaneously change to a = 1 and b = 1. . .

If assignments are not visible within same simulation cycle (correct: i.e. provisional assignments are used)

p_c p_d a b c d
0 0 0 0

P A P

S A S P A S

p_c p_d a b c d
0 0 0 0

P P A S

S P A S

If p c is scheduled before p d, then d will have a 1 pulse.

If p d is scheduled before p c, then d will have a 1 pulse.

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1.6.3

Example: Need for Provisional Assignments

36 .

If assignments are visible within same simulation cycle (incorrect)

p_c p_d a b c d
0 0 0 0

P A P

S A S P A S

p_c p_d a b c d
0 0 0 0

P P A S

S P A S

If p c is scheduled before p d, then d will stay constant 0.

If p d is scheduled before p c, then d will have a 1 pulse.

With provisional assignments, both orders of scheduling processes result in the same behaviour on all signals. Without provisional assignments, different scheduling orders result in different behaviour.