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HIGH FREQUENCY FILTER DESIGN

for High-Frequency Circuit Design Elective

by Michael Tse

September 2003

CONTENTS
1. Introduction
1.1 Types of lters 1.2 Monolithic lters 1.3 Integrators 1.4 Simple rst-order gm-C lters

2.

Filter Design for High Frequencies


2.0 Introduction to lters (separate notes) 2.1 Special requirements for HF

3.

Gm-C Filter Synthesis


3.1 Cascaded biquads 3.2 Signal ow graphs

4.

Realization of Transconductors
4.1 BJT transconductors 4.2 MOSFET transconductors 4.3 Exercise
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1. INTRODUCTION
1920 1960 1970
Basic forms: LC-Ladders Due to the advent of op-amps, ACTIVE RC lters became popular. Miniaturization leads to IC lters which use monolithic technology for active components and thin-lms for frequency determining components (C,R). IC monolithic lters became popular.

1980

Advantages:
Less components, smaller volume Good matching of components Automatic tuning correct transfer functions for process/temp variations Smaller parasitic caps on chip Fabricated in large quantity
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1.1 Types of Filter Realizations


Digital lters Analog discrete-time lters Analog continuous-time lters

1.1.2 Analog discrete-time lters


Signals are discretized but NOT digitized. They are called sampled-data. Filtering is done directly to the sampled-data. Example: switched-capacitor lters (SC lters) But SC lters are mainly for low-frequency applications (audio range)

1.1.1 Digital lters:


Signals need to be discretized and digitized, i.e., sampled and converted to digital words, and the ltering is done in the digital domain.
Discretization (sampling)

Digitization (A/D) Filter or Processor

0011001110010

D/A

0011001110010

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1.1.3 Analog continuous-time lters


Continuous analog signals are directly processed without any A/D or D/A conversions, sampled-&-hold, anti-aliasing lters, etc. Because of the continuous-time nature, analog continuous-time lters are very suitable for high-frequency and high dynamic range applications. Disadvantages:
1. 2. 3. Sensitive to process and temperature variations Aging Need tunings of the frequency determining components

Since we are dealing with high-frequency design, we will focus on Analog Continuous-time Filters in these notes

Michael Tse: HF Filter Design

1.2 Monolithic Filters


Fully integrated analog continuous-time lters were possible when automatic tuning of components became available, starting 1970s. 1.2.1 Bipolar lters Properties
1. 2. 3. 4.

1.2.2 MOS lters High voltage gain Properties High output drive High frequency (up to ~100 MHz) 1. Low power 2. High packing density Low noise and offsets 3. High noise immunity 4. Ease of design 5. Ease of scaling 6. High frequency (up to ~100 MHz)

Michael Tse: HF Filter Design

1.3 Integrators (Building Blocks)


Integrators are needed in all active lters. [ In passive lters, integrators are provided by inductors and capacitors, in both I and V domains. ] However, for active lters, only C exists. Hence, we need to have integrators of output/input variables are in the same voltage or current domain.

1.3.1 Active RC (Op-amp RC) Integrators


Vj Cj
. . .

n x R m x C C int

Ri

Mi

mC V Vi j j Vo = - - i=1 jwCint Ri j =1 Cint


mosfet in triode region to simulate a resistance

Vi Ri
+

Vo

Michael Tse: HF Filter Design

Active RC Integrators (cont)


The RC integrator shown previously in not very suitable for monolithic realization because the time constant ti = RiCint cannot be tuned after realization! Note that C and R can only be fabricated with an accuracy of 20% and 5% respectively.

Design notes:
1. Nonlinearity of MOSFETS is mainly second-order. Thus, MOSFET-C integrators must be designed in BALANCED FORM in order to cancel even harmonics. 2. It is difcult to implement good MOS op-amps. Usually, BiMOS technology is used for MOSFETC integrator lters. 3. It is also possible to tune the frequency using the transconductance instead of the MOSFET resistance.

With MOSFET-C integrators, the tuning problem can be solved by varying the gate voltage of Mi --> Ri --> ti .

Michael Tse: HF Filter Design

1.3.2 Transconductance-C or gm-C Filters


BASIC CIRCUIT:

The general gm-C integrator:


Vj Cj m x C
. . .

transconductance

Vi

gm

i = Vi g m

Vi

gmi gm

n x gm Vo C int

Vo =

n g V mi i

i=1 jwCeff

m j =1

mCV j j

j=1 Ceff

We can control t i = Ceff/gmi by tuning the transconductance. Note: The transfer function suffers from loading effects, which depend on the summation cap Cj. The gain gm is a design parameter (whereas in activeRC, the op-amp gain doesnt matter).

where Ceff = Cint +

C j
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1.4 Simple First-order gm-C Filters


The basic transfer function is: H(s) =
CX

Vout k1 s + k0 = Vi n s + w0

Gm-C realisation:

g m

Vin

+g m

2 CA

Vout

The nodal equation is:


gm1Vi n + sCX (Vi n - Vout ) - sCAVout - gm 2Vout = 0 C g X m1 s C + C +C + C Vout A X A X = g Vi n m2 s+ C + C A X
Michael Tse: HF Filter Design

The parameters are adjusted by

CX =

k1CA for 0 k1 < 1 1- k1

gm1 = k 0 (CA + CX ) gm 2 = w 0 (CA + CX )


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2 FILTER DESIGN FOR HIGH FREQUENCIES 2.1 Special Requirements for HF


(a) No nodes with an undesired capacitance to ground.
In VHF, parasitic caps become signicant and quite similar values to the designed capacitances. Thus, we need to make sure that each node in the lter MUST have a desired capacitance to ground so that we know what it is and how it is put in the transfer functions.

Va Vb

+gm g m g m +g m +gm

g Vo = m (Va - Vb ) sC

m a parasitic NOT SUITABLE FOR HF

I = g (V - Vb )

Va Vb

+gm

g m

g Vo = m (Va - Vb ) sC

+gm

I = gm (Va - Vb )
SUITABLE FOR HF

g m

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2.1
(b)

Special Requirements for HF (cont)


Balanced operation for reducing Vc + 1 Vin 2 even harmonics and crosstalks. Signal inversion can be obtained V - 1 V c easily in gm-C. 2 in Balanced transconductance:
+ gm +

+ gm + C

g V -V Vc + m a b sC 2

Vc is cancelled!
g V - V Vc - m a b sC 2

Vc +

1 2 Vin

Vc 1 Vin 2

+ gm +

Iout,diff = Iop Ion = gmVin

gmVin I on = 2 g Vin Iop = + m 2

+ gm +

+ gm +

g I = + m (Va - Vb ) 2

g I = - m (Va - Vb ) 2
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2.1
(c)

Special Requirements for HF (cont)


Sensitivity must be LOW for component variations to reduce errors. In VHF lters, the capacitors are small and will have 20100% part of parasitic cap. Hence, inaccuracy is expected in capacitance ratios. Fortunately, ratios of gm are usually integer numbers, matching between gms should be good. Thus, sensitivities of lter transfer functions to capacitor values MUST BE KEPT LOW.

(d)

Dynamic range is determined by


dynamic range of gm dynamic range of lter structure e.g., if internal node signal levels have large variations (swings), then the output swing becomes restricted. This usually requires computer simulations for optimisation.
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3. Gm-C FILTER SYNTHESIS


1. 2. 3. 4. Cascaded biquad Signal ow graph State space method Gyrator method

BIQUAD: circuit realizing a general lter transfer function of second order

a2 s2 + a1s + a0 H(s) = K w s2 + s o + wo Qp
a2 = a1 = 0 --> LOWPASS a2 = a0 = 0 --> BANDPASS a1 = a0 = 0 --> HIGHPASS a1 = 0 --> BANDSTOP
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3.1 Cascaded Biquads


General biquad section using gm-C realization (VHF applications)
1
+gm

2
+gm

3
g m

C1

C2

Va

+g m

2 gm 4 gm3 gm5 V + V s Vc + s C3 C3 b C1C3 a Vo = C2 + C3 s2 + s gm3 + gm1gm2 C2 + C3 C1 (C2 + C3 )

5 4

where w o =
Qp =

Vb Vc

+gm

gm1g m2 C1 (C1 + C2 ) C2 + C3 C1 gm1 gm 2 gm 3

C3

So, K, a0, a1, wo and Qp can be chosen by choosing gms and Cs.
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3.1 Cascaded Biquads (cont)


Features:
1. 2. 3. 4. This biquad is suitable for very high frequencies because each node has a known capacitance to ground. C2 is not essential, but is unavoidable. Hence, it must be taken into account. Cascading multiple biquads will cause loading effects, which must be taken into consideration because there is no ideal buffer at high frequencies. Output level can be scaled for optimal dynamic range by varying K.

High order lters: biquad1 biquad2

Disadvantage of cascaded biquads: Passband sensitivity to component variations tends to be too large for some applications. (A better approach is to start with LC ladder.)
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3.2 Signal Flow Graph Synthesis


The starting point is passive lossless LC ladder. The following is a 3rd order elliptic low-pass lter.
IL3 L 3 R1 I 1 I 3
+ +

The state equations:


State VC2: sC2VC 2 + I L 3 + IC 3 = I1

I5 IC3
+ +

Vin

VC2

C2

C 3 C4

VC4

R5 Vout

Vi n - VC 2 R1 V V (sC2 + sC3 )VC 2 - sC3VC 4 + C 2 = i n - IL 3 R1 R1 sC2VC 2 + I L 3 + sC3 (VC 2 - VC 4 ) = VC 2 + VC 2 CV Vi n IL3 = 3 C4 + s(C2 + C3 )R1 C2 + C3 sR1 (C1 + C3 ) s(C2 + C3 )
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3.2 Signal Flow Graph Synthesis (cont)


Signal ow graph for state VC2:
IL3 L 3 R1 I 1 I 3
+ +

I5 IC3
+ +

Vin

1 sR1 (C2 + C3 )

VC2

C3 C2 + C3

VC4 OR Vin

Vin

VC2

C2

C 3 C4

VC4

R5 Vout

1 sR1 (C2 + C3 )

-1 s(C2 + C3 )

C3 VC2 C2 + C3

VC4

IL3 1

1 sR1 (C2 + C3 )

1
Combining similar factors together
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R1IL3
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3.2 Signal Flow Graph Synthesis (cont)


State VC4:
IL3 L 3 R1 I 1 I 3
+ +

Vout = I L 3 + sC3 (VC 2 - VC 4 ) R5 -V s(C4 + C3 )VC 4 = out + IL 3 + sC3VC 2 R5 -Vout IL3 CV VC 4 = + + 3 C2 sR5 (C3 + C4 ) s(C3 + C4 ) C3 + C4 sC4 VC 4 +
C3 C3 + C4

I5 IC3
+ +

Vin

VC2

C2

C 3 C4

VC4

R5 Vout

VC2

VC4

1 1
1 sR5 (C3 + C4 )

Vout

VC2

C3 C3 + C4

VC4

Vout

1 s(C3 + C4 )

1 sR5 (C3 + C4 )

IL3

1
R5IL3

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3.2 Signal Flow Graph Synthesis (cont)


State IL3 :

sL3 IL 3 = VC 2 - VC 4 VC 2 - VC 4 IL 3 = sL3
VC2

IL3 L 3 R1 I 1 I 3
+ +

I5 IC3
+ +

Vin

VC2

C2

C 3 C4

VC4

R5 Vout

VC4

1 sL3
IL3

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3.2 Signal Flow Graph Synthesis (cont)


Combining the three sub-graph, we get the nal signal ow graph:
+

IL3 L 3 R1 I 1 I 3
+

I5 IC3
+ +

Vin
C3 C2 + C3

VC2

C2

C 3 C4

VC4

R5 Vout

Vin
1 1

VC2

C3 C4 + C3

1
1 sR1 (C2 + C3 )

1
R1 sL3

VC4

1 1

Vout

1 sR1 (C3 + C4 )

R1IL3
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R1 = R5
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3.2 Signal Flow Graph Synthesis (cont)


We can now synthesize the circuit with gm-C. The rules are: 1. 2. 3. 4. The 1 branch is gm. All transconductances are 1/R1. 1/s branch is cap to ground. Gains C3/(C2+C3) and C3/(C4+C3) can be realized by capacitor ladder.
g m

VC2

C3

VC4

C2

C4

C3
+gm g m +gm

gm

Vin

+gm

VC2

VC4

Vout

C2

gm

C L3

C4

Exercise: Convert it to a balanced gm-C circuit.


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4. REALISATION OF TRANSCONDUCTORS
Transconductors (gm blocks) can be realized in BJT form or MOSFET form.
Bipolar: 1. Fixed transconductor cascaded with gain cell. A xed transconductor is usually a differential pair linearized by resistor degeneration. Differential input stage with multiple inputs, with transistor scaling for better linearity. MOS: 1. Fixed-bias triode MOS transistor as resistor. Multiple outputs are possible using mirrors. Varying-bias triode MOS transistor as resistor. Differential input with constant drain-source current.

2.

2.

3.

To avoid confusion, in the next pages, we use Gm to stand for the transconductance of the whole block, and gm for the transistors.
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4.1 BJT Transconductors Fixed transconductance using resistor

I1
Q1 i o1 i o1 Q 2

I1

I1
Q1 i o1 i o1 Q 2

I1
No bias current ows in RE. The CM voltage is nearly zero, hence larger CM range. (The base of each side must not be less than Vi/2, or the transistor will be cut off.)

+ Vi

RE /2 RE /2

+ Vi I1

RE

2I 1

I1

io1 1 = Gm = 2 Vi + RE gm

Note: Distortion due to non-constant Gm. So, linearity can be improved if RE is much greater than 1/gm of the transistor. Moreover, if Vbe is assumed xed, Vi appears purely across resistor and hence Gm = 1/RE (independent of gm).
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4.1 BJT Transconductors (cont) Finding the Gm for this xed transconductance
Half-circuit equivalent model:
I1
Q1 i o1 i o1 Q 2

I1

io1 +

vbe

r
RE/2

+ Vi

RE /2 RE /2

Vi 2

gmvbe

2I 1

Vi rp 1 io1 = gm = Vi RE 2 2 r + b + RE p 2 gm

Michael Tse: HF Filter Design

io1 1 = Gm = 2 Vi + RE gm

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4.1 BJT Transconductors (cont) Gain-cell transconductor (tunable Gm)


1 I2 Gm = RE I1
i o1

Q3

Q4

level shifter

I2

I2

+ Vi I1

Q1

Q2

+ VLS

+ VLS
Q5 Q6

i o1

RE 2I 2

The transconductance can be tuned by setting the current ratio I2/I1.

I1

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4.2 MOSFET Transconductors Fixed-bias triode MOSFETusing a MOSFET operating in triode region to simulate a resistor
I1
Q5 Q1 Q2

I1
Q6

MOSFET Q9 in triode region acting as resistor

Transconductance is
Gm =
I 1 + i o1
Q8

V+
i

Vi

I 1 i o1

Vc
Q9

W io1 = mCox ( vgs9 - VTH ) L 9 Vi + - Vi

Q7

Q3

Q4

I2

I2

This Gm can be easily modied to give multiple outputs! (using mirrors)

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4.2 MOSFET Transconductors (cont) Varying bias triode MOSFETimproved linearity


I1 i o1 V1
Q1 Q2 Q3

I1 i o1

Q3 and Q4 are in triode region and undergo varying bias conditions (because their gates are not connected to xed bias.) Why is linearity improved? Try the exercise on next page.

Transconductance is

V2 I1

Q4

Gm =
I1

io1 4 k1k3 I1 = V1 - V2 (k1 + 4 k3 ) k1

m Cox W where kn = 2 L n
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EXERCISE Consider the circuit of the previous page. Suppose I1 = 100A, Cox = 96A/V2, (W/L)1 = (W/L)2 = 20, (W/L)3 = 3, and V2 = 0. (a) Assuming a perfectly linear transconductor, nd io1 when V1=2.5mV and 250mV, using the formula given in the previous page. (b) Assume the gates of Q3 and Q4 are connected to ground and use classical models for both the triode and active regions. Find the true value of io1 when V1=2.5mV and 250mV. Compare your results with those found in (a). (c) Repeat (b), assuming the gates of Q3 and Q4 are connected to the input signals as shown in the circuit. (d) Comment on the linearity improvement, if any, when varying bias triode transistor is used.

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