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Transistor Applications
EE 21 Fundamentals of Electronics
Outline
Current mirror circuits
Constant current circuits
Transistor Switching and Logic gates
Voltage-controlled resistor
Timer Network
Current Mirror Circuits
Provides constant
current
Used primarily in
integrated circuits
Requires identical
transistors,
fabricated near each
other on the same
chip.
Current Mirror Circuits
The two transistor
currents are
approximately



And for each
transistor,
| |
E E
B
I I
I ~
+
=
1
E C
I I ~
Current Mirror Circuits
The current through
resistor Rx is given
by



Simplifying,
| |
|
E E
X
I I
I
2
+ =
| |
|
E E
X
I I
I
2
+ =
Current Mirror Circuits
Finally,


In summary, the
constant current at
Q2 mirrors that of
Q1, given by


E E X
I I I ~
+
=
|
| 2
X
BE CC
X
R
V V
I I

= =
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Current Mirror Circuits
Another type of
current mirror
circuit involves a
JFET, with the
mirrored current
being its I
DSS
.
Constant Current Source (CCS)
Assumption: base
input impedance >
R
1
or R
2
.
By VDR,

Also,
The current is now
given by

2 1
1
R R
R V
V
EE
B
+

=
V V V
B E
7 0. =
C
E
EE E
E
I
R
V V
I ~

=
) (
CCS with Zener Diode
Zener diode allows
for an improved
current source.
VEE serves only to
turn the zener diode
on.
KVL gives us

C
E
BE Z
E
I
R
V V
I ~

=
Transistor Switching
Basis for switching in the concept of saturation
and cutoff.

Involves the switching (or moving) of the Q-
point from cut-off to saturation along the load
line.

Ideal assumptions: I
C
= 0 (cutoff) when I
B
=
0, V
CEsat
= 0. (saturation)

Saturation and Cutoff
At saturation, the current I
C
is high and voltage
V
CE
very low.

Thus, ideal resistance at saturation 0

At cutoff, V
CE
= V
CC
= high and I
C
is very low.
Thus ideal resistance at cutoff .
Logic Gates using BJTs
Inverter / NOT Gate

AND Gate

OR Gate


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Inverter Gate
If a low input is
impressed, the
output is high, while
if a high input (5 V)
is impressed, the
output is low.
AND Gate
The output C = AB
requires that both
inputs A and B be
turned on (high) in
order for the input
to be high.
OR Gate
The output C = A + B
requires that only
either one of the
two inputs A or B be
high in order for the
output to be high.
Voltage Controlled Resistor
Follows the equation given
by the ohmic region
of the FET.

In the ohmic region,
the FET curve can be
likened to that of a resistor (linear).

|
|
.
|

\
|

=
P
GS
o
d
V
V
r
r
1
JFET Timer
INITIAL:
When power is first
applied, capacitor
shorts out.

With Vc = 0, V
GS
= 0
initially, thus I
D
=
I
DSS
and the bulb
lights up.
JFET Timer
While this is
happening,
capacitor charges
up to -9 V.

When capacitor
reaches pinch-off
level (-6V), I
D
= 0
and bulb turns off.
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JFET Timer
TIMING FUNCTION
When switch is
closed, capacitor is
shorted and V
GS
= 0,
thus I
D
= I
DSS
and the
lamp lights up.
When switch is
released, capacitor
charges to -9V.
JFET Timer
The bulb dims until
turned-off when Vc
= Vp.

The length of the
light-on time is
determined by the
RC network, with
=(R
1
+R
2
)C, and the
pinch-off voltage Vp.
JFET Timer
R
1
helps limit initial
surge current
R
2
is the variable
resistance to modify

R
3
limits the
discharge current
when the switch is
closed.
JFET Timer
Note that the JFET
has a very high
input impedance
and thus, will not
affect the of the RC
network (due to it
being connected in
parallel).