2/7/12 CMOS ineie eion

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CMOS interview questions & answer
CMOS interview questions.
1) What is latch up?
Latch-up pertains to a failure mechanism wherein a parasitic thristor (such as a parasitic silicon controlled rectifier, or
SCR) is inadvertentl created within a circuit, causing a high amount of current to continuousl flow through it once it is
accidentall triggered or turned on. Depending on the circuits involved, the amount of current flow produced b this
mechanism can be large enough to result in permanent destruction of the device due to electrical overstress (EOS) .
2)Why is NAND gate preferred over NOR gate for fabrication?
NAND is a better gate for design than NOR because at the transistor level the mobilit of electrons is normall three
times that of holes compared to NOR and thus the NAND is a faster gate.
Additionall, the gate-leakage in NAND structures is much lower. If ou consider t_phl and t_plh delas ou will find
that it is more smmetric in case of NAND ( the dela profile), but for NOR, one dela is much higher than the
other(obviousl t_plh is higher since the higher resistance p mos's are in series connection which again increases the
resistance).
3)What is Noise Margin? Explain the procedure to determine Noise Margin
The minimum amount of noise that can be allowed on the input stage for which the output will not be effected.
4)Explain sizing of the inverter?
In order to drive the desired load capacitance we have to increase the sie (width) of the inverters to get an optimied
performance.
5) How do you size NMOS and PMOS transistors to increase the threshold voltage?
6) What is Noise Margin? Explain the procedure to determine Noise Margin?
The minimum amount of noise that can be allowed on the input stage for which the output will not be effected.
7) What happens to delay if you increase load capacitance?
dela increases.
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2/7/12 CMOS ineie eion
2/4 aic.co.in/Inde_file/cmofa.hm
8)What happens to delay if we include a resistance at the output of a CMOS circuit?
Iceae. (RC dea)
9)What are the limitations in increasing the power supply to reduce delay?
The dea ca be edced b iceaig he e b if e d he heaig effec ce becae f eceie
e, ceae hi e hae iceae he die ie hich i acica.
10)How does Resistance of the metal lines vary with increasing thickness and increasing length?
R = ( *) / A.
11)For CMOS logic, give the various techniques you know to minimize power consumption?
Pe diiai=CV2f ,f hi iiie he ad caaciace, dc age ad he eaig feec.
12) What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus?
I he eia ceced NMOS gic he i caaciace f each gae hae he chage ih he ad caaciace b
hich he gica ee daica iached ha ha f he deied ce. T eiiae hi ad caaciace be
e high caed he i caaciace f he gae (aiae 10 ie).
13)Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit
to one large inverter?
Becae i ca die he ad aigh aa, e gada iceae he ie ge a iied
eface.
14)What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch
Up?
Lach- i a cdii i hich he aaiic ce gie ie he Eabihe f eiace cdcig
ah beee VDD ad VSS ih Dia e.
15) Give the expression for CMOS switching power dissipation?
CV2
16) What is Body Effect?
I geea ie MOS deice ae ade a c bae. A a e, he bae age f a deice i
a ea. Hee hie cecig he deice eia hi a e i a iceae i ce--bae
age a e ceed eica ag he eie chai (Vb1=0, Vb2 0).Which e Vh2>Vh1.
17) Why is the substrate in NMOS connected to Ground and in PMOS to VDD?
e eee bia he chae ad he bae b e aiai he dai,ce jci eee biaed
ih eec he bae ha e d e ce i he bae.
18) What is the fundamental difference between a MOSFET and B1T ?
I MOSFET, ce f i eihe de eec(-chae MOS) de he(-chae MOS) - I BJT, e
ee ce de bh he caie.. eec ad he. BJT i a ce ced deice ad MOSFET i a age
ced deice.
19)Which transistor has higher gain. B1T or MOS and why?
2/7/12 CMOS ineie eion
3/4 aic.co.in/Inde_file/cmofa.hm
BJT ha highe gai becae i ha highe acdcace.Thi i becae he ce i BJT i eeia
deede i hee a i MOSFET i i ae a.
20)Wh do we graduall increase the sie of inverters in buffer design when tring to drive a high capacitive
load? Wh gie he f a cici e age iee?
We ca e a big iee die a age caaciace becae, h i die he big iee? The iga ha
ha die he ca i ee a age gae caaciace f he BIG iee.S hi e i aie fa
ie .A i iee ca die aiae a iee ha 4 ie bigge i ie. S a e eed die a ca f
64 i iee he e ee he iig ie a 1,4,16,64 ha each iee ee a ae ai f
i ca. Thi i he ie ea behid gig f geie iig.
21)In CMOS technolog, in digital design, wh do we design the sie of pmos to be higher than the
nmos.What determines the sie of pmos wrt nmos. Though this is a simple question tr to list all the reasons
possible?
I PMOS he caie ae he he bii i e[ a haf ] ha he eec, he caie i NMOS. Tha
ea PMOS i e ha a NMOS. I CMOS echg, he i ig d he gd a
PMOS he i ig he Vdd. If he ie f PMOS ad NMOS ae he ae, he PMOS ae g
ie chage he de. If e hae a age PMOS ha hee i be e caie chage he de
ic ad ece he ae f PMOS . Baica e d a hi ge ea ie ad fa ie f he
de.
22)Wh PMOS and NMOS are sied equall in a Transmission Gates?
I Taii Gae, PMOS ad NMOS aid each he ahe ceig ih each he. Tha' he ea h e
eed ie he ie i CMOS. I CMOS deig e hae NMOS ad PMOS ceig hich i he ea e
ie he ia hei bii.
23)All of us know how an inverter works. What happens when the PMOS and NMOS are interchanged with
one another in an inverter?
I hae ee iia Q i e f he dici. If he ce & dai a ceced e...i ac a a bffe. B
e i i gic 1 O/P i be degaded 1 Siia degaded 0;
24)A good question on Laouts. Give 5 important Design techniques ou would follow when doing a Laout
for Digital Circuits?
a)I digia deig, decide he heigh f adad ce a a.I deed h big ai i
be.Hae eaabe idh f VDD ad GND ea ah.Maiaiig if Heigh f a he ce i e ia
ice hi i he e ace e eai ad a icae a d aa ceci f a he bc i
ae f aea.
b)Ue e ea i e dieci , Thi de a f ea 1. Sa ae ig ea 2 d hia
ceci, he e ea 3 f eica ceci, ea4 f hia, ea 5 eica ec...
c)Pace a a bae cac a ibe i he e ace f he a.
d)D e e g diace a i ha hge eiace e hae he chice.
e)Ue figeed ai a ad he fee ecea.
f)T aiaiig e i deig. T ge he deig i BIT Siced ae.
25)What is metastabilit? When/wh it will occur?Different was to avoid this?
Meaabe ae: A - ae i beee he gica ae.Thi i hae if he O/P ca i
aed chage/dichage f he eied gica ee.
Oe f he cae i: If hee i a e ie iai, eaabii i cc,T aid hi, a eie f FF i ed
(a 2 3) hich i ee he ieediae ae.
26)Let A and B be two inputs of the NAND gate. Sa signal A arrives at the NAND gate later than signal B.
2/7/12 CMOS ineie eion
4/4 aic.co.in/Inde_file/cmofa.hm
To optimie dela of the two series NMOS inputs A and B which one would ou place near to the output?
The lae coming ignal ae o be placed cloe o he op node ie A hold go o he nmo ha i cloe o he
op.