Tea 5767

TEA5767HN
Low-power FM stereo radio for handheld applications

Rev. 05 26 January 2007 Product data sheet
1. General description
The TEA5767HN is a single-chip electronically tuned FM stereo radio for low-voltage applications with fully integrated Intermediate Frequency (IF) selectivity and demodulation. The radio is completely adjustment-free and only requires a minimum of small and low cost external components. The radio can be tuned to the European, US, and Japanese FM bands.
2. Features
I High sensitivity due to integrated low-noise RF input amplier I FM mixer for conversion to IF of the US/Europe (87.5 MHz to 108 MHz) and Japanese (76 MHz to 91 MHz) FM band I Preset tuning to receive Japanese TV audio up to 108 MHz I RF Automatic Gain Control (AGC) circuit I LC tuner oscillator operating with low cost xed chip inductors I FM IF selectivity performed internally I No external discriminator needed due to fully integrated FM demodulator I Crystal reference frequency oscillator; the oscillator operates with a 32.768 kHz clock crystal or with a 13 MHz crystal and with an externally applied 6.5 MHz reference frequency I Phase-locked loop (PLL) synthesizer tuning system I I2C-bus and 3-wire bus, selectable via pin BUSMODE I 7-bit IF counter output via the bus I 4-bit level information output via the bus I Soft mute I Signal dependent mono to stereo blend [Stereo Noise Cancelling (SNC)] I Signal dependent High Cut Control (HCC) I Soft mute, SNC and HCC can be switched off via the bus I Adjustment-free stereo decoder I Autonomous search tuning function I Standby mode I Two software programmable ports I Bus enable line to switch the bus input and output lines into 3-state mode
NXP Semiconductors
TEA5767HN
3. Quick reference data

Table 1. Quick reference data VCCA = VCCD = VCC(VCO) = 2.7 V; Tamb = 25 C; AC values are given in RMS; for VRF the emf value is given; unless otherwise specied. Symbol VCCA VCC(VCO) Parameter analog supply voltage Voltage-Controlled Oscillator (VCO) supply voltage digital supply voltage analog supply current VCO supply current digital supply current operating; VCCA = 3 V Standby mode; VCCA = 3 V ICC(VCO) ICCD operating; VCC(VCO) = 3 V Standby mode; VCC(VCO) = 3 V operating; VCCD = 3 V Standby mode; VCCD = 3 V bus enable line HIGH bus enable line LOW fFM(ant) Tamb FM input frequency ambient temperature VCCA = VCC(VCO) = VCCD = 2.5 V to 5 V fRF = 76 MHz to 108 MHz; f = 22.5 kHz; fmod = 1 kHz; (S+N)/N = 26 dB; de-emphasis = 75 s; L = R; BAF = 300 Hz to 15 kHz f = 200 kHz; ftune = 76 MHz to 108 MHz f = +200 kHz; ftune = 76 MHz to 108 MHz VRF = 1 mV; L = R; f = 22.5 kHz; fmod = 1 kHz; de-emphasis = 75 s VRF = 1 mV; L = R; f = 22.5 kHz; fmod = 1 kHz; de-emphasis = 75 s
[2]
Conditions
[1] [1]
Min 2.5 2.5
Typ 3.0 3.0
Max Unit 5.0 5.0 V V
VCCD ICCA
[1]
2.5 6.0 560 2.1 30 11 76 10
3.0 8.4 3 750 1 3.0 56 19 -
5.0 6 940 2 3.9 80 26 108 +75
V A A A mA A A MHz C
10.5 mA
FM overall system parameters; see Figure 13 VRF RF sensitivity input voltage 2 3.5 V
S200 S+200 VAFL
low side 200 kHz selectivity high side 200 kHz selectivity left audio frequency output voltage right audio frequency output voltage
32 39 60
36 43 75
90
dB dB mV
[2]
VAFR
60
75
90
mV
TEA5767HN_5
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 26 January 2007
2 of 40
NXP Semiconductors
TEA5767HN
Table 1. Quick reference data continued VCCA = VCCD = VCC(VCO) = 2.7 V; Tamb = 25 C; AC values are given in RMS; for VRF the emf value is given; unless otherwise specied. Symbol (S+N)/N Parameter maximum signal plus noise-to-noise ratio Conditions VRF = 1 mV; L = R; f = 22.5 kHz; fmod = 1 kHz; de-emphasis = 75 s; BAF = 300 Hz to 15 kHz VRF = 1 mV; R = L = 0 or R = 0 and L = 1 including 9 % pilot; f = 75 kHz; fmod = 1 kHz; data byte 3 bit 3 = 0; data byte 4 bit 1 = 1 VRF = 1 mV; L = R; f = 75 kHz; fmod = 1 kHz; de-emphasis = 75 s Min 54 Typ 60 Max Unit dB
cs(stereo)
stereo channel separation
24
30
dB
THD
total harmonic distortion
0.4
[1] [2]
VCCA, VCC(VCO) and VCCD must not differ by more than 200 mV. Low side and high side selectivity can be switched by changing the mixer from high side to low side LO injection.
4. Ordering information
Table 2. Ordering information Package Name TEA5767HN HVQFN40 Description plastic thermal enhanced very thin quad at package; no leads; 40 terminals; body 6 6 0.85 mm Version SOT618-1 Type number
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Product data sheet Rev. 05 26 January 2007
NXP B.V. 2007. All rights reserved. TEA5767HN_5
5. Block diagram
NXP Semiconductors
47 nF LIMDEC2 29 R1 Igain 32 GAIN STABILIZATION AGND 33 22 nF VCCA 4.7 22 F VCCA 34 RESONANCE AMPLIFIER LIMITER
47 nF LIMDEC1 28
47 nF TIFC 27
33 nF Vref 26 MPXO 25
33 nF TMUTE 24 VAFR 23 VAFL 22
POWER SUPPLY
DEMODULATOR
SOFT MUTE SDS
FM antenna
I/Q-MIXER 1st FM
2 N1 IF CENTRE FREQUENCY ADJUST
LEVEL ADC
IF COUNTER MPX DECODER
19 PILFIL
1 nF
33 k 22 nF 22 nF
100 pF RFI1 35 L1 27 pF RFGND 36 47 pF RFI2 37 AGC
Iref
18 PHASEFIL 17 XTAL2
Ccomp(1) 32.768 kHz or 13 MHz
TEA5767HN
TAGC 38 4.7 nF LOOPSW 39 programmable divider output TUNING SYSTEM reference frequency divider output MUX SOFTWARE PROGRAMMABLE PORT pilot mono VCO I2C-BUS AND 3-WIRE BUS 4 VCOTANK2 5 VCC(VCO) VCCD 6 DGND 12 22 nF L3 100 k L2 7 VCCD 8 DATA 9 CLOCK
CRYSTAL OSCILLATOR
Cpull(1) 16 XTAL1 15 SWPORT2 10 k 14 SWPORT1 10 k 13 BUSENABLE 12 BUSMODE
VCCA
1, 10, 20, 21, 30, 31, 40 n.c.
11 WRITE/READ
CPOUT VCOTANK1 10 nF 39 nF 10 k
mhc283
D1
D2
TEA5767HN
47
22 nF VCC(VCO)
The component list is given in Section 16. (1) Ccomp and Cpull data depends on crystal specication.
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Fig 1. Block diagram
NXP Semiconductors
TEA5767HN
6. Pinning information
6.1 Pinning
39 LOOPSW
36 RFGND
33 AGND
38 TAGC
34 VCCA
37 RFI2
35 RFI1
32 Igain PILFIL 19
40 n.c.
terminal 1 index area n.c. CPOUT VCOTANK1 VCOTANK2 VCC(VCO) DGND VCCD DATA CLOCK 1 2 3 4 5 6 7 8 9
31 n.c. 30 n..c. 29 LIMDEC2 28 LIMDEC1 27 TIFC 26 Vref 25 MPXO 24 TMUTE 23 VAFR 22 VAFL 21 n.c. n.c. 20
001aab363
TEA5767HN
n.c. 10 WRITE/READ 11 BUSMODE 12 BUSENABLE 13 SWPORT1 14 SWPORT2 15 XTAL1 16 XTAL2 17 PHASEFIL 18
Transparent top view
Fig 2. Pin conguration
6.2 Pin description

Table 3. Symbol n.c. CPOUT VCOTANK1 VCOTANK2 VCC(VCO) DGND VCCD DATA CLOCK n.c. WRITE/READ BUSMODE BUSENABLE SWPORT1 SWPORT2 XTAL1
TEA5767HN_5
Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Description not connected charge pump output of synthesizer PLL VCO tuned circuit output 1 VCO tuned circuit output 2 VCO supply voltage digital ground digital supply voltage bus data line input/output bus clock line input not connected write/read control input for the 3-wire bus bus mode select input bus enable input software programmable port 1 software programmable port 2 crystal oscillator input 1
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Pin description continued Pin 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Description crystal oscillator input 2 phase detector loop lter pilot detector low-pass lter not connected not connected left audio frequency output voltage right audio frequency output voltage time constant for soft mute FM demodulator MPX signal output reference voltage time constant for IF center adjust decoupling IF limiter 1 decoupling IF limiter 2 not connected not connected gain control current for IF lter analog ground analog supply voltage RF input 1 RF ground RF input 2 time constant RF AGC switch output of synthesizer PLL loop lter not connected
Table 3. Symbol XTAL2 PHASEFIL PILFIL n.c. n.c. VAFL VAFR TMUTE MPXO Vref TIFC LIMDEC1 LIMDEC2 n.c. n.c. Igain AGND VCCA RFI1 RFGND RFI2 TAGC LOOPSW n.c.
7. Functional description
7.1 Low-noise RF amplier
The Low Noise Amplier (LNA) input impedance together with the LC RF input circuit denes an FM band lter. The gain of the LNA is controlled by the RF AGC circuit.
7.2 FM mixer
The FM quadrature mixer converts the FM RF (76 MHz to 108 MHz) to an IF of 225 kHz.
7.3 VCO
The varactor tuned LC VCO provides the Local Oscillator (LO) signal for the FM quadrature mixer. The VCO frequency range is 150 MHz to 217 MHz.
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7.4 Crystal oscillator

The crystal oscillator can operate with a 32.768 kHz clock crystal or a 13 MHz crystal. The temperature drift of standard 32.768 kHz clock crystals limits the operational temperature range from 10 C to +60 C. The PLL synthesizer can be clocked externally with a 32.768 kHz, a 6.5 MHz or a 13 MHz signal via pin XTAL2. The crystal oscillator generates the reference frequency for:
The reference frequency divider for the synthesizer PLL The timing for the IF counter The free-running frequency adjustment of the stereo decoder VCO The center frequency adjustment of the IF lters
7.5 PLL tuning system

The PLL synthesizer tuning system is suitable to operate with a 32.768 kHz or a 13 MHz reference frequency generated by the crystal oscillator or applied to the IC from an external source. The synthesizer can also be clocked via pin XTAL2 at 6.5 MHz. The PLL tuning system can perform an autonomous search tuning function.
7.6 RF AGC
The RF AGC prevents overloading and limits the amount of intermodulation products created by strong adjacent channels.
7.7 IF lter
Fully integrated IF lter.
7.8 FM demodulator
The FM quadrature demodulator has an integrated resonator to perform the phase shift of the IF signal.
7.9 Level voltage generator and analog-to-digital converter

The FM IF analog level voltage is converted to 4 bits digital data and output via the bus.
7.10 IF counter
The IF counter outputs a 7-bit count result via the bus.
7.11 Soft mute

The low-pass ltered level voltage drives the soft mute attenuator at low RF input levels. The soft mute function can be switched off via the bus.
7.12 MPX decoder

The PLL stereo decoder is adjustment-free. The stereo decoder can be switched to mono via the bus.
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Product data sheet
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TEA5767HN
7.13 Signal dependent mono to stereo blend

With a decreasing RF input level the MPX decoder blends from stereo to mono to limit the output noise. The continuous mono to stereo blend can also be programmed via the bus to an RF level depending switched mono to stereo transition. Stereo Noise Cancelling (SNC) can be switched off via the bus.
7.14 Signal dependent AF response

The audio bandwidth will be reduced with a decreasing RF input level. This function can be switched off via the bus.
7.15 Software programmable ports

Two software programmable ports (open-collector) can be addressed via the bus. The port 1 (pin SWPORT1) function can be changed with write data byte 4 bit 0 (see Table 13). Pin SWPORT1 is then output for the ready ag of read byte 1.
7.16 I2C-bus and 3-wire bus

The 3-wire bus and the I2C-bus operate with a maximum clock frequency of 400 kHz. Before any READ or WRITE operation the pin BUSENABLE has to be HIGH for at least 10 s. The I2C-bus mode is selected when pin BUSMODE is LOW, when pin BUSMODE is HIGH the 3-wire bus mode is selected.
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Power on: Mute, stand-by activated All other status is random Complete initialization by microprocessor is required
Write enable activated? yes Reset bit counter: Bits are clocked into the receive register
no
Completed bytes are written to the destinastion register
Use value of tuning memory: Write result to the programmable divider (also available at the bus) Wait 10 ms. Have the signal level available at the bus
Search Mode? yes no Signal level OK?
no
yes Reset IF counter and enable counting Wait for result Have the result available for the bus
Search Mode? no no
yes
Search upwards?
no
IF frequency OK? yes
yes Add 100 kHz to the tuning memory Substract 100 kHz to the tuning memory
Set 'found' flag
Upper tuning limit exceeded? no
yes
Lower tuning limit exceeded? no
Set 'band limit' flag
001aae346
Fig 3. Flowchart auto search or preset
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8. I2C-bus, 3-wire bus and bus-controlled functions

8.1 I2C-bus specication
Information about the I2C-bus can be found in the brochure The I2C-bus and how to use it (order number 9398 393 40011). The standard I2C-bus specication is expanded by the following denitions: IC address: 110 0000b Structure of the I2C-bus logic: slave transceiver Subaddresses are not used The maximum LOW-level input and the minimum HIGH-level input are specied to 0.2VCCD and 0.45VCCD respectively. The pin BUSMODE must be connected to ground to operate the IC with the I2C-bus. Remark: The I2C-bus operates at a maximum clock frequency of 400 kHz. It is not allowed to connect the IC to an I2C-bus operating at a higher clock rate.
8.1.1 Data transfer

Data sequence: address, byte 1, byte 2, byte 3, byte 4 and byte 5 (the data transfer has to be in this order). The Least Signicant Bit (LSB) = 0 of the address indicates a WRITE operation to the TEA5767HN. Bit 7 of each byte is considered as the Most Signicant Bit (MSB) and has to be transferred as the rst bit of the byte. The data becomes valid bitwise at the appropriate falling edge of the clock. A STOP condition after any byte can shorten transmission times. When writing to the transceiver by using the STOP condition before completion of the whole transfer:
The remaining bytes will contain the old information If the transfer of a byte is not completed, the new bits will be used, but a new tuning
cycle will not be started The IC can be switched into a low current Standby mode with the standby bit; the bus is then still active. The standby current can be reduced by deactivating the bus interface (pin BUSENABLE LOW). If the bus interface is deactivated (pin BUSENABLE LOW) without the Standby mode being programmed, the IC maintains normal operation, but is isolated from the bus lines. The software programmable output (SWPORT1) can be programmed to operate as a tuning indicator output. As long as the IC has not completed a tuning action, pin SWPORT1 remains LOW. The pin becomes HIGH, when a preset or search tuning is completed or when a band limit is reached. The reference frequency divider of the synthesizer PLL is changed when the MSB in byte 5 is set to logic 1. The tuning system can then be clocked via pin XTAL2 at 6.5 MHz.
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8.1.2 Power-on reset

At Power-on reset the mute is set, all other bits are set to LOW. To initialize the IC all bytes have to be transferred.
8.2 I2C-bus protocol

S(1) A(2) A(2) P(3)
001aae347
ADDRESS (WRITE)
DATA BYTE(S)
(1) S = START condition. (2) A = acknowledge. (3) P = STOP condition.
Fig 4. Write mode
S(1)
ADDRESS (READ)
A(2)
DATA BYTE 1
001aae348
(1) S = START condition. (2) A = acknowledge.
Fig 5. Read mode Table 4. IC address 1

[1]
IC address byte Mode 1 0 0 0 0 0 R/W[1]
Read or write mode: a) 0 = write operation to the TEA5767HN. b) 1 = read operation from the TEA5767HN.
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Product data sheet
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SDA t SU;DAT t HD;STA tf
tf
t LOW
tr
t BUF
SCL
t HD;STA t SU;BUSEN BUSENABLE
t HD;DAT
t SU;STA
t HIGH
t SU;STO t HO;BUSEN
001aae349
tf = fall time of both SDA and SCL signals: 20 + 0.1Cb < tf < 300 ns, where Cb = capacitive load on bus line in pF. tr = rise time of both SDA and SCL signals: 20 + 0.1Cb < tf < 300 ns, where Cb = capacitive load on bus line in pF. tHD;STA = hold time (repeated) START condition. After this period, the rst clock pulse is generated: > 600 ns. tHIGH = HIGH period of the SCL clock: > 600 ns. tLOW = LOW period of the SCL clock > 1300 ns. tSU;STA = set-up time for a repeated START condition: > 600 ns. tHD;DAT = data hold time: 300 ns < tHD;DAT < 900 ns. Remark: 300 ns lower limit is added because the ASIC has no internal hold time for the SDA signal. tSU;DAT = data set-up time: tSU;DAT > 100 ns. If ASIC is used in a standard mode I2C-bus system, tSU;DAT > 250 ns. tSU;STO = set-up time for STOP condition: > 600 ns. tBUF = bus free time between a STOP and a START condition: > 600 ns. Cb = capacitive load of one bus line: < 400 pF. tSU;BUSEN = bus enable set-up time: tSU;BUSEN > 10 s. tHO;BUSEN = bus enable hold time: tHO;BUSEN > 10 s. Remark: The terms SDA and SCL are the corresponding terms used by the I2C-bus for the DATA and CLOCK signals respectively.
Fig 6. I2C-bus timing diagram
8.3 3-wire bus specication

The 3-wire bus controls the write/read, clock and data lines and operates at a maximum clock frequency of 400 kHz. Hint: By using the standby bit the IC can be switched into a low current Standby mode. In Standby mode the IC must be in the WRITE mode. When the IC is switched to READ mode, during standby, the IC will hold the data line down. The standby current can be reduced by deactivating the bus interface (pin BUSENABLE LOW). If the bus interface is deactivated (pin BUSENABLE LOW) without the Standby mode being programmed, the IC maintains normal operation, but is isolated from the clock and data line.
8.3.1 Data transfer

Data sequence: byte 1, byte 2, byte 3, byte 4 and byte 5 (the data transfer has to be in this order).
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A positive edge at pin WRITE/READ enables the data transfer into the IC. The data has to be stable at the positive edge of the clock. Data may change while the clock is LOW and is written into the IC on the positive edge of the clock. Data transfer can be stopped after the transmission of new tuning information with the rst two bytes or after each following byte. A negative edge at pin WRITE/READ enables the data transfer from the IC. The WRITE/READ pin changes while the clock is LOW. With the negative edge at pin WRITE/READ the MSB of the rst byte occurs at pin DATA. The bits are shifted on the negative clock edge to pin DATA and can be read on the positive edge. To do two consecutive read or write actions, pin WRITE/READ has to be toggled for at least one clock period. When a search tuning request is sent, the IC autonomously starts searching the FM band; the search direction and search stop level can be selected. When a station with a eld strength equal to or greater than the stop level is found, the tuning system stops and the ready ag bit is set to HIGH. When, during search, a band limit is reached, the tuning system stops at the band limit and the band limit ag bit is set to HIGH. The ready ag is also set to HIGH in this case. The software programmable output (SWPORT1) can be programmed to operate as a tuning indicator output. As long as the IC has not completed a tuning action, pin SWPORT1 remains LOW. The pin becomes HIGH, when a preset or search tuning is completed or when a band limit is reached. The reference frequency divider of the synthesizer PLL is changed when the MSB in byte 5 is set to logic 1. The tuning system can then be clocked via pin XTAL2 at 6.5 MHz.
8.3.2 Power-on reset

At Power-on reset the mute is set, all other bits are random. To initialize the IC all bytes have to be transferred.
8.4 Writing data
WRITE_READ
tW(write)
50 %
tsu(clk)
CLOCK
50 %
50 % th(write) tsu(write) valid data

mhc250
DATA
50 %
Fig 7. 3-wire bus write data
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Product data sheet
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DATA BYTE 1
DATA BYTE 2
DATA BYTE 3
DATA BYTE 4
DATA BYTE 5
001aae350
Fig 8. Write mode Table 5. 7 (MSB) MUTE Table 6. Bit 7 6 5 to 0 Table 7. 7 (MSB) PLL7 Table 8. Bit 7 to 0 Table 9. 7 (MSB) SUD Table 10. Bit 7 6 and 5 4 3 2 1 0 Format of 1st data byte 6 SM 5 PLL13 4 PLL12 3 PLL11 2 PLL10 1 PLL9 0 (LSB) PLL8
Description of 1st data byte bits Symbol MUTE SM PLL[13:8] Description if MUTE = 1 then L and R audio are muted; if MUTE = 0 then L and R audio are not muted Search mode: if SM = 1 then in search mode; if SM = 0 then not in search mode setting of synthesizer programmable counter for search or preset
Format of 2nd data byte 6 PLL6 5 PLL5 4 PLL4 3 PLL3 2 PLL2 1 PLL1 0 (LSB) PLL0
Description of 2nd data byte bits Symbol PLL[7:0] Description setting of synthesizer programmable counter for search or preset
Format of 3rd data byte 6 SSL1 5 SSL0 4 HLSI 3 MS 2 MR 1 ML 0 (LSB) SWP1
Description of 3rd data byte bits Symbol SUD SSL[1:0] HLSI MS MR ML SWP1 Description Search Up/Down: if SUD = 1 then search up; if SUD = 0 then search down Search Stop Level: see Table 11 High/Low Side Injection: if HLSI = 1 then high side LO injection; if HLSI = 0 then low side LO injection Mono to Stereo: if MS = 1 then forced mono; if MS = 0 then stereo ON Mute Right: if MR = 1 then the right audio channel is muted and forced mono; if MR = 0 then the right audio channel is not muted Mute Left: if ML = 1 then the left audio channel is muted and forced mono; if ML = 0 then the left audio channel is not muted Software programmable port 1: if SWP1 = 1 then port 1 is HIGH; if SWP1 = 0 then port 1 is LOW
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Product data sheet
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Search stop level setting SSL0 0 1 0 1 Search stop level not allowed in search mode low; level ADC output = 5 mid; level ADC output = 7 high; level ADC output = 10
Table 11. SSL1 0 0 1 1 Table 12. 7 (MSB) SWP2 Table 13. Bit 7 6 5 4 3 2 1 0
Format of 4th data byte 6 STBY 5 BL 4 XTAL 3 SMUTE 2 HCC 1 SNC 0 (LSB) SI
Description of 4th data byte bits Symbol SWP2 STBY BL XTAL SMUTE HCC SNC SI Description Software programmable port 2: if SWP2 = 1 then port 2 is HIGH; if SWP2 = 0 then port 2 is LOW Standby: if STBY = 1 then in Standby mode; if STBY = 0 then not in Standby mode Band Limits: if BL = 1 then Japanese FM band; if BL = 0 then US/Europe FM band Clock frequency: see Table 16 Soft Mute: if SMUTE = 1 then soft mute is ON; if SMUTE = 0 then soft mute is OFF High Cut Control: if HCC = 1 then high cut control is ON; if HCC = 0 then high cut control is OFF Stereo Noise Cancelling: if SNC = 1 then stereo noise cancelling is ON; if SNC = 0 then stereo noise cancelling is OFF Search Indicator: if SI = 1 then pin SWPORT1 is output for the ready ag; if SI = 0 then pin SWPORT1 is software programmable port 1
Table 14. 7 (MSB) PLLREF Table 15. Bit 7
Format of 5th data byte 6 DTC 5 4 3 2 1 0 (LSB) -
Description of 5th data byte bits Symbol PLLREF Description if PLLREF = 1 then the 6.5 MHz reference frequency for the PLL is enabled; if PLLREF = 0 then the 6.5 MHz reference frequency for the PLL is disabled; see Table 16 if DTC = 1 then the de-emphasis time constant is 75 s; if DTC = 0 then the de-emphasis time constant is 50 s not used; position is dont care
6 5 to 0
DTC -
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Clock bits setting XTAL 0 1 0 1 Clock frequency 13 MHz 32.768 kHz 6.5 MHz not allowed
Table 16. PLLREF 0 0 1 1
8.5 Reading data
WRITE_READ
tW(read)
50 %
tsu(clk)
tHIGH 50 % tLOW th 50 % td 50 %
mhc249
CLOCK
50 %
DATA
Fig 9. 3-wire bus read data
DATA BYTE 1
DATA BYTE 2
DATA BYTE 3
DATA BYTE 4
DATA BYTE 5
001aae350
Fig 10. Read mode Table 17. 7 (MSB) RF Table 18. Bit 7 6 5 to 0 Table 19. 7 (MSB) PLL7 Format of 1st data byte 6 BLF 5 PLL13 4 PLL12 3 PLL11 2 PLL10 1 PLL9 0 (LSB) PLL8
Description of 1st data byte bits Symbol RF BLF PLL[13:8] Description Ready Flag: if RF = 1 then a station has been found or the band limit has been reached; if RF = 0 then no station has been found Band Limit Flag: if BLF = 1 then the band limit has been reached; if BLF = 0 then the band limit has not been reached setting of synthesizer programmable counter after search or preset
Format of 2nd data byte 6 PLL6 5 PLL5 4 PLL4 3 PLL3 2 PLL2 1 PLL1 0 (LSB) PLL0
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Description of 2nd data byte bits Symbol PLL[7:0] Description setting of synthesizer programmable counter after search or preset
Table 20. Bit 7 to 0 Table 21. 7 (MSB) STEREO Table 22. Bit 7 6 to 0 Table 23. 7 (MSB) LEV3 Table 24. Bit 7 to 4 3 to 1 0 Table 25. 7 (MSB) 0 Table 26. Bit 7 to 0
Format of 3rd data byte 6 IF6 5 IF5 4 IF4 3 IF3 2 IF2 1 IF1 0 (LSB) IF0
Description of 3rd data byte bits Symbol STEREO PLL[13:8] Description Stereo indication: if STEREO = 1 then stereo reception; if STEREO = 0 then mono reception IF counter result
Format of 4th data byte 6 LEV2 5 LEV1 4 LEV0 3 CI3 2 CI2 1 CI1 0 (LSB) 0
Description of 4th data byte bits Symbol LEV[3:0] CI[3:1] Description level ADC output Chip Identication: these bits have to be set to logic 0 this bit is internally set to logic 0
Format of 5th data byte 6 0 5 0 4 0 3 0 2 0 1 0 0 (LSB) 0
Description of 5th data byte bits Symbol Description reserved for future extensions; these bits are internally set to logic 0
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9. Internal circuitry
Table 27. Pin 1 2 Internal circuitry Symbol n.c. CPOUT Equivalent circuit
270
mhc285
3 4
VCOTANK1 VCOTANK2
120
4
120
mhc286
5 6 7 8
VCC(VCO) DGND VCCD DATA
mhc287
CLOCK
270
mhc288
10
n.c.
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Internal circuitry Symbol WRITE/READ Equivalent circuit
Table 27. Pin 11
270
11 6
mhc289
12
BUSMODE
270
12
mhc290
13
BUSENABLE
150
13
mhc291
14
SWPORT1
150
14
mhc292
15
SWPORT2
150
15
mhc293
16 17
XTAL1 XTAL2
16
17
mhc294
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Internal circuitry Symbol PHASEFIL
18
Table 27. Pin 18
Equivalent circuit
33
mhc295
19
PILFIL
270
19
33
mhc296
20 21 22
n.c. n.c. VAFL
10
22
33
mhc297
23
VAFR
10
23
33
mhc298
24
TMUTE
24
1 k
33
mhc299
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Internal circuitry Symbol MPXO Equivalent circuit
Table 27. Pin 25
150
25
33
mhc300
26
Vref
26
mhc301
33
27
TIFC
40 k
27
mhc302
28
LIMDEC1
270
28
mhc303
29
LIMDEC2
270
29
mhc304
30 31
n.c. n.c.
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Internal circuitry Symbol Igain
32
Table 27. Pin 32
Equivalent circuit
mhc305
33 34 35 36 37
AGND VCCA RFI1 RFGND RFI2

35 37
36
mhc306
38
TAGC
38
36
mhc307
39
LOOPSW
5
39
mhc308
40
n.c.
10. Limiting values

Table 28. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VVCOTANK1 VVCOTANK2 VCCD VCCA Tstg Tamb Parameter VCO tuned circuit output voltage 1 VCO tuned circuit output voltage 2 digital supply voltage analog supply voltage storage temperature ambient temperature Conditions Min 0.3 0.3 0.3 0.3 55 10 Max +8 +8 +5 +8 +150 +75 Unit V V V V C C
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Table 28. Limiting values continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Vesd Parameter electrostatic discharge voltage Conditions all pins except pin DATA pin DATA
[1] [2] [1] [2]
Min 200 2000 150 2000
Max +200 +2000 +200 +2000
Unit V V V V
[1] [2]
Machine model (R = 0 , C = 200 pF). Human body model (R = 1.5 k, C = 100 pF).
11. Thermal characteristics

Table 29. Symbol Rth(j-a) Thermal characteristics Parameter Conditions Typ 29 Unit K/W thermal resistance from junction to in free air ambient
12. Static characteristics

Table 30. Static characteristics VCCA = VCC(VCO) = VCCD = 2.7 V; Tamb = 25 C; All AC values are given in RMS unless otherwise specied. Symbol Supply VCCA VCC(VCO) VCCD ICCA Parameter analog supply voltage VCO supply voltage digital supply voltage analog supply current operating VCCA = 3 V VCCA = 5 V Standby mode VCCA = 3 V VCCA = 5 V ICC(VCO) VCO supply current operating VCC(VCO) = 3 V VCC(VCO) = 5 V Standby mode VCC(VCO) = 3 V VCC(VCO) = 5 V 1 1.2 2 2.2 A A 560 570 750 760 940 950 A A 3 3.2 6 6.2 A A 6.0 6.2 8.4 8.6 10.5 10.7 mA mA Conditions Min 2.5 2.5 2.5 Typ 3.0 3.0 3.0 Max 5.0 5.0 5.0 Unit V V V voltages[1]
Supply currents
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Table 30. Static characteristics continued VCCA = VCC(VCO) = VCCD = 2.7 V; Tamb = 25 C; All AC values are given in RMS unless otherwise specied. Symbol ICCD Parameter digital supply current Conditions operating VCCD = 3 V VCCD = 5 V Standby mode; VCCD = 3 V bus enable line HIGH bus enable line LOW Standby mode; VCCD = 5 V bus enable line HIGH bus enable line LOW
[1] VCCA, VCC(VCO) and VCCD must not differ by more than 200 mV.
Min 2.1 2.25 30 11 50 20
Typ 3.0 3.15 56 19 78 33
Max 3.9 4.05 80 26 105 45
Unit mA mA A A A A
Table 31. DC operating points, unloaded DC voltage VCCA = VCC(VCO) = VCCD = 2.7 V; Tamb = 25 C; unless otherwise specied. Operating Conditions point VCPOUT VXTAL2 VXTAL2 VPHASEFIL VPILFIL VAFL VAFR VTMUTE VMPXO Vref VTIFC VLIMDEC1 VLIMDEC2 VIgain VRFI1 VRFI2 VTAGC VRF = 0 V fRF = 98 MHz; VRF = 1 mV fRF = 98 MHz; VRF = 1 mV VRF = 0 V fRF = 98 MHz; VRF = 1 mV data byte 4 bit 4 = 1 data byte 4 bit 4 = 0 data byte 4 bit 4 = 1 data byte 4 bit 4 = 0 Min 0.1 1.64 1.68 1.64 1.68 0.4 0.65 720 720 1.5 680 1.45 1.34 1.86 1.86 480 0.93 0.93 1 Typ 1.72 1.75 1.72 1.75 1.2 0.9 850 850 1.65 815 1.55 1.44 1.98 1.98 530 1.03 1.03 1.57 Max VCC(VCO) 0.1 1.8 1.82 1.8 1.82 VCCA 0.4 1.3 940 940 1.8 950 1.65 1.54 2.1 2.1 580 1.13 1.13 2 Unit V V V V V V V mV mV V mV V V V V mV V V V
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13. Dynamic characteristics

Table 32. Dynamic characteristics VCCA = VCCD = VCC(VCO) = 2.7 V; Tamb = 25 C; AC values given in RMS; For VRF the emf value is given; unless otherwise specied. Symbol VCO fosc oscillator frequency 150 217 MHz Crystal oscillator Circuit input: pin XTAL2 Vi(osc) Ri oscillator input voltage input resistance oscillator externally clocked oscillator externally clocked data byte 4 bit 4 = 0 data byte 4 bit 4 = 1 Ci input capacitance oscillator externally clocked data byte 4 bit 4 = 0 data byte 4 bit 4 = 1 Crystal: 32.768 kHz fr f/fr C0 RS fr/fr(25 C) fr f/fr C0 Cmot RS fr/fr(25 C) Synthesizer Programmable divider[1] Nprog programmable divider ratio data byte 1 = XX11 1111; data byte 2 = 1111 1110 data byte 1 = XX01 0000; data byte 2 = 0000 0000 Nstep programmable divider step size crystal oscillator divider ratio data byte 4 bit 4 = 0 data byte 5 bit 7 = 1; data byte 4 bit 4 = 0 data byte 4 bit 4 = 1
TEA5767HN_5
Parameter
Conditions
Min
Typ
Max
Unit
140 2 230 3.9 5 -
3 330 5.6 6 32.768
350 4 430 7.3 7 +20 106 3.5 80 +50 106 +30 106 4.5 3.0 100 +30 106
mV k k pF pF kHz
series resonance frequency frequency deviation shunt capacitance series resistance temperature drift series resonance frequency frequency deviation shunt capacitance motional capacitance series resistance temperature drift
data byte 4 bit 4 = 1
20 106 10 C < Tamb < +60 C data byte 4 bit 4 = 0 -
pF k
50 106 13
Crystal: 13 MHz MHz
30 106 1.5 40 C < Tamb < +85 C -
pF fF k
30 106 -
2048 -
8191 -
Reference frequency divider Nref 260 130 1 -
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Table 32. Dynamic characteristics continued VCCA = VCCD = VCC(VCO) = 2.7 V; Tamb = 25 C; AC values given in RMS; For VRF the emf value is given; unless otherwise specied. Symbol Isink Parameter charge pump peak sink current Conditions 0.2 V < VCPOUT < VVCOTANK2 0.2 V; fVCO > fref Nprog Min Typ 0.5 Max Unit A Charge pump: pin CPOUT
Isource
charge pump peak source 0.2 V < VCPOUT < current VVCOTANK2 0.2 V; fVCO < fref Nprog RF input voltage for correct IF count IF counter length IF counter prescaler ratio IF counter period IF counter resolution IF counter result for search tuning stop fxtal = 32.768 kHz fxtal = 13 MHz fxtal = 32.768 kHz fxtal = 13 MHz fxtal = 32.768 kHz fxtal = 13 MHz
0.5
IF counter VRF NIF Nprecount Tcount(IF) REScount(IF) IFcount 29h 30h 10 12 7 64 15.625 15.754 4.096 4.0625 18 3Dh 3Dh V bit ms ms kHz kHz M
Pins DATA, CLOCK, WRITE/READ, BUSMODE and BUSENABLE Ri input resistance
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Table 32. Dynamic characteristics continued VCCA = VCCD = VCC(VCO) = 2.7 V; Tamb = 25 C; AC values given in RMS; For VRF the emf value is given; unless otherwise specied. Symbol Parameter Conditions Min Typ Max Unit Software programmable ports Pin SWPORT1 Isink(max) maximum sink current data byte 3 bit 0 = 0; data byte 4 bit 0 = 0; VSWPORT1 < 0.5 V 500 A
Ileak(max)
maximum leakage current data byte 3 bit 0 = 1; VSWPORT1 < 5 V maximum sink current data byte 4 bit 7 = 0; VSWPORT1 < 0.5 V
+1
Pin SWPORT2 Isink(max) Ileak(max) 500 1 +1 A A
maximum leakage current data byte 4 bit 7 = 1; VSWPORT1 < 5 V
FM signal channel FM RF input fFM(ant) Ri Ci VRF FM input frequency input resistance at pins RFI1 and RFI2 to RFGND input capacitance at pins RFI1 and RFI2 to RFGND RF sensitivity input voltage fRF = 76 MHz to 108 MHz; f = 22.5 kHz; fmod = 1 kHz; (S+N)/N = 26 dB; L = R; de-emphasis = 75 s; BAF = 300 Hz to 15 kHz f1 = 200 kHz; f2 = 400 kHz; ftune = 76 MHz to 108 MHz f1 = 4 MHz; f2 = 8 Hz; ftune = 76 MHz to 108 MHz 76 75 2.5 100 4 2 108 125 6 3.5 MHz pF V
IP3in
in-band 3rd-order intercept point related to VRFI1-RFI2 (peak value) out-band 3rd-order intercept point related to VRFI1-RFI2 (peak value) RF input voltage for start of AGC
81
84
dBV
IP3out
82
85
dBV
RF AGC VRF1 fRF1 = 93 MHz; fRF2 = 98 MHz; VRF2 = 50 dBV;

[2]
66
72
78
dBV
V TMUTE 14 mV ----------------------- < ------------------- 3 dBV V RF1

IF lter fIF BIF S+200 S200 S+100 IF lter center frequency IF lter bandwidth high side 200 kHz selectivity low side 200 kHz selectivity high side 100 kHz selectivity f = +200 kHz; ftune = 76 MHz to 108 MHz f = 200 kHz; ftune = 76 MHz to 108 MHz f = +100 kHz; ftune = 76 MHz to 108 MHz
[3]
215 85 39 32 8
225 94 43 36 12
235 102 -
kHz kHz dB dB dB
[3]
[3]
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Table 32. Dynamic characteristics continued VCCA = VCCD = VCC(VCO) = 2.7 V; Tamb = 25 C; AC values given in RMS; For VRF the emf value is given; unless otherwise specied. Symbol S-100 IR Parameter low side 100 kHz selectivity image rejection Conditions f = 100 kHz; ftune = 76 MHz to 108 MHz ftune = 76 MHz to 108 MHz; VRF = 50 dBV read mode data byte 4 bit 4 = 1
[3]
Min 8 24
Typ 12 30
Max -
Unit dB dB
FM IF level detector and mute voltage VRF Vstep Pin TMUTE Vlevel Vlevel(slope) Ro VMPXO level output DC voltage slope of level voltage VRF = 0 V VRF = 3 V VRF = 10 V to 500 V 1.55 1.60 150 1.65 1.70 165 1.80 1.85 180 V V RF input voltage for start of level ADC level ADC step size 2 2 3 3 5 5 V dB
mV ------------20 dB
k mV
output resistance demodulator output voltage VRF = 1 mV; L = R; f = 22.5 kHz; fmod = 1 kHz; de-emphasis = 75 s; BAF = 300 Hz to 15 kHz VRF = 1 mV; L = R; f = 22.5 kHz; fmod = 1 kHz; de-emphasis = 75 s; BAF = 300 Hz to 15 kHz VRF = 1 mV; L = R; f = 75 kHz; fmod = 1 kHz; de-emphasis = 75 s VRF = 300 V; L = R; f = 22.5 kHz; fmod = 1 kHz; m = 0.3; de-emphasis = 75 s; BAF = 300 Hz to 15 kHz
280 60
400 75
520 90
FM demodulator: pin MPXO
(S+N)/N
maximum signal plus noise-to-noise ratio
54
60
dB
THD
0.5
1.5
AM
AM suppression
40
dB
Ro Isink Soft mute VRF mute
demodulator output resistance demodulator output sink current RF input voltage for soft mute start mute attenuation mute = 3 dB; data byte 4 bit 3 = 1 VRF = 1 V; L = R; f = 22.5 kHz; fmod = 1 kHz; de-emphasis = 75 s; BAF = 300 Hz to 15 kHz; data byte 4 bit 3 = 1
500 30
3 4
5 7
10 15
V dB
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Table 32. Dynamic characteristics continued VCCA = VCCD = VCC(VCO) = 2.7 V; Tamb = 25 C; AC values given in RMS; For VRF the emf value is given; unless otherwise specied. Symbol VAFL Parameter left audio frequency output voltage right audio frequency output voltage left audio frequency output resistance right audio frequency output resistance left audio frequency output sink current right audio frequency output sink current input overdrive margin left audio frequency output voltage difference right audio frequency output voltage difference THD < 3 % VRF = 1 mV; L = R; f = 75 kHz; fmod = 1 kHz; de-emphasis = 75 s VRF = 1 mV; L = R; f = 75 kHz; fmod = 1 kHz; de-emphasis = 75 s Conditions VRF = 1 mV; L = R; f = 22.5 kHz; fmod = 1 kHz; de-emphasis = 75 s VRF = 1 mV; L = R; f = 22.5 kHz; fmod = 1 kHz; de-emphasis = 75 s Min 60 Typ 75 Max 90 Unit mV MPX decoder
VAFR
60
75
90
mV
RAFL RAFR Isink(AFL) Isink(AFR) VMPXIN(max) VAFL
170 170 4 -1
50 50 +1
A A dB dB
VAFR
-1
+1
dB
cs(stereo)
stereo channel separation VRF = 1 mV; R = L = 0 or R = 0 and L = 1 including 9 % pilot; f = 75 kHz; fmod = 1 kHz; data byte 3 bit 3 = 0; data byte 4 bit 1 = 1 maximum signal plus noise-to-noise ratio VRF = 1 mV; L = R; f = 22.5 kHz; fmod = 1 kHz; de-emphasis = 75 s; BAF = 300 Hz to 15 kHz VRF = 1 mV; L = R; f = 75 kHz; fmod = 1 kHz; de-emphasis = 75 s related to f = 75 kHz; fmod = 1 kHz; de-emphasis = 75 s VRF = 1 mV; read mode data byte 3 bit 7 = 1 data byte 3 bit 7 = 0 VRF = 1 mV
24
30
dB
(S+N)/N
54
60
dB
THD
0.4
pilot
pilot suppression measured at pins VAFL and VAFR stereo pilot frequency deviation
40
50
dB
fpilot
1 2
3.6 3 -
5.8 -
kHz kHz dB
f pilot1 ---------------f pilot2
pilot switch hysteresis
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Table 32. Dynamic characteristics continued VCCA = VCCD = VCC(VCO) = 2.7 V; Tamb = 25 C; AC values given in RMS; For VRF the emf value is given; unless otherwise specied. Symbol TCde-em Parameter de-emphasis time constant Conditions VRF = 1 mV data byte 5 bit 6 = 0 data byte 5 bit 6 = 1 VRF = 1 V data byte 5 bit 6 = 0 data byte 5 bit 6 = 1 Mono to stereo blend control cs(stereo) stereo channel separation VRF = 45 V; R = L = 0 or R = 0 and L = 1 including 9 % pilot; f = 75 kHz; fmod = 1 kHz; data byte 3 bit 3 = 0; data byte 4 bit 1 = 1 stereo channel separation switching from mono to stereo with increasing RF input level R = L = 0 or R = 0 and L = 1 including 9 % pilot; f = 75 kHz; fmod = 1 kHz; data byte 3 bit 3 = 0; data byte 4 bit 1 = 0 VRF = 1 mV VRF = 20 V Bus-driven mute functions 24 1 dB dB 4 10 16 dB 114 171 150 225 186 279 s s 38 57 50 75 62 93 s s Min Typ Max Unit High cut control
Mono to stereo switched cs(stereo)
Tuning mute
mute mute(L) mute(R) VAFL and VAFR muting depth VAFL muting depth VAFR muting depth data byte 1 bit 7 = 1 data byte 3 bit 1 = 1; fAF = 1 kHz; Rload(L) < 30 k data byte 3 bit 2 = 1; fAF = 1 kHz; Rload(R) < 30 k 60 80 80 dB dB dB
[1]
Calculation of this 14-bit word can be done as follows: formula for high side injection:
4 ( f RF + f IF ) 4 ( f RF f IF ) N = -------------------------------------- ; formula for low side injection: N = -------------------------------------f ref f ref
where: N = decimal value of PLL word; fRF = the wanted tuning frequency [Hz]; fIF = the intermediate frequency [Hz] = 225 kHz; fref = the reference frequency [Hz] = 32.768 kHz for the 32.768 kHz crystal; fref = 50 kHz for the 13 MHz crystal or when externally clocked with 6.5 MHz. Example for receiving a channel at 100 MHz with high side injection: The PLL word becomes 2FCAh. [2] [3] VRF in Figure 13 is replaced by VRF1 + VRF2. The radio is tuned to 98 MHz (high side injection). Low side and high side selectivity can be switched by changing the mixer from high side to low side LO injection.
4 ( 100 10 + 225 10 ) N = ------------------------------------------------------------------- = 12234 32768
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14. FM characteristics
001aae351
0 VAFL, VAFR (dB) 20

(1)
4 THD+N (%) 3
40
60
(2)
1
(3)
80 101
10
102
103
104
105 VRF (V)
0 106
(1) Mono signal, no soft mute, f = 22,5 kHz. (2) Noise in mono mode, no soft mute. (3) Total Harmonic Distortion (THD), f = 75 kHz.
Fig 11. FM mono characteristics
0
(1)
001aae352
4 THD+N (%)
VAFL, VAFR (dB) 20
(2)
40
(3)
60
1
(4)
80 101
10
102
103
104
105 VRF (V)
0 106
(1) Right channel with modulation right, SNC on, f = 67,5 kHz + 6,75 kHz pilot. (2) Left channel with modulation left, SNC on, f = 67,5 kHz + 6,75 kHz pilot. (3) Noise in stereo mode, SNC on, f = 0 kHz + 6,75 kHz pilot. (4) Total Harmonic Distortion (THD), f = 67,5 kHz + 6,75 kHz pilot.
Fig 12. FM stereo characteristics
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15. I2C-bus characteristics

Table 33. Digital levels and timing Conditions Min Max Unit V V A mV kHz kHz s s s s s s ns ns ns ns ns Symbol Parameter Digital inputs VIH VIL Isink(L) VOL Timing fclk tHIGH tLOW tW(write) tW(read) tsu(clk) th(out) td(out) tsu(write) th(write) clock input frequency clock HIGH time clock LOW time pulse width for write enable pulse width for read enable clock set-up time read mode output delay time write mode set-up time write mode hold time I2C-bus enabled 3-wire bus enabled I2C-bus enabled 3-wire bus enabled I2C-bus enabled 3-wire bus enabled 3-wire bus enabled 3-wire bus enabled 3-wire bus enabled 3-wire bus enabled 3-wire bus enabled 3-wire bus enabled 1 1 1 1 1 1 300 10 100 100 400 400 400 HIGH-level input voltage LOW-level input voltage LOW-level sink current LOW-level output voltage IOL = 500 A 0.45VCCD 500 0.2VCCD 450
Digital outputs
read mode data output hold time 3-wire bus enabled
16. Test information

Table 34. R1 D1 and D2 L1 L2 and L3 XTAL13MHz Cpull Component list for Figure 1 and Figure 13 Parameter resistor with low temperature coefcient varicap for VCO tuning RF band lter coil VCO coil 13 MHz crystal pulling capacitor for NX4025GA pulling capacitor for XTAL32768Hz Value 18 k 120 nH 33 nH 10 pF Cload
[1]
Component
Tolerance Type 1 % 2 % 2 % RC12G BB202 Qmin = 40 Qmin = 40 NX4025GA
Manufacturer Philips Philips
XTAL32768Hz 32,768 kHz crystal Cpull

[1]
Value of the Cpull must be as close as possible to the value of Cload of the crystal.
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Product data sheet Rev. 05 26 January 2007
NXP B.V. 2007. All rights reserved. TEA5767HN_5
NXP Semiconductors
47 nF LIMDEC2 29 R1 Igain 32 GAIN STABILIZATION AGND 33 22 nF VCCA 4.7 22 F VCCA 34 RESONANCE AMPLIFIER LIMITER
47 nF LIMDEC1 28
47 nF TIFC 27
33 nF Vref 26 MPXO 25
33 nF TMUTE 24 VAFR 23 VAFL 22
POWER SUPPLY
DEMODULATOR
SOFT MUTE SDS
I/Q-MIXER 1st FM
2 N1 IF CENTRE FREQUENCY ADJUST
LEVEL ADC
IF COUNTER MPX DECODER
19 PILFIL
1 nF
33 k 22 nF 22 nF
100 pF RFI1 35 40 VRF 4.7 nF LOOPSW 39 L1 27 pF RFGND 36 47 pF RFI2 37 AGC
Iref
18 PHASEFIL 17 XTAL2
Ccomp(1) 32.768 kHz or 13 MHz
TEA5767HN
TAGC 38 programmable divider output TUNING SYSTEM reference frequency divider output MUX
CRYSTAL OSCILLATOR
Cpull(1) 16 XTAL1 15 SWPORT2 10 k 14 SWPORT1 10 k
SOFTWARE PROGRAMMABLE PORT pilot mono
VCCA
13 BUSENABLE 12 BUSMODE 11 WRITE/READ 1, 10, 20, 21, 30, 31, 40 n.c.

mhc284
VCO
I2C-BUS AND 3-WIRE BUS 4 VCOTANK2 5 VCC(VCO) VCCD 6 DGND 12 22 nF 7 VCCD 8 DATA 9 CLOCK
CPOUT VCOTANK1 10 nF 39 nF 10 k L3 100 k L2
D1
D2
TEA5767HN
47
22 nF VCC(VCO)
Value of Cpull must be as close as possible to the value of Cload of the crystal. (1) Ccomp and Cpull data depends on crystal specication.
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Fig 13. Application and test diagram
NXP Semiconductors
TEA5767HN
17. Package outline

HVQFN40: plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 x 6 x 0.85 mm
SOT618-1
terminal 1 index area E A A1
detail X
e1 e 11 L 10 21 e
1/2 e
C b 20 v M C A B w M C y1 C y
Eh
1/2 e
e2
1 terminal 1 index area
30 40 Dh 0 2.5 scale E(1) 6.1 5.9 Eh 4.25 3.95 e 0.5 e1 4.5 e2 4.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 5 mm 31 X
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D(1) 6.1 5.9 Dh 4.25 3.95
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT618-1 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-22
Fig 14. Package outline SOT618-1 (HVQFN40)

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NXP Semiconductors
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18. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 Surface mount reow soldering description.
18.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for ne pitch SMDs. Reow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
18.2 Wave and reow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
Through-hole components Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature prole. Leaded packages, packages with solder balls, and leadless packages are all reow solderable. Key characteristics in both wave and reow soldering are:
Board specications, including the board nish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus PbSn soldering
18.3 Wave soldering

Key characteristics in wave soldering are:
Process issues, such as application of adhesive and ux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
Solder bath specications, including temperature and impurities

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18.4 Reow soldering

Key characteristics in reow soldering are:
Lead-free versus SnPb soldering; note that a lead-free reow process usually leads to
higher minimum peak temperatures (see Figure 15) than a PbSn process, thus reducing the process window
Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
Reow temperature prole; this prole includes preheat, reow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classied in accordance with Table 35 and 36
Table 35. SnPb eutectic process (from J-STD-020C) Package reow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 36. 235 220 Lead-free process (from J-STD-020C) Package reow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reow soldering, see Figure 15.
TEA5767HN_5
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temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 15. Temperature proles for large and small components
For further information on temperature proles, refer to Application Note AN10365 Surface mount reow soldering description.
TEA5767HN_5
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19. Revision history

Table 37. Revision history Release date 20070126 Data sheet status Product data sheet Change notice Supersedes TEA5767HN_4 Document ID TEA5767HN_5 Modications: TEA5767HN_4 TEA5767HN_3 (9397 750 13531) TEA5767HN_2 (9397 750 12071) TEA5767HN_1 (9397 750 09626)
Modied: Section 13 Dynamic characteristics values of Soft mute, mute attenuation are changed Product data sheet Product specication Preliminary specication Preliminary specication TEA5767HN_3 (9397 750 13531) TEA5767HN_2 (9397 750 12071) TEA5767HN_1 (9397 750 09626) -
20060220 20040920 20031112 20020913
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20. Legal information

20.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualication Production
Denition This document contains data from the objective specication for product development. This document contains data from the preliminary specication. This document contains the product specication.
Please consult the most recently issued document before initiating or completing a design. The term short data sheet is explained in section Denitions. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
20.2 Denitions
Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales ofce. In case of any inconsistency or conict with the short data sheet, the full data sheet shall prevail.
result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specied use without further testing or modication. Limiting values Stress above one or more limiting values (as dened in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/prole/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
20.3 Disclaimers
General Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to
20.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus logo is a trademark of NXP B.V.
21. Contact information

For additional information, please visit: http://www.nxp.com For sales ofce addresses, send an email to: salesaddresses@nxp.com
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Product data sheet
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NXP Semiconductors
TEA5767HN
22. Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 8 8.1 8.1.1 8.1.2 8.2 8.3 8.3.1 8.3.2 8.4 8.5 9 10 11 12 13 14 15 16 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Low-noise RF amplier . . . . . . . . . . . . . . . . . . . 6 FM mixer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . 7 PLL tuning system . . . . . . . . . . . . . . . . . . . . . . 7 RF AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 IF lter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 FM demodulator . . . . . . . . . . . . . . . . . . . . . . . . 7 Level voltage generator and analog-to-digital converter . . . . . . . . . . . . . . . . 7 IF counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Soft mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 MPX decoder . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Signal dependent mono to stereo blend . . . . . . 8 Signal dependent AF response . . . . . . . . . . . . 8 Software programmable ports . . . . . . . . . . . . . 8 I2C-bus and 3-wire bus . . . . . . . . . . . . . . . . . . . 8 2C-bus, 3-wire bus and bus-controlled I functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 I2C-bus specication . . . . . . . . . . . . . . . . . . . . 10 Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 11 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 11 3-wire bus specication . . . . . . . . . . . . . . . . . 12 Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 13 Writing data . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Reading data . . . . . . . . . . . . . . . . . . . . . . . . . 16 Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 18 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 22 Thermal characteristics. . . . . . . . . . . . . . . . . . 23 Static characteristics. . . . . . . . . . . . . . . . . . . . 23 Dynamic characteristics . . . . . . . . . . . . . . . . . 25 FM characteristics . . . . . . . . . . . . . . . . . . . . . . 31 I2C-bus characteristics . . . . . . . . . . . . . . . . . . 32 Test information . . . . . . . . . . . . . . . . . . . . . . . . 32 17 18 18.1 18.2 18.3 18.4 19 20 20.1 20.2 20.3 20.4 21 22 Package outline . . . . . . . . . . . . . . . . . . . . . . . . Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reow soldering . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Reow soldering. . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Denitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 35 35 35 35 36 38 39 39 39 39 39 39 40
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information.
NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 26 January 2007 Document identifier: TEA5767HN_5

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TEA5767HN

Low-power FM stereo radio for handheld applications

3. Quick reference data

Min 2.5 2.5

Typ 3.0 3.0

Max Unit 5.0 5.0 V V

2.5 6.0 560 2.1 30 11 76 10

3.0 8.4 3 750 1 3.0 56 19 -

5.0 6 940 2 3.9 80 26 108 +75

S200 S+200 VAFL

NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 05 26 January 2007

stereo channel separation

total harmonic distortion

NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 05 26 January 2007

33 nF TMUTE 24 VAFR 23 VAFL 22

SOFT MUTE SDS

2 N1 IF CENTRE FREQUENCY ADJUST

IF COUNTER MPX DECODER

100 pF RFI1 35 L1 27 pF RFGND 36 47 pF RFI2 37 AGC

Ccomp(1) 32.768 kHz or 13 MHz

Cpull(1) 16 XTAL1 15 SWPORT2 10 k 14 SWPORT1 10 k 13 BUSENABLE 12 BUSMODE

Low-power FM stereo radio for handheld applications

1, 10, 20, 21, 30, 31, 40 n.c.

Fig 1. Block diagram

n.c. 10 WRITE/READ 11 BUSMODE 12 BUSENABLE 13 SWPORT1 14 SWPORT2 15 XTAL1 16 XTAL2 17 PHASEFIL 18

Transparent top view

Fig 2. Pin conguration

6.2 Pin description

Product data sheet

Rev. 05 26 January 2007

NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 05 26 January 2007

7.4 Crystal oscillator

7.5 PLL tuning system

7.9 Level voltage generator and analog-to-digital converter

7.11 Soft mute

7.12 MPX decoder

Product data sheet

Rev. 05 26 January 2007

7.13 Signal dependent mono to stereo blend

7.14 Signal dependent AF response

7.15 Software programmable ports

7.16 I2C-bus and 3-wire bus

NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 05 26 January 2007

Completed bytes are written to the destinastion register

Search Mode? yes no Signal level OK?

IF frequency OK? yes

Set 'found' flag

Upper tuning limit exceeded? no

Lower tuning limit exceeded? no

Set 'band limit' flag

Fig 3. Flowchart auto search or preset

NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 05 26 January 2007

8. I2C-bus, 3-wire bus and bus-controlled functions