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PIC mic ocon olle

F om Wikipedia, he f ee enc clopedia

PIC i a famil of modified Ha a d a chi ec e mic ocon olle made b Mic ochip Technolog , de i ed f om he PIC1650[1][2][3] o iginall de eloped b Gene al In men ' Mic oelec onic Di i ion. The name PIC ini iall efe ed o "Pe iphe al In e face Con olle ".[4][5] PIC a e pop la i h bo h ind ial de elope and hobb i alike d e o hei lo co , ide a ailabili , la ge e ba e, e en i e collec ion of applica ion no e , a ailabili of lo co o f ee de elopmen ool , and e ial p og amming (and e-p og amming i h fla h memo ) capabili . Mic ochip anno nced on Sep embe 2011 he hipmen of i PIC p oce o .[6] en billion h
PIC mic ocon olle package in DIP and QFN

Con en
1 Co e a chi ec e 1.1 Da a pace (RAM) 1.2 Code pace 1.3 Wo d i e 1.4 S ack 1.5 In c ion e 1.6 Pe fo mance 1.7 Ad an age 1.8 Limi a ion 1.9 Compile de elopmen 2 Famil co e a chi ec al diffe ence 2.1 Ba eline co e de ice 2.2 Mid- ange co e de ice 2.3 Enhanced Mid- ange co e de ice 2.4 PIC17 high end co e de ice 2.5 PIC18 high end co e de ice 2.6 PIC24 and d PIC 16-bi mic ocon olle 2.7 PIC32 32-bi mic ocon olle 3 De ice a ian and ha d a e fea e 3.1 Va ian 3.2 T end 4 Hi o 5 PIC clone 6 De elopmen ool 7 De ice p og amme 8 Deb gging
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16-bi 28-pin PDIP PIC24 mic ocon olle ne o a me ic

le

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8.1 S 8.2 I 8.3 I 9 PICK 2 10 P 11 S 12 R 13 E

Co e a chi ec
T PIC S N A M O ) A RAM ( :// 1. A A D T ). T , RAM

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: (H . (2 (W0), ( , ) / D /35007 . ( CPU, , ( RAM . 256 4 (. . .[3] ) ), 8), ) PIC32, V

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PIC .T , .I T FSR, FSR. L .T E
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RAM. S PIC , , " " (FSR) " INDF FSR , . " (INDF) PIC18 / .A .L

(SP). .
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Code space
The code pace i gene all implemen ed a ROM, EPROM o fla h ROM. In gene al, e e nal code memo i no di ec l add e able d e o he lack of an e e nal memo in e face. The e cep ion a e PIC17 and elec high pin co n PIC18 de ice .[7]

Word si e
All PIC handle (and add e ) da a in 8-bi ch nk . Ho e e , he ni of add e abili of he code pace i no gene all he ame a he da a pace. Fo e ample, PIC in he ba eline and mid- ange familie ha e p og am memo add e able in he ame o d i e a he in c ion id h, i.e. 12 o 14 bi e pec i el . In con a , in he PIC18 e ie , he p og am memo i add e ed in 8-bi inc emen (b e ), hich diffe f om he in c ion id h of 16 bi . In o de o be clea , he p og am memo han in b e . capaci i all a ed in n mbe of ( ingle o d) in c ion , a he

Stacks
PIC ha e a ha d a e call ack, hich i ed o a e e n add e e . The ha d a e ack i no of a e acce ible on ea lie de ice , b hi changed i h he 18 e ie de ice . Ha d a e ppo fo a gene al p po e pa ame e ack a lacking in ea l e ie , b hi g ea l imp o ed in he 18 e ie , making he 18 e ie a chi ec e mo e f iendl o high le el lang age compile .

Instruction set
A PIC' in c ion a f om abo 35 in c ion fo he lo -end PIC o o e 80 in c ion fo he high-end PIC . The in c ion e incl de in c ion o pe fo m a a ie of ope a ion on egi e di ec l , he acc m la o and a li e al con an o he acc m la o and a egi e , a ell a fo condi ional e ec ion, and p og am b anching. Some ope a ion , ch a bi e ing and e ing, can be pe fo med on an n mbe ed egi e , b a i hme ic ope a ion al a in ol e W ( he acc m la o ), i ing he e l back o ei he W o egi e . To load a con an , i i nece a o load i in o W befo e i can be mo ed in o ano he olde co e , all egi e mo e needed o pa h o gh W, b hi changed on he "high end" co bi-ope and he o he ope and egi e . On he e.

PIC co e ha e kip in c ion hich a e ed fo condi ional e ec ion and b anching. The kip in c ion a e ' kip if bi e ' and ' kip if bi no e '. Beca e co e befo e PIC18 had onl ncondi ional b anch in c ion , condi ional j mp a e implemen ed b a condi ional kip ( i h he oppo i e condi ion) follo ed b an ncondi ional b anch. Skip a e al o of ili fo condi ional e ec ion of an immedia e ingle follo ing in c ion. The 18 e ie implemen ed hado egi e hich a e e e al impo an egi e d ing an in e ha d a e ppo fo a oma icall a ing p oce o a e hen e icing in e p . In gene al, PIC in c ion fall in o 5 cla e : (mo e li e al o
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p , p o iding

1. Ope a ion on o king egi e (WREG) i h 8-bi immedia e ("li e al") ope and. E.g.
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2. 3.

4. 5.

WREG), (AND literal with WREG). One instruction peculiar to the PIC is , load immediate into WREG and return, which is used with computed branches to produce lookup tables. Operation with WREG and indexed register. The result can be written to either the Working register (e.g. e ). or the selected register (e.g. g e ). g Bit operations. These take a register number and a bit number, and perform one of 4 actions: set or clear a bit, and test and skip on set/clear. The latter are used to perform conditional branches. The usual ALU status flags are available in a numbered register so operations such as "branch on carry clear" are possible. Control transfers. Other than the skip instructions previously mentioned, there are only two: and . A few miscellaneous zero-operand instructions, such as return from subroutine, and to enter lowpower mode.

Performance
The architectural decisions are directed at the maximization of speed-to-cost ratio. The PIC architecture was among the first scalar CPU designs,[ci a ion needed] and is still among the simplest and cheapest. The Harvard architecturein which instructions and data come from separate sourcessimplifies timing and microcircuit design greatly, and this benefits clock speed, price, and power consumption. The PIC instruction set is suited to implementation of fast lookup tables in the program space. Such lookups take one instruction and two instruction cycles. Many functions can be modeled in this way. Optimization is facilitated by the relatively large program space of the PIC (e.g. 4096 14-bit words on the 16F690) and by the design of the instruction set, which allows for embedded constants. For example, a branch instruction's target may be indexed by W, and execute a "RETLW" which does as it is named - return with literal in W. Interrupt latency is constant at three instruction cycles. External interrupts have to be synchronized with the four clock instruction cycle, otherwise there can be a one instruction cycle jitter. Internal interrupts are already synchronized. The constant interrupt latency allows PICs to achieve interrupt driven low jitter timing sequences. An example of this is a video sync pulse generator. This is no longer true in the newest PIC models, because they have a synchronous interrupt latency of three or four cycles.

Ad antages
The PIC architectures have these advantages: Small instruction set to learn RISC architecture Built in oscillator with selectable speeds Easy entry level, in circuit programming plus in circuit debugging PICKit units available from Microchip.com for less than $50 Inexpensive microcontrollers Wide range of interfaces including I C, SPI, USB, USART, A/D, programmable comparators, PWM, LIN, CAN, PSP, and Ethernet[8]

Limitations
The PIC architectures have these limitations:
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One accumulator Register-bank switching is required to access the entire RAM of many devices Operations and registers are not orthogonal; some instructions can address RAM and/or immediate constants, while others can only use the accumulator The following stack limitations have been addressed in the PIC18 series, but still apply to earlier cores: The hardware call stack is not addressable, so preemptive task switching cannot be implemented Software-implemented stacks are not efficient, so it is difficult to generate reentrant code and support local variables With paged program memory, there are two page sizes to worry about: one for CALL and GOTO and another for computed GOTO (typically used for table lookups). For example, on PIC16, CALL and GOTO have 11 bits of addressing, so the page size is 2048 instruction words. For computed GOTOs, where you add to PCL, the page size is 256 instruction words. In both cases, the upper address bits are provided by the PCLATH register. This register must be changed every time control transfers between pages. PCLATH must also be preserved by any interrupt handler.[9]

Compiler development
While several commercial compilers are available, in 2008, Microchip released their own C compilers, C18 and C30, for the line of 18F 24F and 30/33F processors. The easy to learn RISC instruction set of the PIC assembly language code can make the overall flow difficult to comprehend. Judicious use of simple macros can increase the readability of PIC assembly language. For example, the original Parallax PIC assembler ("SPASM") has macros which hide W and make the PIC look like a twoaddress machine. It has macro instructions like " " (move the data from address a to address b) and " " (add data from address a to data in address b). It also hides the skip instructions by providing three operand branch macro instructions such as " " (compare a with b and jump to de if they are not equal).

Famil core architectural differences

Baseline core devices
These devices feature a 12-bit wide code memory, a 32-byte register file, and a tiny two level deep call stack. They are represented by the PIC10 series, as well as by some PIC12 and PIC16 devices. Baseline devices are available in 6-pin to 40-pin packages. Generally the first 7 to 9 bytes of the register file are special-purpose registers, and the remaining bytes are general purpose RAM. Pointers are implemented using a register pair: after writing an address to the FSR (file select register), the INDF (indirect f) register becomes an alias for the addressed register. If banked RAM is implemented, the bank number is selected by the high 3 bits of the FSR. This affects register numbers 16 31; registers 0 15 are global and not affected by the bank select bits. Because of the very limited register space (5 bits), 4 rarely-read registers were not assigned addresses, but written by special instructions ( and ).
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The ROM address space is 512 words (12 bits each), which may be extended to 2048 words by banking. and instructions specify the low 9 bits of the new code location; additional high-order bits are taken from the status register. Note that a CALL instruction only includes 8 bits of address, and may only specify addresses in the first half of each 512-word page. Lookup tables are implemented using a computed instructions. (assignment to PCL register) into a table of

The instruction set is as follows. Register numbers are referred to as "f", while constants are referred to as "k". Bit numbers (07) are selected by "b". The "d" bit selects the destination: 0 indicates W, while 1 indicates that the result is written back to source register f. The C and Z status flags may be set based on the result; otherwise they are unmodified. Add and subtract (but not rotate) instructions that set C also set the DC (digit carry) flag, the carry from bit 3 to bit 4, which is useful for BCD arithmetic. 12-bit PIC instruction set 11 10 9 8 7 6 5 4 3 2 1 0 Mnemonic C? Z? 0 0 0 0 0 0 0 opcode

Description

Miscellaneous instructions No operation (MOVW 0,W) Copy W to OPTION register Go into standby mode Restart watchdog timer Copy W to tri-state register ( = 1, 2 or 3) ALU operations: dest MOVWF CLR ,d SUBWF ,d DECF ,d IORWF ,d ANDWF ,d XORWF ,d ADDWF ,d MOVF ,d COMF ,d INCF ,d dest Z dest C Z dest Z dest Z dest Z dest Z dest C Z dest Z dest Z dest Z dest W 0, usually written CLRW or CLRF fW f1 f|W, logical inclusive or f&W, logical and f^W, logical exclusive or f+W f ~f, bitwise complement f+1
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0 0 0 0 0 0 0 0 0 0 0 0 NOP 0 0 0 0 0 0 0 0 0 0 1 0 OPTION 0 0 0 0 0 0 0 0 0 0 1 1 SLEEP 0 0 0 0 0 0 0 0 0 1 0 0 CLRWDT 0 0 0 0 0 0 0 0 0 1 0 0 opcode d egi e TRIS

OP(f,W)

0 0 0 0 0 0 1 0 0 0 0 0 1 d 0 0 0 0 1 0 d 0 0 0 0 1 1 d 0 0 0 1 0 0 d 0 0 0 1 0 1 d 0 0 0 1 1 0 d 0 0 0 1 1 1 d 0 0 1 0 0 0 d 0 0 1 0 0 1 d 0 0 1 0 1 0 d
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0 0 1 0 1 1 d 0 0 1 1 0 0 d 0 0 1 1 0 1 d 0 0 1 1 1 0 d 0 0 1 1 1 1 d 0 1 op bi bi bi bi bi k k k k

f f f f f egi e f f f f

DECFSZ f,d RRF f,d RLF f,d SWAPF f,d INCFSZ f,d C C

dest dest carry dest dest dest

f1, then skip if zero CARRY*128 | f>>1, rotate right through F<<1 | CARRY, rotate left through carry f<<4 | f>>4, swap nibbles f+1, then skip if zero Bit operations

0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 op

BCF f,b BSF f,b BTFSC f,b BTFSS f,b

Clear bit b of f Set bit b of f Skip if bit b of f is clear Skip if bit b of f is set Control transfers

1 0 0 0 1 0 0 1 1 0 1 1 1 op

RETLW k CALL k GOTO k

Set W

k, then return from subroutine

Call subroutine, 8-bit address k Jump to 9-bit address k[10] OP(k,W)

8-bi immedia e k k k k

Operations with W and 8-bit literal: W MOVLW k IORLW k ANDLW k XORLW k W Z W Z W Z W k k|W, bitwise logical or k&W, bitwise and k^W, bitwise exclusive or Description

1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1

11 10 9 8 7 6 5 4 3 2 1 0 Mnemonic C? Z?

Mid-range core devices

These devices feature a 14-bit wide code memory, and an improved 8 level deep call stack. The instruction set differs very little from the baseline devices, but the increased opcode width allows 128 registers and 2048 words of code to be directly addressed. The mid-range core is available in the majority of devices labeled PIC12 and PIC16. The first 32 bytes of the register space are allocated to special-purpose registers; the remaining 96 bytes are used for general-purpose RAM. If banked RAM is used, the high 16 registers (0x700x7F) are global, as are a few of the most important special-purpose registers, including the STATUS register which holds the RAM bank select bits. (The other global registers are FSR and INDF, the low 8 bits of the program counter PCL, the PC high preload register PCLATH, and the master interrupt control register INTCON.)
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The PCLATH register supplies high-order instruction address bits when the 8 bits supplied by a write to the PCL register, or the 11 bits supplied by a or instruction, is not sufficient to address the available ROM space. 14-bit PIC instruction set 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mnemonic C? Z? 0 0 0 0 0 0 0 opcode

Description

Miscellaneous instructions No operation (MOVW 0,W) Return from subroutine, W unmodified Return from interrupt Copy W to OPTION register Go into standby mode Restart watchdog timer Copy W to tri-state register ( = 1, 2 or 3) ALU operations: dest MOVWF CLR ,d SUBWF ,d DECF ,d IORWF ,d ANDWF ,d XORWF ,d ADDWF ,d MOVF ,d COMF ,d INCF ,d DECFSZ ,d RRF ,d C f Z dest C Z dest Z dest Z dest Z dest Z dest C Z dest Z dest Z dest Z dest dest W 0, usually written CLRW or CLRF fW f1 f|W, logical inclusive or f&W, logical and f^W, logical exclusive or f+W f ~f, bitwise complement f+1 f1, then skip if zero OP(f,W)

0 0 0 0 0 0 0 0 0 0 0 0 0 0 NOP 0 0 0 0 0 0 0 0 0 0 1 0 0 0 RETURN 0 0 0 0 0 0 0 0 0 0 1 0 0 1 RETFIE 0 0 0 0 0 0 0 1 1 0 0 0 1 0 OPTION 0 0 0 0 0 0 0 1 1 0 0 0 1 1 SLEEP 0 0 0 0 0 0 0 1 1 0 0 1 0 0 CLRWDT 0 0 0 0 0 0 0 1 1 0 0 1 0 0 opcode d egi e TRIS

0 0 0 0 0 0 1 0 0 0 0 0 1 d 0 0 0 0 1 0 d 0 0 0 0 1 1 d 0 0 0 1 0 0 d 0 0 0 1 0 1 d 0 0 0 1 1 0 d 0 0 0 1 1 1 d 0 0 1 0 0 0 d 0 0 1 0 0 1 d 0 0 1 0 1 0 d 0 0 1 0 1 1 d 0 0 1 1 0 0 d

dest CARRY*128 | f>>1, rotate right through carry dest f<<1 | CARRY, rotate left through
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0 0 1 1 0 1 d 0 0 1 1 1 0 d 0 0 1 1 1 1 d 0 1 op bi bit bit bit bit k k k op

f f f egi e f f f f

RLF f,d SWAPF f,d INCFSZ f,d

carry dest dest f<<4 | f>>4, swap nibbles f+1, then skip if zero Bit operations

0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 op 1 0 0 1 0 1 1 1

BCF f,b BSF f,b BTFSC f,b BTFSS f,b

Clear bit b of f Set bit b of f Skip if bit b of f is clear Skip if bit b of f is set Control transfers

CALL k GOTO k

Call subroutine Jump to address k OP(k,W)

8-bi immedia e k k k k k k k k

Operations with W and 8-bit literal: W MOVLW k RETLW k IORLW k ANDLW k XORLW k (reserved) SUBLW k C Z W kW, subtract k+W, add Description ADDLW k C Z W W W Z W Z W Z W k

1 1 0 0 1 1 0 1 1 1 1 0 0 0 1 1 1 0 0 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1

k, then return from subroutine k|W, bitwise logical or k&W, bitwise and k^W, bitwise exclusive or

13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mnemonic C? Z?

Enhanced Mid-range core devices

Enhanced Mid-range core devices introduce a deeper hardware stack, additional reset methods, 14 additional instructions and C programming language optimizations. In particular. there are two INDF0 and ), and two corresponding register pairs ( and ). Special instructions use registers like address registers, with a variety of addressing modes. 14-bit enhanced PIC additional instructions 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mnemonic C? Z? 0 0 0 0 0 0 0 opcode

Description

Miscellaneous instructions Software reset

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0 0 0 0 0 0 0 0 0 0 0 0 0 1 RESET
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0 0 0 0 0 0 0 0 0 0 1 0 1 0 CALLW 0 0 0 0 0 0 0 0 0 0 1 0 1 1 BRW 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 opcode d k egi e f f f f f k k k k k k ADDFSR FSR ,k MOVLP k BRA k MOVIW k[FSR ] MOVWI k[FSR ] Mnemonic C? Z? LSLF f,d LSRF f,d ASRF f,d SUBWFB f,d ADDWFC f,d 0 0 0 1 1 0 1 1 MOVIW ++FSR MOVIW FSR MOVIW FSR ++ MOVIW FSR MOVWI using FSR MOVLB k

Push PC, then jump to PCLATH:W PC PC + W, relative jump using W INDF INDF

Z Increment FSR , then W Z Decrement FSR , then W Z W Z W INDF

INDF , then increment FSR INDF , then decrement FSR W, same modes as MOVIW

BSR k, move literal to bank select register ALU operations: dest C Z dest C Z dest C Z dest dest C Z carry C Z dest OP(f,W)

1 1 0 1 0 1 d 1 1 0 1 1 0 d 1 1 0 1 1 1 d 1 1 1 0 1 1 d 1 1 1 1 0 1 d 1 1 opcode

f << 1, logical shift left f >> 1, logical shift right f >> 1, arithmetic shift right f W 1 + C, subtract with f + W + C, add with carry

Operations with literal k FSR offset FSR + k, add 6-bit signed k, move 7-bit literal to PC

1 1 0 0 0 1 0 1 1 0 0 0 1 1 1 1 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1

PCLATH latch high

PC PC + k, branch relative using 9bit signed offset Z W [FSR +k], 6-bit signed offset W, 6-bit signed offset Description

[FSR +k]

13 12 11 10 9 8 7 6 5 4 3 2 1 0

PIC17 high end core devices

The 17 series never became popular and has been superseded by the PIC18 architecture. It is not recommended
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for new designs, and availability may be limited. Improvements over earlier cores are 16-bit wide opcodes (allowing many new instructions), and a 16 level deep call stack. PIC17 devices were produced in packages from 40 to 68 pins. The 17 series introduced a number of important new features: a memory mapped accumulator read access to code memory (table reads) direct register to register moves (prior cores needed to move registers through the accumulator) an external program memory interface to expand the code space an 8-bit 8-bit hardware multiplier a second indirect register pair auto-increment/decrement addressing controlled by control bits in a status register (ALUSTA)

PIC18 high end core de ices

Microchip introduced the PIC18 architecture in 2000. [4] (http://mdubuc.freeshell.org/Sdcc/) Unlike the 17 series, it has proven to be very popular, with a large number of device variants presently in manufacture. In contrast to earlier devices, which were more often than not programmed in assembly, C has become the predominant development language [5] (http://www.microchipc.com/sourcecode/) . The 18 series inherits most of the features and instructions of the 17 series, while adding a number of important new features: much deeper call stack (31 levels deep) the call stack may be read and written conditional branch instructions indexed addressing mode (PLUSW) extending the FSR registers to 12 bits, allowing them to linearly address the entire data address space the addition of another FSR register (bringing the number up to 3) The auto increment/decrement feature was improved by removing the control bits and adding four new indirect registers per FSR. Depending on which indirect file register is being accessed it is possible to postdecrement, postincrement, or preincrement FSR; or form the effective address by adding W to FSR. In more advanced PIC18 devices, an "extended mode" is available which makes the addressing even more favorable to compiled code: a new offset addressing mode; some addresses which were relative to the access bank are now interpreted relative to the FSR2 register the addition of several new instructions, notable for manipulating the FSR registers. These changes were primarily aimed at improving the efficiency of a data stack implementation. If FSR2 is used either as the stack pointer or frame pointer, stack items may be easily indexedallowing more efficient re-entrant code. Microchip's MPLAB C18 C compiler chooses to use FSR2 as a frame pointer.

PIC24 and dsPIC 16-bit microcontrollers

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In 2001, Microchip introduced the dsPIC series of chips,[11] which entered mass production in late 2004. They are Microchip's first inherently 16-bit microcontrollers. PIC24 devices are designed as general purpose microcontrollers. dsPIC devices include digital signal processing capabilities in addition. Architecturally, although they share the PIC moniker, they are very different from the 8-bit PICs. The most notable differences are:[12] they feature a set of 16 working registers (W0-W15) they fully support a stack in RAM, and do not have a hardware stack bank switching is not required to access RAM or special function registers data stored in program memory can be accessed directly using a feature called Program Space Visibility interrupt sources may be assigned to distinct handlers using an interrupt vector table Some features are: hardware MAC (multiplyaccumulate) barrel shifting bit reversal (16 16)-bit single-cycle multiplication and other DSP operations hardware divide assist (19 cycles for 16/32-bit divide) hardware support for loop indexing Direct memory access dsPICs can be programmed in C using Microchip's C30 compiler which is a variant of gcc.

PIC32 32-bi mic ocon olle

In November 2007 Microchip introduced the new PIC32MX (http://www.microchip.com/stellent/idcplg? IdcService=SS_GET_PAGE&nodeId=2018&mcparam=en532888) family of 32-bit microcontrollers. The initial device line-up is based on the industry standard MIPS32 M4K Core[6] (http://www.mips.com/products/processors/32-64-bit-cores/mips32-m4k/) . The device can be programmed using the Microchip MPLAB C Compiler for PIC32 MCUs (http://microchip.com/c32) , a variant of the GCC compiler. The first 18 models currently in production (PIC32MX3xx and PIC32MX4xx) are pin to pin compatible and share the same peripherals set with the PIC24FxxGA0xx family of (16-bit) devices allowing the use of common libraries, software and hardware tools. The PIC32 architecture brings a number of new features to Microchip portfolio, including: The highest execution speed 80 MIPS (120+[13] Dhrystone MIPS @ 80 MHz) The largest flash memory: 512 kByte One instruction per clock cycle execution The first cached processor Allows execution from RAM Full Speed Host/Dual Role and OTG USB capabilities Full JTAG and 2 wire programming and debugging Real-time trace

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Device variants and hardware features

PIC devices generally feature: Sleep mode (power savings). Watchdog timer. Various crystal or RC oscillator configurations, or an external clock.

Variants
Within a series, there are still many device variants depending on what hardware resources the chip features. General purpose I/O pins. Internal clock oscillators. 8/16/32 Bit Timers. Internal EEPROM Memory. Synchronous/Asynchronous Serial Interface USART. MSSP Peripheral for I C and SPI Communications. Capture/Compare and PWM modules. Analog-to-digital converters (up to ~1.0 MHz). USB, Ethernet, CAN interfacing support. External memory interface. Integrated analog RF front ends (PIC16F639, and rfPIC). KEELOQ Rolling code encryption peripheral (encode/decode) And many more.

Trends
The first generation of PICs with EPROM storage are almost completely replaced by chips with Flash memory. Likewise, the original 12-bit instruction set of the PIC1650 and its direct descendants has been superseded by 14bit and 16-bit instruction sets. Microchip still sells OTP (one-time-programmable) and windowed (UV-erasable) versions of some of its EPROM based PICs for legacy support or volume orders. The Microchip website lists PICs that are not electrically erasable as OTP despite the fact that UV erasable windowed versions of these chips can be ordered..

Histor
The original PIC was built to be used with General Instrument's new 16-bit CPU, the CP1600. While generally a good CPU, the CP1600 had poor I/O performance, and the 8-bit PIC was developed in 1975 to improve performance of the overall system by offloading I/O tasks from the CPU. The PIC used simple microcode stored in ROM to perform its tasks, and although the term was not used at the time, it shares some common features with RISC designs. In 1985, General Instrument spun off their microelectronics division and the new ownership cancelled almost everything which by this time was mostly out-of-date. The PIC, however, was upgraded with internal EPROM to produce a programmable channel controller and today a huge variety of PICs are available with various onen.wikipedia.org/wiki/PIC_microcontroller 13/17

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b a d e i he a ( e ia c ica i d e , UART , 256 d 64 d a d e (a " d" i e a e b de e di g he ecific PIC ic fa i ). PIC a d PIC ic a e egi e ed ade Pe iphe al In e face Con olle , a h PIC1650 de ice a "P og ammable "P og ammable In elligen Comp e

c e e , e c.) a d a g age i ci , a i gf

ga e 12, 14

f 16 bi

a f Mic chi Tech g . I i ge e a gh Ge e a I e ' igi a ac f [4] The ac In e face Con olle ". a [5] ". .

h gh ha PIC a d f he i i ia PIC1640 a d ic e aced i h

The Mic chi 16C84 (PIC16 84), i d ced i 1993 , a he fi [ci a ion needed] Mic chi CPU i h -chi EEPROM e Thi e ec ica e a ab e e ade i c e ha CPU ha e i ed a a "e a e i d " f e a i g EPROM.

PIC clone
Thi d a a fac e Pa a a SX a ec a ib e d c ,f e a e he
Va i ic c de (EPROM) PIC e

De elopmen ool

Mic chi ide a f ee a e IDE ac age ca ed MPLAB, hich i c de a a e b e , i e , f a e i a , a d deb gge . The a e Cc ie f he PIC18 a d d PIC hich i eg a e c ea ih MPLAB. F ee de e i f he C c ie a e a a aiab e i h a fea e . B f he f ee e i , [14] i iai i be di ab ed af e 60 da . Se e a hi d a ie a e C a g age c ie f PIC , a f hich i eg a e MPLAB a d/ fea e hei IDE. A f fea ed c ie f he PICBASIC a g age g a PIC ic c e i a aiab e f eLab , I c. De e e a e a aiab e f he PIC fa i de he GPL he f ee f ae e ce ice e .

De ice p og amme
De ice ca ed " g a e " a e adi i a ed ge g a c de i he a ge PIC. M PIC ha Mic chi c e e fea e ICSP (I Ci c i Se ia P g a i g) a d/ LVP (L V age P g a i g) ca abii ie , a i g he PIC be g a ed hie i i i i g i he a ge ci c i . ICSP g a i g i e f ed i g i ,c c a d da a, hie a high age (12V) i e e he V /MCLR i . L age g a i g di e e i h he high age, b e e e e c i e e f a I/O i a d ca he ef e be di ab ed ec e he i f he e ( ce di ab ed i ca be e-e ab ed i g high age g a i g). The e a e a ga e e e i e de ig e f PIC ic c hich e ICSP e , a gi g f a di ec d

A de e e b adf c MCU, f Mic chi

i -

he ad f c de f

ah

e,

i e ige
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ga ga i e ige

e ha ca e if he de ice a e e a age . Ma f he e c e ed PIC he e e e d he g a i gc a d he PIC ha i be e f g a e i eeded g a ea ie PIC de ( EPROM i -ci c i g a i g.

ga e ea g a ed. The e) hich d

e-

Ma f he highe e d f a h ba ed PIC ca a e f- g a ( i e hei ga e ). De b a d a e a aiab e i h a a b ade fac g a ed ha ca be ed ad e ga e a i e face ch a RS-232 USB, h b ia i g he eed f a g a e de ice. A e a i e he e i b ade fi a e a aiab e ha he e ca ad he PIC i g ICSP. The ad a age f a b ade e ICSP i he fa ei g a i g eed , i edia e g a e ec i f ig g a i g, a d he abii b h deb g a d ga i g he a e cab e. P g a e /deb gge a e a aiab e di ec f Mic chi . Thi d a g a e a ge f a b id , e f-a e b i a df e ed ead - -g i . S e a e i e de ig hich e i e a PC d he -e e g a i g ig a i g ( he e ica c ec he e ia aae a d c i f a fe i e c e ), hie he ha e he g a i g gic b i i he ( he e ica e a e ia USB c ec i , a e a fa e , a d a e f e b i i g PIC he e e f c ).

Debugging
Soft are emulation
C e cia a d f ee e a e i f he PIC fa i ce .

Mic chi PICSTART P ga e

In-circuit debugging
La e de PIC fea e a ICD (i -ci c i deb ggi g) i e face, b i i he CPU c e. ICD deb gge (MPLAB ICD2 a d he hi d a ) ca c ica e i h hi i e face i g h ee i e . Thi chea a d i e deb ggi g e c e a a ice h e e , a e i i ed b ea i c (1 de ic 3 e e PIC ), f e IO ( i h he e ce i f e face 44- i PIC hich ha e dedica ed i e f deb ggi g) a d f e fea e f he chi . F a PIC , he e he f IO ca ed b hi e h d d be acce ab e, ecia heade a e ade hich a e fi ed i h PIC ha ha e e a i ecifica f deb ggi g.

In-circuit emulators
Mic chi ffe h ee f i ci c i e a : he MPLAB ICE2000 ( a a e i e face, a USB c e e i a aiab e); he e e MPLAB ICE4000 (USB 2.0 c ec i ); a d ece , he REAL ICE. A f he e ICE ca be ed i h he MPLAB IDE f f ce- e e deb ggi g f c de ig he a ge . The ICE2000 e i e e a e a d e, a d ci d e , a d he e ha d a e de ice. ide a c e hich ca a e ei he a

The REAL ICE c ec di ec d c i de ice hich i -ci c i e a i h gh he PGC/PGD g a i g i e face, h gh a high eed c ec i hich e e i . Acc di g Mic chi , i [15] " " f a h-ba ed PIC, PIC24, a d d PIC ce .
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The ICE4000 i ec e ded f

ge di ec e de ig .

ad e i ed

Mic chi '

eb i e, a d he

cha i g age a e ha i i

PICKit 2 open source structure and clones

PICKi 2 ha bee a i e e i g PIC ga e f Mic chi . I ca g a a PIC a d deb g f he PIC (a f Ma -2009, he PIC32 fa i i ed f MPLAB deb ggi g). E e i ce i fi e ea e , a f a e ce c de (fi a e, PC a ica i ) a d ha d a e che a ic a e e he b ic. Thi a e i e a i e ea f a e d e dif he ga e f e iha -Wi d eai g e ch a Li Mac OS. I he ea i e, i a c ea e f DIY i e e a d c e . Thi e ce c e b i g a fea e he PICKi 2 c i ch a P g a e - -G , he UART T a d he L gic T , hich ha e bee c ib ed b PICKi 2 e . U e ha e a added ch fea e he PICKi 2 a 4MB P g a e - -g ca abii , USB b c /b ci c i , RJ12 e c ec a d he .

Part number suffi es

The F i a a e ge e a i dica e he PIC ic e fa h e a d ca be e a ed e ec ica . A C ge e a ea i ca be e a ed b e i g he die a i e igh ( hich i ib e if a i d ed ac age e i ed). A e ce i hi e i he PIC16C84 hich e EEPROM a d i he ef e e ec ica e a ab e. A L i he a e i dica e he a Pa de ig ed ecifica f he a be . The e a a e a i a a e age, f e ihf e e c i i i ed.[16]

age e a i , i hi a ic a ge f 3 - 3.6 V , a e a ed i h a J i i e I/O e a a he i acce 5V a i .[16]

See also
PIC16 84 A e AVR Ad i BASIC A BASIC S a D e g OOPic PICAXE TI MSP430 Ma i i e

References
1. ^ h :// 1. ic chi .c /d ad /e /De iceD c/39630C. df 2. ^ h :// .da a hee a chi e.c /d /Da ab -1/B 241-407. df 3. ^ "PIC ic Fa i T ee", PIC16F Se i a P e e a i h :// . ic chi .c . /PDF/2004_ i g/PIC16F%20 e i a %20 e e a i . df
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4. ^ "MOS DATA 1976", General Instrument 1976 Databook 5. ^ "1977 Data Catalog", Micro Electronics from General Instrument Corporation http://www.rhoent.com/pic16xx.pdf 6. ^ "Microchip Technology Delivers Ten Billionth PIC Microcontroller to Samsung Electronics Co." (http://www.microchip.com/pagehandler/en-us/press-release/microchip-technology-delivers-10-billionth-picmic.html) (Press release). Microchip Technology. 19 September 2011. http://www.microchip.com/pagehandler/en-us/press-release/microchip-technology-delivers-10-billionth-picmic.html. 7. ^ "AN869: External Memory Interfacing Techniques for the PIC18F8XXX" (http://ww1.microchip.com/downloads/en/AppNotes/00869b.pdf) . http://ww1.microchip.com/downloads/en/AppNotes/00869b.pdf. Retrieved 24 August 2009. 8. ^ Microchip Product Selector [1] (http://www.microchip.com/productselector/MCUProductSelector.html) 9. ^ "PIC Paging and PCLATH" (http://massmind.org/techref/microchip/pages.htm) 10. ^ PIC10F200/202/204/206 Da a Shee (http://ww1.microchip.com/downloads/en/DeviceDoc/41239D.pdf) . Microchip Technology. 2007. p. 52. http://ww1.microchip.com/downloads/en/DeviceDoc/41239D.pdf. 11. ^ [2] (http://www.microchip.com/stellent/idcplg? IdcService=SS_GET_PAGE&nodeId=2018&mcparam=en013529) 12. ^ "PIC24H Family Overview" (http://ww1.microchip.com/downloads/en/DeviceDoc/70166A.pdf) . http://ww1.microchip.com/downloads/en/DeviceDoc/70166A.pdf. Retrieved 23 September 2007. 13. ^ "32-bit PIC MCUs" (http://www.microchip.com/en_US/family/pic32/) . http://www.microchip.com/en_US/family/pic32/. Retrieved 13 October 2010. 14. ^ "MPLAB C Compiler for PIC18 MCUs" (http://www.microchip.com/stellent/idcplg? IdcService=SS_GET_PAGE&nodeId=1406&dDocName=en010014) . http://www.microchip.com/stellent/idcplg? IdcService=SS_GET_PAGE&nodeId=1406&dDocName=en010014. 15. ^ "MPLAB REAL ICE In-Circuit Emulator Product Overview" (http://ww1.microchip.com/downloads/en/DeviceDoc/51630a.pdf) . http://ww1.microchip.com/downloads/en/DeviceDoc/51630a.pdf. Retrieved 23 September 2007. 16. ^ "3V Design Center" (http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=2530) . http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=2530. Retrieved 2 August 2011.

E ternal links
PIC microcontroller (http://www.dmoz.org/Computers/Hardware/Components/Processors/PIC//) at the Open Directory Project. Official Microchip website (http://www.microchip.com/stellent/idcplg? IdcService=SS_GET_PAGE&nodeId=64) Retrieved from "http://en.wikipedia.org/w/index.php?title=PIC_microcontroller&oldid=474270748" Categories: Microcontrollers Instruction set architectures This page was last modified on 31 January 2012 at 20:19. Text is available under the Creative Commons Attribution-ShareAlike License; additional terms may apply. See Terms of use for details. Wikipedia is a registered trademark of the Wikimedia Foundation, Inc., a non-profit organization.

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