1.

INTRODUCTION TO PSPICE

Electronic circuit design requires accurate methods for evaluating circuit performance. Because of the enormous complexity of modern integrated circuits, computer aided circuit analysis is essential and can provide information about circuit performance that is almost impossible to obtain with laboratory prototype measurements. Computer aided analysis permits.

1. Evaluating the effects of variations in elements, such as resistors, transistors, transformers, and so on. 2. The assessment of performance improvements or degradations. 3. Evaluating the effects of noise and signal distortion without the need of expensive measuring instruments. 4. Sensitivity analysis to determine the permissible bonds due to tolerances on each and every element value of parameter of active elements. 5. Fourier analysis without expensive wave analyzers 6. Evaluating the effects of nonlinear elements on the circuit performance 7. Optimizing the design of electronic circuits in terms of circuit parameters.

SPICE is a general purpose circuit program that simulates electronic circuits. SPICE can perform various analyses of electronic circuits: the operating (or the quiescent) points of transistors, a time-domain response, a small-signal frequency response, and so on. SPICE contains models for common circuit elements, active as well as passive, and is capable of simulating most electronic circuits. It is a versatile program and is widely used both in industries and universities. The acronym SPICE stands for Simulation Program with Integrated Circuit Emphasis.

Unit recently, SPICE was available only on mainframe computers. In addition to the initial cost of the computer system, such a machine can be expensive and inconvenient for classroom use. In 1984, MicroSim introduced the PSpice simulator, which is similar to the Berkeley SPICE and runs on an IBM-PC or compatible. It is available at no cost to students for classroom use. PSpice, therefore, widens the scope for the integration of computer-aided circuit analysis into electronic circuits courses at the undergraduate level. Other versions of PSpice that will run on computers such as the Macintosh II, VAX, SUN, and NEC are also available.

DESCRIPTION OF SPICE:

The development of SPICE spans a period of about 30 years. During the mid1960s, the program ECAP was developed at IBM [1]. Later ECAP served as the starting point for the development of program CANCER at the University of California (UC), Berkeley in early 1970s. SPICE2, which is an improved version of SPICE, was developed during the mid1970s at UC Berkeley.

The algorithms of SPICE2 are general in nature but are robust and powerful for simulating electrical and electronics circuits, and SPICE2 has become a standard tool in the industry for circuit simulations. The development of SPICE2 was supported by public funds at UC-Berkeley, and the program is in the public domain. SPICE3, which is a variation of SPICE2, is designed especially to support the computer aided design (CAD) research program at UC Berkeley.

SPICE2 has become an industry standard and is now referred to simply as SPICE. The input syntax for SPICE is a free-format style; it does not require that data be entered in fixed column locations. SPICE assumes reasonable default values fro unspecified circuit parameters. In addition, it performs a considerable amount of error checking to ensure that a circuit has been entered correctly.

PSpice, which uses the same algorithms as SPICE2 and is a member of the SPICE family, is equally useful for simulating all types of circuits in a wide range of applications. A circuit is described by statements that are stored in a file called the circuit file. The circuit file is read by the SPICE simulator. Each statement is self-contained and independent; the statements do not interact with each other. SPICE (or PSpice) statements are easy to learn and use.

TYPES OF SPICE:

The commercially supported versions of SPICE2 can be divided into two types: mainframe versions and PC-based versions. Their methods of computation may differ, but their features are almost identical to those of SPICE2. However, some may include such additions as a pre-processor or shell program to manage input and provide interactive control, as well as a postprocessor for refining the normal SPICE output. A person who is familiar with one SPICE version (e.g., PSpice) should be able to work with other versions.

The mainframe versions are

HSPICE (Meta-Software), which is designed for integrated circuit design with special device models RAD-SPICE (Meta-Software), which simulates circuits subjected to ionizing radiation. IG-SPICE (A.B. Associates) I-SPICE (NCSS Time Sharing). IG-SPICE and I-SPICE are designed for interactive circuit simulation with graphic output. Precise (Electronic Engineering Software) PSpice (Mentor Graphics) Cadence SPICE (Cadence Design) SPICE Plus (Valid Logic)

The PC-versions are All Spice (Acotech) IS-SPICE (Intusoft) Z-SPICE(Z-Tech) SPICE-Plus (Analog Design Tools) DSPICE (Daisy Systems) PSpice (MicroSim)

TYPES OF ANALYSIS :

PSpice allows various types of analysis. Each analysis is invoked by including its command statement. For example, a statement beginning with the .DC command invokes the DC sweep. The types of analysis and their corresponding .(dot) commands are described below.

Dc Analysis is used for circuits with time-invariant sources (e.g., steady state dc sources). It calculates all node voltages and branch currents over a range of values, and their quiescent (dc) values are the outputs.

Dc sweep of and input voltage/current source, a model parameter, or temperature over a range of values (.DC) Determination of the linearized model parameters of nonlinear devices (.OP) Dc operating point to obtain all node voltages (.OP) Small signal transfer function with small signal gain, input resistance, and output resistance (Thevenins equivalent) (.TF) Dc small signal sensitivities (.SENS)

Transient Analysis is used for circuits with time-variant sources (e.g., ac sources and switched dc sources). It calculates all node voltages and branch currents over a time interval, and their instantaneous values are the outputs.

Circuit behavior in response to time varying sources (.TRAN) Dc and Fourier components of the transient analysis results (.FOUR)

Ac Analysis is used for small-signal analysis of circuits with sources of variable frequencies. It calculates all node voltages and branch currents over a range of frequencies, and their magnitudes and phase angle are the outputs.

Circuit response over a range of source frequencies (.AC) Noise generation at an output node for every frequency (.NOISE)

LIMITATIONS OF PSpice :

As a circuit simulator, PSpice has the following limitations:

1. The student version of PSpice is restricted to circuits with 10 transistors only. However, the professional DOS (or production) version can simulate a circuit with up to 200 bipolar transistors (or 150 MOSFETs). 2. The program is not interactive; that is, the circuit cannot be analyzed for various component values without editing the program statements.

3. PSpice does not support an interactive method of solution. If the elements of a circuits are specified, the output can be predicted. On the other hand, if the output is specified, PSpice cannot be used to synthesize the circuit elements. 4. The input impedance cannot be determined directly without running the graphic post processor, probe. The student version does not require a floating-point co-processor for running Probe, but the professional version does require such a co-processor. 5. The PC version needs 512 kilobytes of memory (RAM) to run. 6. Distortion analysis is not available in PSpice . SPICE2 allows distortion analysis, but it gives wrong answers. 7. The output impedance of a circuit cannot be printed or plotted directly.
8. The student version will run with or without the floating point co-processor (8087,

80287, or 80387). If the co processor is present, the program will run at full speed; otherwise it will run 5 to 15 times slower. The professional version requires a coprocessor; it is not optional.

Note: The component values in circuits may change depending on specifications.So the experimental procedure should be given more weightage.

2. COMMON EMITTER AMPLIFIER

AIM : i)To analyse the performance of given CE amplifier circuit with respect to gain,band width, i/p resistance & o/p resistance. ii) To design and simulate common emitter amplifier as per given specifications.

CIRCUIT DIAGRAM :

THEORY: The CE amplifier provides high gain and wide frequency response. The emitter lead is common to both the input and output circuits are grounded. The emitter base junction is at forward biased .The collector current is controlled by the base current rather than the emitter current. The input signal is applied to the base terminal of the transistor and amplified output taken across collector terminal. A very small change in base current produces a much larger change in collector current. When the positive is fed to input circuit it opposes forward bias of the circuit which cause the collector current to decrease, it decreases the more negative. Thus when input cycle varies through a negative half cycle, increases the forward bias of the circuit, which causes the collector current increases .Thus the output signal in CE is out of phase with the input signal.

PROCEDURE

1. Select different components and place them in the grid. 2. For calculating the voltage gain the input voltage of 25mv (p-p) amplitude and 1KHz frequency is applied, then the circuit is simulated and output voltage is noted. 3. The voltage gain is calculated by using the expression Av = Vo/Vi 4. For plotting frequency response, the input voltage is kept constant at 25mv(p-p) and frequency is varied. 5. Note down the output voltage for each frequency. 6. All readings are tabulated and Av in db is calculated using the formula 20 Log Vo/Vi. 7. A graph is drawn by taking frequency on X-axis and gain in dB on Y-axis on a Semilog graph sheet.

THEORITICAL CALCULATIONS :

R2 VB = -------------- *VCC = R1 + R2

2400 ---------- * 12 = 2v 14400

VE = VB - V BE

= 2 - 0.7 = 1.3 v

VE

1.3

IE = ------- = ------ = 3.3mA RE 390

V C = VCC - IC* RC = 12 - 0.0033 * 1500 = 7.05 v To calculate Av, Zin(base) and Z in :

25mV re = --------IE

25 = ------- = 7.575 3.3

RC * RL rL = ------------- = RC + RL

1500*1000 ------------------ = 600 1500+1000

rL

600

Av = ------- = --------- = 79.20 re 7.575

Zin(base)

= re = 40* 7.575 = 303

Z in = Z in(base)|| R1||R2|| = 303||12000||2400 = 263

Z in Vb

263

= -------------- * 25mV = ---------------- = 7.61mv R G + Z in 600 + 263

Vout =

Av * Vb

= 79.20* 7.61mv = 0.603v

PRACTICAL CALCULATIONS :

V in = 17mv

Vout = 1.1v

Vout Av = ---------------- = Vin OBSERVATIONS :

1.1 -------= 64.7

17mv

Frequency(Hz)

Voltage Gain

BAND WITH: f2 - f1 =

HZ

RESULT :

3.COMMON SOURCE AMPLIFIER

AIM : i)To analyse the performance of given CS amplifier circuit with respect to gain,band width, i/p resistance & o/p resistance. ii) To design and simulate common emitter amplifier as per given specifications.

CIRCUIT DIAGRAM:

THEORY: A weak signal is applied between gate and source and output is obtained at drain. For the proper operation of FET, gate must be reverse biased. A small change in reverse bias on the gate produces a large drain current. This fact makes FET capable of raising the strength of a weak signal. The gain of the common source FET amplifier is very high which is greater than unity.

PROCEDURE: 1. 2. Select different components and place them in the grid. For calculating the voltage gain the input voltage of 0.2V(p-p) amplitude and 1KHz frequency is applied, then the circuit is simulated and output voltage is noted. 3. 4. The voltage gain is calculated by using the expression Av = Vo / Vi For plotting frequency response the input voltage is kept constant at 0.2V(p-p) and frequency is varied. 5. 6. 7. Note down the output voltage for each frequency. All readings are tabulated and Av in dB is calculated using 20 Log Vo / Vi. A graph is drawn by taking frequency on X-axis and gain in dB on Y-axis on a Semilog graph sheet.

THEORITICAL CALCULATIONS :

RD*RL rL = ---------

1500*10000

= ------------------- =1300 1500 +10000

RD + RL

IDSS = 10mA , VGS = 4v 2 IDSS gmo = ------------- = -VGS(off) 2*10mA ----------------- = 5mS 4v

VGS gm = gmo ----(VGS off) -4 1 - -----------= 5mS 1 -

-1

= 5mS*0.75 =3.75mS

Av = gm * rL

= 3.75mS * 1300 = 4.875

Vin = 0.2 Vpp

Vout = Av * vin = 4.875 * 0.2 Vpp = 0.935 Vpp

PRACTICAL CALCULATIONS : Vin = 0.2 Vpp

Vout = Vout Av = ---------------- = Vin OBSERVATIONS : Frequency(Hz) Voltage Gain

BAND WITH: f2 - f1 =

Hz

RESULT :

4. RC COUPLED AMPLIFIER

AIM : i)To analyse the performance of a RC coupled CE amplifier circuit with respect to gain,band width,& distortion

CIRCUIT DIAGRAM :

THEORY:

RC is the most widely used coupling as it provides excellent audio fidelity. A coupling capacitor is used to connect output of first stage to the input of the second stage. Resistances R1, R2, R5, R3, R4 and R10 form biasing and stabilisation network. Emitter bypass capacitors C5 and

C6 offer low reactance paths to the signals. The coupling capacitor C3 transmits ac signal and blocks dc signal. Cascaded stages amplifies signal and overall gain is improved. The total gain is less than the product of gains of individual stages. Thus overall gain of two stages is A = A1 x A2, where A1 = Voltage gain of first stage and A2 = Voltage gain of second stage

When ac signal is applied to the base of the transistor Q1, its amplified output appears across the collector resistor R9. It is given to the second stage for further amplification and signal appears with more strength. Frequency response curve is obtained by plotting a graph between frequency and gain in dB. The gain is constant in midband frequency range and gain decreases in low and high frequency ranges. The gain decreases in the low frequency range due to coupling capacitor C3 and at high frequencies due to junction capacitance Cbe .

PROCEDURE:

1. Select different components and place them in the grid.

2. Apply input by using function generator to the circuit and simulate the circuit.

3. Observe the output waveform on CRO. 4. Measure the voltage at (i) (ii) Output of the first stage Output of the second stage

5. From the readings, calculate voltage gain of first stage, second stage and overall gain. Disconnect voltage gain. 6. Compare it with the voltage gain obtained when second stage was connected. second stage and then measure output voltage of first stage and calculate

7. For plotting the frequency response, the input voltage is kept constant at 2mv (p-p) and the frequency is varied from 100Hz to 1MHz. 8. Note down the value of output voltage for each frequency. 9. All the readings are tabulated and voltage gain in dB is calculated by using the expression Av =20 Log
10

(Vo/Vi)

10. A graph is drawn by taking frequency on X-axis and gain in dB on Y-axis on a Semilog graph sheet. 11. The bandwidth of the amplifier is calculated from the graph using the expression Bandwidth = f2 f1. Where f1 = Lower cutoff frequency of CE amplifier. f2 = Upper cutoff frequency of CE amplifier THEORITICAL CALCULATIONS : DC Analysis : Calculation of RC& RE :

Given Ic = 1mA, Vce= 5v , VE =2v for the operating point to be approximately for the centre point with this data. Ic IB = ------ = 1mA --------40 = 0.025mA

IE = IB + Ic = 0.025mA + 1mA = 1.025mA

VE Choose VE =2v then

2V

RE = ------ = --------- = 1.95 k IE 1.025mA

Then Vc =VCC (VE + Vce ) = 9 ( 2 + 5 ) = 2V Vc 2v

RC = ------ = -------- = 2k Ic 1mA

It is recommended that RE must be less than RC selected RE = 1k and RC = 2k Calculation of R3 & R4 : The Thevenins equivalent voltage base R4 VB = --------- VCC and is equal to sum of VBE & VE. R3 + R4

BE + VE = 0.7 + 2 = 2.7v V

R4 --------- =

VB -----=

2.7 -------- = 0.3

R3 + R4 R3 = 2.33* R4

VCC

Choose the current flowing through R4 is I4

IC I4 = ------ = 10

1mA -------- = 100 A 10

VBE R4 = -------- = I4

2.7 -------- = 27k 100 A

R4 = 2.33k, R3 = 27k

Select R3 = 2.2k , R4 = 27k

AC Analysis: The voltage gain of an amplifier can be taken as RL Av = -------- = 10 Re 20mv Where Re = ------- = IE RL Av = -------- = 10 => RL = 250 Re RL = RC//RL = 2.2k// RL => RL = 282 20mv ---------- = 25 1.04mA

There is resistance offered between collector and emitter choose RL = 300 select Ce = 100f, Cc = 1 f, Rs =2k

for ac analysis

PRACTICAL CALCULATIONS:

Vi1 = 1.5mv Vo1 =

Vo1 Av1 = -------- = Vi1 Vi2 = Vo1 Vo2 = Vo2 Av2 = --------- = Vi2

Av =Av1*Av2 =

Vo2 Av = ----------=

Vi1

OBSERVATIONS:

Frequency (Hz)

Voltage Gain

BAND WITH: f2 - f1 = Hz

RESULT:

5. WIEN BRIDGE OSCILLATOR

AIM : To construct and simulate the Wien Bridge oscillator and then to verify the frequency of oscillation theoretically and by simulation.

CIRCUIT DIAGRAM :

THEORY:

The Wien Bridge oscillator consists of two RC coupled Amplifiers which provide a phase of 360 or 0. A balanced bridge is used as the feedback network which has no need to provide additional phase shift to satisfy the Barkhausen criteria for sustain the oscillations. The loop gain of the circuit is greater than equal to one, this condition generates the sinusoidal oscillations. The

feed back network consists of Lead Lag network and a Voltage divider. The Lead Lag network provides the positive feedback to the input of the first stage and the voltage divider provides a negative feed back to the emitter of the first stage.The frequency of oscillations is 1 f = ---------2RC PROCEDURE:

1. Select different components and place them in the grid and simulate the

circuit. 2. Observe the output signal and note down the output amplitude and time period (T). 3. Calculate the practical frequency of oscillation (f=1/T) and compare with the theoretical value. OBSERVATIONS : Theoritical calculation : 1 1 = 16 kHz

f = ---------- = ------------2Rc Practical calculation : 1 6.283*10-5

f = ------- = T

RESULT : 6. RC PHASE SHIFT OSCILLATOR

AIM:

To construct and simulate the RC phase shift oscillator and to verify the frequency of oscillation theoretically and by simulation..

CIRCUIT DIAGRAM:

THEORY:

RC-Phase shift Oscillator has a CE amplifier followed by three sections of RC phase shift feed back networks. The out put of the last stage is return to the input of the amplifier. The values of R and C are chosen such that the phase shift of each RC section is 60. Thus The RC ladder network produces a total phase shift of 180 between its input and output voltage for the given frequencies. Since CE Amplifier produces 180 phases shift the total phase shift from the base of the transistor around the circuit and back to the base will be exactly 360 or 0. This satisfies the Barkhausen condition for sustaining oscillations and total loop gain of this circuit is greater than or equal to 1, this condition used to generate the sinusoidal oscillations.

The is,

frequency

of

oscillations

of

RC-Phase

Shift

Oscillator

1 f= ----------2RC* 6

PROCEDURE:

1. Select different components and place them in the grid and simulate the circuit.

2. Observe the output signal and note down the output amplitude and time period (Td).
3. Calculate the frequency of oscillations theoretically and verify it practically (f=1/Td).

4. Calculate the phase shift at each RC section by measuring the time shifts (Tp) between the final waveform and the waveform at that section by using the below formula.

OBSERVATIONS : THEORITICAL CALCULATIONS : R = 10000, C = 0.001 f 1 f= ----------------- = 2RC* 6 1 ------------- = 6.497 kHZ 6.283*10-5

PRACTICAL CALCULATIONS: Td = 1 f= ----------------- = Td tp

(1). 1= --------*3600 = Td tp (2). 2 = --------- = * 3600 = Td tp (3). 3= ----------- = *3600 = Td

RESULT :

7. CLASS A POWER AMPLIFIER

AIM: To calculate the efficiency of class A power amplifier by simulation

CIRCUIT DIAGRAM:

THEORY: The function of power amplifier is to raise the power level of input signal. Class A power amplifier is one in which the output current flows during the entire cycle of input signal. Thus the operating point is selected in such away that the transistor operates only over the linear region of its load line. So this amplifier can amplify input signal of small amplitude. As the transistor operates over the linear portion of load line the output wave form is exactly similar to the input wave form. Hence this amplifier is used where freedom from distortion is the prime aim.

PROCEDURE: 1. Select different components and place them in the grid.

2. Apply the input ac signal voltage of 160mV (p-p) and simulate the circuit. 3. Observe the output wave form on CRO and measure the output voltage V0.

4. Now connect the ammeter at collector terminal of transistor. 5. Disconnect the ac signal from input and measure the collector current Ic in ammeter. 6. calculate the efficiency by using practical calculations compare it with theoretically calculated efficiency

OBSERVATION : THEORITICAL CALCULATIONS : VCC/R L ICQ = -----------2

IC ICQ = -----2

VCC *VCC

(VCC) 2

Pin(dc) = -------------- = 2 RL

-----------2 RL

( Vmax Vmin)*(Imax Imin) Po(a.c) = ----------------------------------------8 VCC (Imax Imin) = --------RL (Vmax Vmin) = VCC VCC*VCC Po(a.c) = ------------------- = 8RL ( VCC ) ----------8RL
2

Po(a.c)

( VCC ) 2 /8RL

% of efficiency = --------- *100 = ------------------- *100 = 25% Pin(d.c) ( VCC ) 2 /2RL

PRACTICAL CALCULATIONS :

IC =

Pin(d.c) = VCC*ICQ =

Vo2 Po(a.c) = -------- = 8RL

Po(a.c) % of efficiency = ------------- *100 = Pin(d.c)

RESULT: The efficiency of class A Power amplifier is _______

8. CLASS B COMPLEMENTARY SYMMETRY PUSH PULL AMPLIFIER

AIM: i)To simulate and verify the efficiency of class B complementary symmetry push pull amplifier. II) To study the phenomenon of cross over distortion in a Class B amplifier

CIRCUIT DIAGRAM:

THEORY:

Complementary means the circuit uses two identical transistors but one is NPN and other is PNP. The symmetry means the biasing resistors connected in both transistors are equal. As a result of this, emitter base junction of each transistor is biased with the same voltage.

During the positive half cycle of ac input the base emitter voltage of both transistors becomes positive. Under this condition only NPN transistor conducts, while PNP transistor is cutoff. During this process positive half cycle current flows through load resistor R5.

During negative half cycle of ac input only PNP transistor conducts and NPN transistor is cutoff and the negative half cycle current flows through R 5. We get a complete amplified wave form of input signal. This amplifier circuit has a unity gain because of the emitter follower configuration is used

PROCEDURE:

1. Select different components and place them in the grid.

2. Apply the input ac signal voltage of 0.8V (p-p) and simulate the circuit.

3. Observe the output wave form on CRO and measure the output voltage Vo. 4. Now connect the ammeters at collector terminals of NPN and PNP transistors. 5. Disconnect the ac signal from input and measure the collector currents Ic1 and Ic2 in ammeters. 6. Calculate the efficiency by using practical calculations 7. Compare it with theoretically calculated efficiency

OBSERVATIONS : THEORITICAL CALCULATIONS : VCC/RL ICQ = -------------2 Pin(d.c) = VCC*ICQ

VCC*VCC Pin(d.c) =

(VCC) 2

------------- = -----------2RL 2 RL

( Vmax Vmin)*(Imax Imin)

Po(a.c)

----------------------------------------8 VCC

(Imax Imin) = -----RL

( Vmax Vmin) = VCC

VCC*VCC
2

(VCC ) Po(a.c) =

------------------- = ----------8RL 8RL

Po(a.c)

( VCC ) 2 /8RL

% of efficiency = ----------- *100 = ------------------- *100 Pin(d.c) ( VCC ) 2 /2RL

= -----------*100 = 78.5% 4

PRACTICAL CALCULATIONS :

IC1 = IC2 = IC1+IC2 IC = -------------- = 2 IC ICQ = ---------- = 2 VCC = Vo(p-p) = Vo(p-p)2 Po(a.c) = -----------8RL Pin(d.c) = VCC*ICQ Po(a.c) % of efficiency = ----------- *100 Pin(d.c)

RESULT:

ELECTRONIC CIRCUITS LAB

(HARDWARE)

Testing in the Hardware Laboratory (Six Experiments: 3+3) :

1. 2. 3.

Common Emitter and Common Source amplifier. Two Stage RC Coupled Amplifiers. RC Phase Shift Oscillator using Transistors. 4. Single Tuned Voltage Amplifier. 5. Series Voltage Regulator. 6. Shunt Voltage Regulator.

COMMON EMITTER AMPLIFIER

AIM : To test the performance of CE amplifier which was already simulated.

APPARATUS:

(component values may change as per design specifications)

1. 2. 3. 4. 5. 6. 7.

Transistor(BC-107)-1 Capacitors- 1F-2, 47F-1 Resistors -600, 12K, 2.4K, 1.5K, 390, 1K Function generator Regulated Power Supply Cathode Ray Oscilloscope Bread board

CIRCUIT DIAGRAM :

THEORY:

The CE amplifier provides high gain and wide frequency response. The emitter lead is common to both the input and output circuits are grounded. The emitter base junction is at forward biased .The collector current is controlled by the base current rather than the emitter current. The input signal is applied to the base terminal of the transistor and amplified output taken across collector terminal. A very small change in base current produces a much larger change in collector current. When the positive is fed to input circuit it opposes forward bias of the circuit which cause the collector current to decrease, it decreases the more negative. Thus when input cycle varies through a negative half cycle, increases the forward bias of the circuit, which causes the collector current increases .Thus the output signal in CE is out of phase with the input signal.

PROCEDURE

1. Connections are made as per the circuit diagram 2. For calculating the voltage gain the input voltage of 25mv(p-p) amplitude and 1KHz frequency is applied and output voltage is noted. 3. The voltage gain is calculated by using the expression Av = Vo/Vi 4. For plotting frequency response, the input voltage is kept constant at 25mv(p-p) and frequency is varied. 5. Note down the output voltage for each frequency. 6. All readings are tabulated and Av in db is calculated using the formula 20 Log Vo/Vi. 7. A graph is drawn by taking frequency on X-axis and gain in dB on Y-axis on a Semilog graph sheet.

THEORITICAL CALCULATIONS :

R2 VB = -------------- * VCC = R1 + R2

2400 ---------- * 12 = 2V 14400

VE = VB -- V BE

= 2 - .7 = 1.3 V

VE IE = ------- = RE

1.3 ------ = 3.3mA 390

V C = VCC -- IC* RC = 12 - .0033 * 1500 = 7.05 V

To calculate Av, Zin(base) and Z in :

25mV re = --------IE

25 = ------- = 7.575 3.3

RC * RL

1500*1000

rL = ------------RC + RL

------------------ = 600 1500+1000

rL

600

Av = ------- = --------- = 79.20 re 7.575

Zin(base)

= re = 40* 7.575 = 303

Z in = Z in(base)|| R1||R2|| = 303||12000||2400 = 263

Z in Vb

263

= -------------- * 25mV = ---------------- = 7.61mV R G + Z in 600 + 263

Vout =

Av * Vb

= 79.20* 7.61mV = 0.603V

PRACTICAL CALCULATIONS :

V in

= 17mv

Vout

Vout Av = ---------------- = Vin

OBSERVATIONS :

Frequency(Hz)

Voltage Gain

BAND WITH: f2 - f1 = HZ

RESULT :

VIVA QUESTIONS :

1. 2. 3. 4. 5. 6.

What is the phase difference between input and output waveforms of CE amplifier? What type of biasing is used in the given circuit? If the given transistor is replaced by P-N-P ,Can we get the output or not? What is the effect of emitter bypass capacitor on frequency response? What is the effect of coupling capacitor? What is the region of transistor so that it operates as an amplifier?

7. Draw the h-parameter model of CE amplifier. 8. How does transistor acts as an amplifier. 2.COMMON SOURCE AMPLIFIER

AIM : To test the performance of CE amplifier which was already simulated.

APPARATUS; (component values may change as per design specifications).

1. 2. 3. 4. 5. 6. 7.

FET( BFW11)-1 Resistors 1M, 1.5K, 220, 10K Capacitors - 0.01F - 1, 100F - 2 Cathode Ray Oscilloscope Function generator Regulated Power Supply Bread board

CIRCUIT DIAGRAM:

THEORY: A weak signal is applied between gate and source and output is obtained at drain. For the proper operation of FET, gate must be reverse biased. A small change in reverse bias on the gate produces a large drain current. This fact makes FET capable of raising the strength of a weak signal. The gain of the common source FET amplifier is very high which is greater than unity.

PROCEDURE:

1. 2. 3. 4. 5. 6. 7.

Connections are made as per the circuit diagram For calculating the voltage gain the input voltage of 0.2V(p-p) amplitude and 1KHz frequency is applied and output voltage is noted. The voltage gain is calculated by using the expression Av = Vo / Vi For plotting frequency response the input voltage is kept constant at 0.2V(p-p) and frequency is varied. Note down the output voltage for each frequency. All readings are tabulated and Av in dB is calculated using 20 Log Vo / Vi. A graph is drawn by taking frequency on X-axis and gain in dB on Y-axis on a Semilog graph sheet.

THEORITICAL CALCULATIONS :

RD*RL rL = --------RD + RL =

1500*10000 ------------------- =1300 1500 +10000

IDSS = 10mA , VGS = 4V

2 IDSS gmo = ------------=

2*10mA ----------------- = 5mS

-VGS(off)

4V

VGS gm = gmo 1 - -----------(VGS off) = 5mS 1 -

-1 -----4

= 5mS * 0.75 = 3.75mS

Av = gm * rL

= 3.75mS * 1300 = 4.875

Vin = 0.2 Vpp

Vout = Av * vin = 4.875 * 0.2 Vpp

= 0.935 Vpp

PRACTICAL CALCULATIONS :

Vin = 0.2 Vpp

Vout =

Vout Av = ---------------- = Vin

OBSERVATIONS :

Frequency(Hz)

Voltage Gain

BAND WITH: f2 - f1 =Hz

RESULT :

3. RC COUPLED AMPLIFIER

AIM : To construct RC coupled amplifier and analyse its performance with respect to the voltage gain , bandwidth and distortion in output

APPARATUS:

1. 2. 3. 4. 5. 6.

Transistors(BC-107)-2 Resistors -2K -1, 68K - 2, 27K - 2, 2.2K -2, 1.8K - 2, 330 -2 Capacitors-1F -2,10F -1,100F -2 Regulated Power Supply (0-30V) Cathode Ray Oscilloscope Bread board

CIRCUIT DIAGRAM :

THEORY:

RC is the most widely used coupling as it provides excellent audio fidelity. A coupling capacitor is used to connect output of first stage to the input of the second stage. Resistances R1, R2, R5, R3, R4 and R10 form biasing and stabilisation network. Emitter bypass capacitors C5 and C6 offer low reactance paths to the signals. The coupling capacitor C3 transmits ac signal and blocks dc signal. Cascaded stages amplifies signal and overall gain is improved. The total gain is less than the product of gains of individual stages. Thus overall gain of two stages is A = A1 x A2, where A1 = Voltage gain of first stage and A2 = Voltage gain of second stage

When ac signal is applied to the base of the transistor Q1, its amplified output appears across the collector resistor R9. It is given to the second stage for further amplification and signal appears with more strength. Frequency response curve is obtained by plotting a graph between frequency and gain in dB. The gain is constant in midband frequency range and gain decreases in low and high frequency ranges. The gain decreases in the low frequency range due to coupling capacitor C3 and at high frequencies due to junction capacitance Cbe .

PROCEDURE:

1. 2. 3. 4.

Connections are made as per the circuit diagram. Apply input by using function generator to the circuit. Observe the output waveform on CRO. Measure the voltage at (i) Output of the first stage (ii) Output of the second stage

5. From the readings, calculate voltage gain of first stage, second stage and overall gain. Disconnect second stage and then measure output voltage of first stage and calculate voltage gain. 6. Compare it with the voltage gain obtained when second stage was connected. 7. For plotting the frequency response, the input voltage is kept constant at 2mv (pfrequency is varied from 100Hz to 1MHz. 8. Note down the value of output voltage for each frequency. 9. All the readings are tabulated and voltage gain in dB is calculated by using the Av =20 Log
10

p) and the

expression

(Vo/Vi) Semilog

10. A graph is drawn by taking frequency on X-axis and gain in dB on Y-axis on a graph sheet. 11. The bandwidth of the amplifier is calculated from the graph using the Bandwidth = f2 f1. Where f1 = Lower cutoff frequency of CE amplifier. f2 = Upper cutoff frequency of CE amplifier expression

THEORITICAL CALCULATIONS :

DC Analysis : Calculation of RC& RE :

Given Ic = 1mA, Vce= 5V , VE =2V for the operating point to be approximately at the centre point with this data. Ic IB = ------ = 1mA --------40 = 0.025mA

IE = IB + Ic = 0.025mA + 1mA = 1.025mA

VE Choose VE =2V then RE = ------ = IE

2V --------- = 1.95 k 1.025mA

Then Vc =VCC (VE + Vce ) = 9 ( 2 + 5 ) = 2V Vc RC = ------ = Ic 2v -------- = 2k 1mA

It is recommended that RE must be less than RC is selected RE = 1k and RC = 2k

Calculation of R3 & R4 :

The Thevinins equivalent voltage at base

R4 VB = --------- VCC and is equal to sum of VBE & VE. R3 + R4

BE + VE = 0.7 + 2 = 2.7V

R4 --------- = R3 + R4

VB -----VCC =

2.7 -------- = 0.3 9

R3 = 2.33* R4 Choose the current flowing through R4 as I4

IC I4 = ------ = 10

1mA -------- = 100 A 10

VBE R4 = -------- = I4

2.7 -------- = 27k 100 A

R4 = 2.33k, R3 = 27k

Select R3 = 2.2k , R4 = 27k AC Analysis: The voltage gain of an amplifier can be taken as

RL Av = -------- = 10 Re 20mv Where Re = ------- = IE 20mv ---------- = 25 1.04mA

RL Av = -------- = 10 => RL = 250 Re RL = RC//RL = 2.2k// RL => RL = 282

There is resistance offered between collector and emitter choose RL = 300 . For ac analysis select Ce = 100f ,Cc = 1 f, Rs =2k

PRACTICAL CALCULATIONS:

Vi1 = 1.5mV Vo1 =

Vo1 Av1 = -------- = Vi1 Vi2 = Vo1 Vo2 = Av2 =

Av = Av1*Av2 = Vo2 Av = ----------Vi1 =

OBSERVATIONS:

Frequency(Hz)

Output voltage(Vo)

Voltage gain in dB Av =20 log

10

(Vo/Vi)

BAND WITH: f2 - f1 = Hz

RESULT:

VIVA QUESTIONS:

7. 8. 9.

What is the necessity of cascading? Define 3-dB bandwidth. Why RC-coupling is preferred in audio range.

10. Explain various types of capacitors. 11. What is loading effect? 12. What is meant by RC coupling?

4. RC PHASE SHIFT OSCILLATOR

AIM:To construct the RC phase shift oscillator to give output signal of specified frequency.

APPARATUS:

1. 2. 3. 4. 5. 6.

Transsistor-BC107-1. Resistors: 10 K - 3, 120 K - 1, 22 K - 1, 1.2 K - 1, 4.7 K - 1. Capacitors: 0.001F - 3, 10F -1, 1F -1. Regulated Power Supply Cathode Ray Oscilloscope. Bread board

CIRCUIT DIAGRAM:

THEORY:

RC-Phase shift Oscillator has a CE amplifier followed by three sections of RC phase shift feed back networks. The out put of the last stage is return to the input of the amplifier. The values of R and C are chosen such that the phase shift of each RC section is 60. Thus The RC ladder network produces a total phase shift of 180 between its input and output voltage for the given frequencies. Since CE Amplifier produces 180 phases shift the total phase shift from the base of the transistor around the circuit and back to the base will be exactly 360 or 0. This

satisfies the Barkhausen condition for sustaining oscillations and total loop gain of this circuit is greater than or equal to 1, this condition used to generate the sinusoidal oscillations. The frequency of oscillations of RC-Phase Shift Oscillator is,

1 f= ----------2RC* 6 PROCEDURE:

1. Make the connection as per the circuit diagram as shown above.

2. Observe the output signal and note down the output amplitude and time period (Td).

3. Calculate the frequency of oscillations theoretically and verify it practically (f=1/Td). 4. Calculate the phase shift at each RC section by measuring the time shifts (Tp) between the final waveform and the waveform at that section by using the below formula.

OBSERVATIONS:

THEORITICAL CALCULATIONS: R = 10000, C = 0.001 f

1 f= ----------------- = 2RC* 6

1 ------------- = 6.497 kHZ 6.283*10-5

PRACTICAL CALCULATIONS:

Td =165*10-6

1 f= ----------------Td Tp (1) 1= --------* 3600 = Td

Tp (2) 2 = --------- * 3600 = Td

Tp (3) 3= ---------- * 3600 = Td RESULT:

VIVA QUESTIONS:

5. SINGLE TUNED VOLTAGE AMPLIFIER

AIM: To plot the frequency response of a single tuned voltage amplifier.

APPARATUS:

1. 2. 3. 4. 5. 6. 7. 8.

Transistor SL 100 -1 Resistors 56K, 33K,560,100K Capacitor 0.1 F Inductor - 100mH Regulated Power Supply Function generator CRO Bread board

CIRCUIT DIAGRAM:

THEORY:

The signal to be amplified is applied between the terminals base and emitter. The tank circuit is tuned (i.e L or C may be varied) in such a way that the resonant frequency becomes equal to the frequency of the input signal. At resonance the tuned circuit offers very high impedance and thus, the given input signal is amplified by the amplifier and appears with large value across it and other frequencies will be rejected. So the tuned circuit selects the derived frequency and rejects all other frequencies. PROCEDURE:

1. Connections are made as per the circuit diagram. 2. Set Vi = 50mV using the signal generator 3. Keeping the input voltage constant, vary the frequency from 10Hz to 1MHz in regular steps and note down the corresponding output voltage. 4. Plot the graph of gain in dB vs Frequency (Hz) 5. Calculate the bandwidth from the graph. THEORITICAL CALCULATIONS: L = 100mH, C = 0.1 f

1 f= ----------------- = 2LC

1 ----------------------------- = 1.6 kHZ 2100*10-3*0.1* 10-6

PRACTICAL CALCULATIONS:

Td =

1 f= ----------------Td PRECAUTIONS: =

1. Transistor terminals must be identified properly

RESULT:

6. SERIES VOLTAGE REGULATOR

AIM: i)To design & construct a series voltage regulator as per given specifications ii) To calculate line and load regulation

APPARATUS:

1. 2. 3. 4. 5. 6. 7. 8.

Transistors SL 100 -2 Zener diode 6.2V Resistors 270, 1K, 2.2K, 6.8K, 8.2K Decade Resistance Box Ammeter (0-100mA) Multimeter Regulated Power Supply Bread board

CIRCUIT DIAGRAM:

(1) LINE REGULATION:

(2) LOAD REGULATION:

THEORY: Voltage regulator converts a dc input voltage in to a chosen dc voltage which is stable under conditions of load current and input variation. A series regulator using an additional transistor as an error amplifier, it improves the line and load regulation of the circuit. Resistor R2 and zener diode are the reference source. Transistor Q2 and its associated circuit components constitute the error amplifier, that controls the series pass transistor. When the circuit output changes, the change is amplified by transistor Q2 and fed back to the base of Q1 to correct the output voltage level. Now suppose Vo decreases , VBE2 decreases .Because emitter voltage of Q2 is held at Vz, any decrease in VBE2 appears across the base emitter of Q2.A reduction ib VBE2 causes IC2 to be reduced,VR1 is reduced and VB1 is increased causing the output voltage increase.

DESIGN:

Select Vz =0.75*Vo = 0.75* 8V = 9V

For D1, use a IN (

) Zener diode with Vz= 6.2V

For minimum D1 current, Select IR2 = 10mA

Vo - Vz R2 = ------------- = IR2

12V 6.2V --------------- = 290 ( use 270 standard value ) 10mA

IE1(max) = IL(max) + IR2= 40mA + 10mA = 50mA

Specification for Q1,

VCE1(max) = VS = 20V

IC1(max) = IE(max) =50mA PD(max) =( VS Vo)* IE1(max) = (20V 8V)*50mA = 600mW Assuming hFE1(min) = 50,

IE1(max)

50mA

IB1(max) = --------------- = ------------- = 1mA hFE1(min) 50

IC2 > IB1(max)

Select IC2 =5mA

VS --VB1

20V -- (8V + 0.7V)

R1 = --------------- = ------------------------- = 1.89 k (use 1.8 k standard value)

IC2 -- IB1

5mA + 1mA

IZ = IE2(max) + IR2 = 5mA +10mA = 15mA

I4 > > IB1(max)

I4 = 1mA

Vz VBE2

6.2V + 0.7V

R4 = -------------- = ------------------ = 6.9K (use 6.8k standard value) I4 1mA

Vo VR4 R3 = -------------- = I4

8V + 0.7V

8 5.8

---------------- = --------- = 2.2K 1m 1mA

PROCEDURE:

Line Regulation:

1. Connections are made as per the circuit diagram. 2. Using the regulated power supply vary the input voltage and note down the corresponding output voltage.

Load Regulation:

1. Connections are made as per the circuit diagram. 2. Keep the input voltage constant at which the line regulation is obtained and DRB is kept at 10K. 3. By go on decreasing the load resistance, note down the load current and load voltages. 4. Calculate the % load regulation using the following formula % Load regulation = (VNL VFL) / VFL 100 Where VNL = Input voltage at which the line regulation is obtained 5. Plot the graph of load resistance versus % Load regulation

OBSERVATIONS :

LINE REGULATION :

S.NO

INPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

LOAD REGULATION :

S.NO

LOAD RESISTANCE

LOAD CURRENT LOAD VOLTAGE

% LOAD REGULATION

PRECAUTIONS:

1.

Transistor terminals must be identified properly

RESULT:

7. SHUNT VOLTAGE REGULATOR

AIM:

To design, construct and plot the load regulator characteristics of shunt voltage regulator

APPARATUS:

1. 2. 3. 4. 5. 6. 7. 8.

Transistors SL 100 -2 Zener diode 6.2V Resistors 100, 220, 1K Decade Resistance Box Ammeter (0-100mA) Multimeter Regulated Power Supply Bread board

CIRCUIT DIAGRAM:

(1) LINE REGULATION:

(2) LOAD REGULATION:

THEORY: If control element is connected in shunt with the load the regulator circuit is called shunt voltage regulator. The unregulated input voltage Vin tries to provide the load current, but part of the current is taken by the control element, to maintain a constant voltage across the load. If there is any change in load voltage the sampling circuit provides a feed back signal to the comparator circuit. The comparator circuit compares the feed back signal with the reference voltage and generates a control signal which decides the amount of current required to be shunted to keep the load voltage constant. Now suppose if load voltage increases than comparator circuit decides the control signal based on the feed back information which draws increased shunt current ISH value Due to this load current decreases and hence the load voltage decreases to its normal value. Thus control element maintains the constant output voltage by shunting the current, hence the regulator circuit is called a shunt voltage regulator.

PROCEDURE:

Line Regulation:

1. Connections are made as per the circuit diagram. 2. Using the regulated power supply vary the input voltage and note down the corresponding output voltage.

Load Regulation:

1. Connections are made as per the circuit diagram. 2. Keep the input voltage constant at which the line regulation is obtained and DRB is kept at 10K. 3. By go on decreasing the load resistance, note down the load current and load voltages. 4. Calculate the % load regulation using the following formula % Load regulation = (VNL VFL) / VFL 100 Where VNL = Input voltage at which the line regulation is obtained 5. Plot the graph of load resistance versus % Load regulation

OBSERVATIONS:

LINE REGULATION :

S.NO

INPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

LOAD REGULATION :

S.NO

LOAD RESISTANCE

LOAD CURRENT LOAD VOLTAGE % LOAD REGULATION

PRECAUTIONS:

1. Transistor terminals must be identified properly

RESULT: