Lecture #2

Introduction to VHDL

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VHDL
An acronym for: VHSIC Hardware Description Language VHSIC was the name of a Department of Defense program that funded the development of VHDL. VHSIC was an acronym for: Very High Speed Integrated Circuits Some thought VHSIC should have stood for: Very Healthy Sums of Instant Cash because it was a very well funded program.
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History of VHDL
1981 1983 1985 19861987 1988 1993 1981 Dept. of Defense (DoD) issued requirements for a new standardized HDL to replace the Babel of proprietary HDLs that existed -1983 Contract awarded to three companies: IBM, TI, Intermetrics 1985 Version 7.2 release to the public. Strong industrial participation throughout the development process -1986 Transferred to IEEE for standardization. Language was substantially enhanced by a standards committee, consisting of industry, university, and government representatives. 1987 (Dec) Publication of IEEE Std. 1076-1987, also recognized by ANSI (American National Standards Institute) Defacto world standard -BYU ECEn 493R

History of VHDL
1981 1983 1985 19861987 1988 1993 1988 Dept. of Defense (DoD) requires that all ASIC providers deliver VHDL descriptions with their chips -1993 Language revised, some problems resolved. New version released as IEEE Std. 1076-1993 2002 You learn VHDL---

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Features
Embodies a formal specification of digital systems which is standard and non-proprietary (paid by your tax $$) Provides a medium of exchange between
Supplier and Buyer (Lockheed and DoD) Supplier and Designer Designer and Designer Designer and CAD tool CAD tool A and CAD tool B

Its not technology specific Supports hierarchical designs Has precise simulation semantics Includes timing model that supports concurrency, synchronous (clocked) and asynchronous circuits Supports three basic design styles: structural, dataflow, and behavioral
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Synthesizable VHDL
Even though VHDL was designed for the purpose of writing formal specifications of digital systems which can be simulated--- it has also become the source language for synthesis tools. The synthesis technology was pioneered by Synopsys. However, today there are many synthesis companies: Cadence, Mentor, Synplicity, Synopsys, and Xilinx.

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Synthesizable VHDL
Not all valid VHDL files are synthesizable. We will try to show you how to write synthesizable VHDL, which is an important subset of the VHDL language. All examples will be synthesizable. You will probably have occasion to write VHDL code which is valid VHDL, but is not synthesizable. When this happens, you must rewrite your VHDL so the synthesizer can make sense of it.
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The Entity
The entity is the model (or abstraction) of a digital system. It has two parts: External View : Entity Declaration Internal Description : Architecture More than one Architecture may be defined for each Entity. However, before elaboration, the system must be configured to choose which architecture to be used-BYU ECEn 493R

Basic VHDL Structure

Entity Declaration
The external view of a block

Architecture
The internal view of a block There may be many different architectures for the same entity

Entity = a model of a digital system

Component
A reference to a block
An entity in this file An entity in another file An entity in a library An external block
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Component = a reference to a digital system that can be instantiated

Basic VHDL Structure

Component

Entity Declaration
Architecture (structural)
Component Component

Entity Decl
(in your design)

Entity Decl
(in library)

Architecture (behavioral)

External Design
(not in VHDL)

Component

Entity
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Entity
entity entity_name is [ generic ( generic_declarations ); ] [ port ( port_declarations ); ] end [ entity_name ] ;

entity_name The name of the entity generic_declarations parameters used for sizing or configuring the entity. port_declarations the names and types of the input and output ports

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Example : NAND2 Entity

entity NAND2 is port ( A : in std_logic; B : in std_logic; C : out std_logic ); end NAND2;

-- first input -- second input -- output

Comments
-- anything to the end of line
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Entity Generic Specifications

Generics allow the entity to be parameterized
generic ( constant_name : type [ := value ] { ; constant_name : type [ := value ] } );

constant_name name of the parameter (or comma-separated list of names) type data-type of the parameter value optional default value of parameter
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Entity Port Specifications

Ports are the inputs and outputs of the entity.
port ( port_name : mode type { ; port_name : mode type } );

port_name name of the port (or commaseparated list of port names) mode in, out, buffer, or inout type data-type of the port value
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Example : N-bit Comparator

-- Block to compare two N-bit inputs entity COMP is generic ( N : integer := 8 --default 8-bits ); port ( X, Y : in std_logic_vector(N-1 downto 0); EQ : out std_logic ); end COMP; N X N EQ Y

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Architecture
architecture architecture_name of entity_name is { block_declarative_item } begin { concurrent_statement } end [ architecture_name ] ;

architecture_name name of architecture entity_name the name of the entity being implemented block_declarative_item components, signals, etc. concurrent_statement things executed in parallel

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entity counter3 is port ( clk : in std_logic; reset : in std_logic; count : out std_logic_vector(2 downto 0) ); end counter3;

Example : Implementation of a 3-bit Counter

architecture my_design of counter3 is signal count_x : std_logic_vector (2 downto 0); begin process(clk,reset) begin if reset=1 then count_x <= 000; elsif clkevent and clk=1 then --rising edge of clk count_x <= count_x + 1; end if; end process; count <= count_x; end my_design;
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Is this a behavioral or a structural architecture?

Find the Errors

entity x is port ( a, b : in std_logic; c, d : out std_logic; ); end x; architecture x_aroo of x is signal a : std_logic; signal d : std_logic; begin . . . end x_aroo;

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Declarations in an Architecture
Components
declaration of a reference to other entities/designs

Signals
wires that connect concurrent statements in an architecture together through interface ports

Constants
named values of a given type

Types
define data-types for signals, ports, generics and constants

Things declared in an architecture are local to that architecture.

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Component Declarations
Component declarations reference entities and other design modules, in order to allow instantiation.
component entity_name [ generic { generic_declarations } ; ] [ port { port_declarations } ; ] end component; entity_name The name of the referenced entity generic_declarations default values for entity parameters (must agree with entity) port_declarations the names and type of the input and output ports (must agree with entity)
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Examples : NAND2 and ADD Components

component and2 port ( I1, I2 : in std_logic; O1 : out std_logic ); end component; component add generic ( N : positive ); port ( X, Y : in std_logic_vector(N-1 downto 0); Z : out std_logic_vector(N-1 downto 0); CARRY : out std_logic ); end component;
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Sources of Components
An entity in the same VHDL file An entity in another VHDL file A component from a library Another format such as EDIF or a netlist

port names port types port widths port modes (in, out, buffer, inout)
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Agreement of Components and Entities

These must match

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Signals
Signal declarations create new wires that can be used to interconnect concurrent statements.
signal sig_name : type [ := default_value ] ; sig_name name of the signal (comma seperated list of names) type type of the signal default_value optional initial value of wire, used only in simulation
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Constants
Constant declarations create named values of a given type.
constant cons_name : type := default_value ; cons_name name of the signal (or commaseparated list of names) type type of the constant default_value value of constant

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Examples : Signals and Constants

signal A, B : std_logic; signal data_bus : std_logic_vector(31 downto 0); constant gnd : std_logic := 0; constant vdd : std_logic := 1; constant bus_all_ones : std_logic_vector (31 downto 0) := 11111111111111111111111111111111;

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Types
Type declarations create new types that can be used to declare signals.
type type_name is type_definition ; type_name name of the new type type_definition type of the signal integer_type_definition : range expression ( to | downto ) expression enumeration_type_definition: ( identifier | character_literal { , ... } )
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Example: Types
constant number_of_bits : integer := 32; type bit_index is range 0 to number_of_bits - 1; type day_of_month is range 1 to 31; type alu_function is (pass_A, not_A, A_and_B, A_or_B, A_add_B, A_sub_B); type state is (initial_state, stateA, stateB ); type boolean is (false, true); type bit is (0, 1); -- PREDEFINED -- PREDEFINED

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Array Types
Constrained Array Type Definition
type array_type_name is array ( integer_range ) of type_name ;

Unconstrained Array Type Definition

type array_type_name is array ( range_type_name range <> ) of type_name ;

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Types

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PACKAGE std_logic_1164 IS

-------------------------------------------------------------------- logic state system (unresolved) ------------------------------------------------------------------TYPE std_ulogic IS ( 'U', -- Uninitialized 'X', -- Forcing Unknown '0', -- Forcing 0 '1', -- Forcing 1 'Z', -- High Impedance 'W', -- Weak Unknown 'L', -- Weak 0 'H', -- Weak 1 '-' -- Don't care ); -------------------------------------------------------------------- unconstrained array of std_ulogic for use with the resolution function ------------------------------------------------------------------TYPE std_ulogic_vector IS ARRAY ( NATURAL RANGE <> ) OF std_ulogic; -------------------------------------------------------------------- resolution function ------------------------------------------------------------------FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic; -------------------------------------------------------------------- *** industry standard logic type *** ------------------------------------------------------------------SUBTYPE std_logic IS resolved std_ulogic; -------------------------------------------------------------------- unconstrained array of std_logic for use in declaring signal arr ays ------------------------------------------------------------------TYPE std_logic_vector IS ARRAY ( NATURAL RANGE <>) OF std_logic; -- functions (and, or, not ...) operating on std_logic defined ... END std_logic_1164;
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IEEE Std Logic

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PACKAGE BODY std_logic_1164 IS

-------------------------------------------------------------------- local types ------------------------------------------------------------------TYPE stdlogic_1d IS ARRAY (std_ulogic) OF std_ulogic; TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic; -------------------------------------------------------------------- resolution function ------------------------------------------------------------------CONSTANT resolution_table : stdlogic_table := ( ----------------------------------------------------------| U X 0 1 Z W L H | | ---------------------------------------------------------( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X | ( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 | ( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 | ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z | ( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W | ( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L | ( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - | ); FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic IS VARIABLE result : std_ulogic := 'Z'; -- weakest state default BEGIN -- the test for a single driver is essential otherwise the -- loop would return 'X' for a single driver of '-' and that -- would conflict with the value of a single driver unresolved -- signal. IF (s'LENGTH = 1) THEN RETURN s(s'LOW); ELSE FOR i IN s'RANGE LOOP result := resolution_table(result, s(i)); END LOOP; END IF; RETURN result; BYU ECEn 493R END resolved;

IEEE Std Logic

Body of an Architecture: Concurrent Statements

Concurrent statements do the following: Read input signal values Perform computation using input signal values Assign computed values to output signals

Concurrent statements may be written in any order. They are executed on a demand-driven basis.

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Concurrent Statements
Component Instantiation Statements
Creates an instance of an entity (component) connecting its interface ports to signals or interface ports of the entity being defined (structural)

Concurrent Signal Assignment Statements

Assign computed values to signals or interface ports (dataflow)

Process Statements
Defines sequential algorithms that read values of signals and compute new values to assign to other signals (behavioral)

Block Statements
Groups a set of concurrent statements

Procedure Call Statements

Calls procedures that compute and assign values to signals
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VHDL Coding Styles

Structural
Hierarchically describes a circuit in terms of lower level circuits

Dataflow
Functionally describes the flow of data from one signal to another

Behavioral
Algorithms are used describe the circuit

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Component Instantiation Statement

Instantiate a component that has been previously declared--- structural VHDL.
instance_name : component_name [ generic map ( generic_name => expression [ { , generic_name => expression } ] ) ] port map ( [ port_name => ] sig_name [ { , [ port_name => ] sig_name } ] );
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Examples : Component Instantiation

component add generic ( Declaration of N : positive Component ); port ( X, Y : in std_logic_vector(N-1 downto 0); Z : out std_logic_vector(N-1 downto 0) ); end component; U1 : add generic map ( N => 4 ) port map ( X => A, Y => B, Z => SUM );

Instantiation of Component port map uses named associations there can be many instantiations.
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Examples : Component Instantiation

component add generic ( Declaration of N : positive Component ); port ( X, Y : in std_logic_vector(N-1 downto 0); Z : out std_logic_vector(N-1 downto 0) ); end component;

U1 : add generic map ( N => 4 ) port map ( A, B, SUM );

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Instantiation of Component port map uses positional association, signals must be in same order as ports in component declaration

Example Three-bit Counter

architecture structure of counter3 is -- declarations component DFF port ( clk, data : in std_logic; q : out std_logic ); end component; component INV port ( I : in std_logic; O : out std_logic ); end component; component OR2 port ( I1, I2 : in std_logic; O : out std_logic ); end component; component XNOR2 port ( I1, I2 : in std_logic; O : out std_logic ); end component; component NAND2 port ( I1, I2 : in std_logic; O : out std_logic ); end component; signal N1, N2, N3, N4, N5, N6, N7, N8, N9 : std_logic; begin -- concurrent statements -- on next page end structure;

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Example Three-bit Counter

architecture structure of counter3 is -- declarations from previous page begin -- concurrent statements U1 U2 U3 U4 U5 U6 U7 U8 U9 : : : : : : : : : DFF port map( CLK, N1, N2 ); DFF port map( CLK, N5, N3 ); DFF port map( CLK, N9, N4 ); INV port map( N2, N1 ); OR2 port map( N3, N1, N6 ); NAND2 port map ( N1, N3, N7 ); NAND2 port map ( N6, N7, N5 ); XNOR2 port map ( N8, N4, N9 ); NAND2 port map ( N2, N3, N8 );

Declarations from previous page

Instantiation statements

count(0) <= N2; count(1) <= N3; count(2) <= N4; end structure;
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Signal assignment statements

Concurrent Signal Assignment Statements

Provides a new value for a signal--- dataflow VHDL Models Combinational Logic only--- no Sequential Logic . . . Two types : Conditional Signal Assignment Statement Selected Signal Assignment Statement
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[ label : ] signal_name <= { waveform when boolean_expression else } waveform [ when boolean_expression ] ; signal_name name of signal to be changed

Conditional Signal Assignment Statement (Concurrent)

boolean_expression an expression which evaluates to a boolean value (true or false)

And where a

waveform

is :

value_expression [ after time_expression ] {, value_expression [ after time_expression ] } value_expression an expression for the new value time_expression optional delay time used in simulation, such as: 2 ns (ignored for synthesis)
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Conditional Signal Assignment Examples

x <= y; x <= not x after 10 ns; x <= (y or z) and u; out <= in1 when sel=00 else in2 when sel=01 else in3 when sel=10 else in4; bus <= data when enable=1 else ZZZZZZZZ; reset <= 1, 0 after 100 ns;

VHDL is strongly typed. The operations available depend on the data typeECEn 493R of the signals. BYU

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[ label : ] with expression select signal_name <= { waveform when choices , } waveform when choices ;
expression key value which is used to make the selection

Selected Signal Assignment Statement (Concurrent)

signal_name name of signal to be changed choices waveform a vertical-bar (|) separated list of selection choices same as before

Every possible value of expression must be accounted for in one of the choices. No value can be included in more than one choice.
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Selected Signal Assignment Examples

type alu_function is (pass_A, not_A, A_and_B, A_or_B, A_add_B, A_sub_B); signal alu_op : alu_function; begin -- body of architecture when when when when when when pass_A not_A A_and_B A_or_B A_add_B A_sub_B , , , , , ;

with alu_op select alu_out <= A not A A and B A or B A + B A B

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Std_Logic and Std_Logic_Vector Expressions

Logical operations available: ( in package std_logic_1164 ) and nand or nor xor xnor* not A and B A nand B A or B A nor B A xor B A xnor B not A Arithmetic operations available: ( in package std_logic_unsigned, or std_logic_signed ) add A + B sub A - B mul A * B comparisons <, <=, >, >=, =, /= A < B (returns a boolean) shift left* A SHL B shift right* A SHR B

* Not available in all implementations

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Process Statement (Concurrent)

[ label : ] process [ ( sensitivity_list ) ] [ { process_declarative_item } ] begin { sequential_statement } end process [ label ] ;

label option name for the process sensitivity_list comma-separated list of signals whose changes require resumption of the process process_declarative_item a declaration local to the process sequential_statement like if, case, etc.
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Process Statements
A Process is a concurrent statement, but is made up of sequentially executed statements that define algorithms. These sequential statements may be any of the following : case statement exit statement if statement loop statement next statement null statement wait statement procedure call signal assignment variable assignment

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Process Statements
Processes, like all other concurrent statements, read and write signals and the values of the interface ports to communicate with the rest of the architecture and with the enclosing system. Processes are unique, in that they behave like concurrent statements to the rest of the design, but internally, they are sequential. In addition, only processes can define variables to hold intermediate values in a sequence of computations.
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Process Statement
Processes never exit. When a process finishes, it suspends (sleeps) until one of the signals in its sensitivity list changes, whereupon it resumes at the beginning of the process.

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Sequential vs. Concurrent Statements

WARNING: Sequential statements can only be used inside a process, and cannot be used as stand-alone concurrent statements. Concurrent statements cannot be used inside processes. A sequential version of the signal assignment statement may be used in a process.
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Example : Process Statement

The D-type Flip-Flop with asynchronous reset
process (clk, reset) begin if reset=1 then q <= 0; elsif clkevent and clk=1 then q <= d; end if; end process; Why is the input d not in the sensitivity list? Means rising edge of clk
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Process Statement
Process statements are the only way to represent clocked logic ( i.e. , sequential logic) . Dont go overboard with processes, or you will end up with something that is not synthesizable or something that will synthesize into an inefficient circuit. You will be learning the basic process forms for common circuits.
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Wait Statement (Sequential)

[ label : ] wait [ on signal_name { , ... } ] [ until boolean_expression ] [ for time_expression ] ;

Causes the process to suspend (sleep) until the signal signal_name has an event (changes) the boolean_expression becomes true the time_expression amount of time elapses
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The Wait Statement and the Sensitivity List

Equivalent process (a, b, c) process begin begin -- process body wait on a,b,c; end -- process body end

implicit loop

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[ label : ] signal_name <= value_expression [ after time_expression ] {, value_expression [ after time_expression ]};

Signal Assignment Statement (Sequential)

signal_name

name of signal to be changed

value_expression an expression for the new value time_expression optional delay time used in simulation, such as: 2 ns (ignored for synthesis)

Only this kind of simple assignment statement may be used in a process. You cannot use the concurrent conditional or selected signal assignments in a process.
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Signal Assignment Examples

process begin A <= 1 after 5, 0 after 10; end; process begin A <= 0 after 10; A <= 1 after 5; end; process begin B <= C; A <= B; end;

What happens to signal A in these three examples?

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If Statement (Sequential)
[ label : ] if boolean_expression then { sequential_statement } { elsif boolean_expression then { sequential_statement } } [ else { sequential_statement } ] end if [ label ] ;

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If Statement Examples

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Case Statement (Sequential)

[ label : ] case expression is { when choices => { sequential_statement } } end case [ label ] ; Where choices is a vertical-bar (|) separated list containing : simple_expression , or discrete_range , or the keyword others (must be the last choice)

Every possible value of expression must be accounted for in one of the choices. No value can be included in more than one choice.
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Null Statement (Sequential)

[ label : ] null ;

No action is performed

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Case Statement Examples

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Loop Statement (Sequential)

[ label : ] loop { sequential_statement } end loop [ label ] ;

An infinite loop of sequential statements. Since we are modeling digital systems, loops are used to model hardware that repeatedly performs the same function (until power is turned off) .

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Exit Statement (Sequential)

[ label : ] exit [ loop_label ] [ when boolean_expression ] ;

loop_label label of the loop being exited

Exit a loop without executing any further instructions in the loop.

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Exit Statement Examples

exit when i>10; if i>10 then exit; end if; exit when reset=1; outer: loop i <= 1; inner: loop i <= i+1; if i>10 then exit inner; end if; end loop; end loop; -- short hand for ...

-- actually, this is the default

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Next Statement (Sequential)

[ label : ] next [ loop_label ] [ when boolean_expression ] ;

loop_label label of the loop being restarted

Restart a loop The current iteration is completed without executing any further instructions.
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While Loop Statement (Sequential)

[ label : ] while boolean_expression loop { sequential_statement } end loop [ label ] ;

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For Loop Statement (Sequential)

[ label : ] for identifier in discrete_range loop { sequential_statement } end loop [ label ] ;

discrete_range

is: or

simple_expression to simple_expression,

simple_expression downto simple_expression

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All Concurrent Statements are Really Processes In Disguise

a <= b; process(b) begin a <= b; end process; process(a, b, c, d, sel) begin if sel = 00 then q <= a; elsif sel = 01 then q <= b; elsif sel = 10 then q <= c; else q <= d; end if; end process;

q <= a when sel=00 else b when sel=01 else c when sel=10 else d;

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All Concurrent Statements are Really Processes In Disguise

with sel select q <= a when 00, b when 01, c when 10, d when others; process(a, b, c, d, sel) begin case sel is when 00 => q <= a; when 01 => q <= b; when 10 => q <= c; when others => q <= d; end case; end process; process(b) begin for i in brange loop a(i) <= not(b(i)); end loop; end process;

a <= not(b); -- a, b are vectors

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Decoder
-- 3 to 8 Decoder, Synchronous with Reset -RESET: in STD_LOGIC; -CLK: in STD_LOGIC; -D_IN: in STD_LOGIC_VECTOR(2 downto 0); -D_OUT: out STD_LOGIC_VECTOR(7 downto 0); process(CLK,RESET,D_IN) begin if ( RESET = '1') then D_OUT <= "00000000"; elsif ( CLK'event and CLK ='1') then case D_IN is when "000" => D_OUT <= "00000001"; when "001" => D_OUT <= "00000010"; when "010" => D_OUT <= "00000100"; when "011" => D_OUT <= "00001000"; when "100" => D_OUT <= "00010000"; when "101" => D_OUT <= "00100000"; when "110" => D_OUT <= "01000000"; when "111" => D_OUT <= "10000000"; when others => NULL; end case; end if; end process; BYU ECEn 493R

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Encoder
-- 8 to 3 Encoder, Synchronous with Reset -RESET: in STD_LOGIC; -CLK: in STD_LOGIC; -D_IN: in STD_LOGIC_VECTOR(7 downto 0); -D_OUT: out STD_LOGIC_VECTOR(2 downto 0); process(CLK,RESET,D_IN) begin if ( RESET = '1') then D_OUT <= "000"; elsif ( CLK'event and CLK ='1') then case D_IN is when "00000001" => D_OUT <= "000"; when "00000010" => D_OUT <= "001"; when "00000100" => D_OUT <= "010"; when "00001000" => D_OUT <= "011"; when "00010000" => D_OUT <= "100"; when "00100000" => D_OUT <= "101"; when "01000000" => D_OUT <= "110"; when "10000000" => D_OUT <= "111"; when others => NULL; end case; end if; end process; BYU ECEn 493R

Comparator
------N-bit Comparator, synchronous with reset Please define the value of N for A and B CLK : in STD_LOGIC; RESET : in STD_LOGIC; A, B : in STD_LOGIC_VECTOR(N downto 0); ALB : out STD_LOGIC;

process(CLK,RESET) begin if (RESET = '1') then ALB <= '0'; elsif (CLK'event and CLK ='1') then if ( A < B ) then ALB <= '1'; else ALB <= '0'; end if; end if; end process;
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A A<B B

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--HEX-to-seven-segment decoder -HEX: in STD_LOGIC_VECTOR (3 downto 0); -LED: out STD_LOGIC_VECTOR (6 downto 0);
--- segment encoding -0 ----- 5 | | 1 ---<- 6 -- 4 | | 2 ----3

Hex to 7-Segment Decoder

with HEX SELect LED<= "1111001" "0100100" "0110000" "0011001" "0010010" "0000010" "1111000" "0000000" "0010000" "0001000" "0000011" "1000110" "0100001" "0000110" "0001110" "1000000"

when when when when when when when when when when when when when when when when

"0001", "0010", "0011", "0100", "0101", "0110", "0111", "1000", "1001", "1010", "1011", "1100", "1101", "1110", "1111", others;

--1 --2 --3 --4 --5 --6 --7 --8 --9 --A --b --C --d --E --F --0

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Multiplexor
process (SEL, A, B, C, D) begin case SEL is when 00 => MUX_OUT <= when 01 => MUX_OUT <= when 10 => MUX_OUT <= when 11 => MUX_OUT <= when others => NULL; end case; end process; MUX_OUT MUX_OUT MUX_OUT MUX_OUT <= <= <= <= A B C D when when when when (SEL(0)='0') (SEL(1)='0') (SEL(2)='0') (SEL(3)='0') A; B; C; D;
00 01 10 11

else else else else

'Z'; 'Z'; 'Z'; 'Z';

MUX_OUT <= A when SEL=00 else B when SEL=01 else C when SEL=10 else D;
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4-Bit Loadable Up-Down Counter

-- Required Libraries library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.STD_LOGIC_ARITH.ALL; -- 4-bit synchronous counter with count enable, -- asynchronous reset and synchronous load -CLK: in STD_LOGIC; -RESET: in STD_LOGIC; -CE, LOAD, DIR: in STD_LOGIC; -DIN: in STD_LOGIC_VECTOR(3 downto 0); -COUNT: inout STD_LOGIC_VECTOR(3 downto 0); process (CLK, RESET) begin if RESET='1' then COUNT <= "0000"; elsif CLK='1' and CLK'event then if LOAD='1' then COUNT <= DIN; else if CE='1' then if DIR='1' then COUNT <= COUNT + 1; else COUNT <= COUNT - 1; end if; end if; end if; end if; BYU ECEn 493R end process;

CE DIR

LOAD RST

-- D Latch -GATE: in STD_LOGIC; -DIN: in STD_LOGIC; -DOUT: out STD_LOGIC; process (GATE, DIN) begin if GATE='1' then DOUT <= DIN; end if; end process;

Latch
Without Reset

--GATE active High

-- D Latch with Reset -GATE: in STD_LOGIC; -RESET: in STD_LOGIC; -DIN: in STD_LOGIC; -DOUT: out STD_LOGIC; process (GATE, DIN, RESET) begin if RESET='1' then --RESET active High DOUT <= '0'; elsif GATE='1' then --GATE active High DOUT <= DIN; end if; BYU ECEn 493R end process;

With Reset

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DFF with Asynchronous Reset

-- D Flip Flop with Asynchronous Reset -CLK: in STD_LOGIC; -RESET: in STD_LOGIC; -DIN: in STD_LOGIC; -DOUT: out STD_LOGIC;
rst

process (CLK, RESET) begin if RESET='1' then DOUT <= '0'; elsif (CLK'event and CLK='1') then DOUT <= DIN; end if; end process;

BYU ECEn 493R

DFF with Synchronous Reset

-- D Flip Flop with Synchronous Reset -CLK: in STD_LOGIC; -RESET: in STD_LOGIC; -DIN: in STD_LOGIC; -DOUT: out STD_LOGIC;
rst

process (CLK) begin if CLK'event and CLK='1' then if RESET='1' then DOUT <= '0'; else DOUT <= DIN; end if; end if; end process;
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DFF with Enable

-- D Flip Flop with Clock Enable -CLK: in STD_LOGIC; -ENABLE: in STD_LOGIC; -DIN: in STD_LOGIC; -DOUT: out STD_LOGIC; process (CLK) begin if (CLK'event and CLK='1') then if (ENABLE='1') then DOUT <= DIN; end if; end if; end process;
BYU ECEn 493R

en

----

CLOCK, RESET: in STD_LOGIC; IN1, IN2, IN3: in STD_LOGIC; OUT1, OUT2: out STD_LOGIC

State Machine

type STATE_TYPE is (S1, S2, S3, S4); -- in arch. declarations signal CS, NS: STATE_TYPE; -- current and next states SYNC_PROC: process (CLOCK, RESET) begin if (RESET='1') then CS <= S1; -- initial state on reset elsif (CLOCK'event and CLOCK = '1') then CS <= NS; end if; end process; COMB_PROC: process (CS, <other inputs>) begin case CS is when S1 => --<assign moore outputs here> if ( <conditions> ) then --<next state assignment here> --<assign mealy outputs here> end if; --repeat when clauses for all states end case; end process; BYU ECEn 493R
I O
Clk

CS NS
Rst

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State Encodings
Binary State Encodings
type STATE_TYPE is (S1, S2, S3, S4); attribute ENUM_ENCODING: STRING; attribute ENUM_ENCODING of STATE_TYPE: type is "00 01 10 11";

One-Hot State Encodings

type STATE_TYPE is (S1, S2, S3, S4); attribute ENUM_ENCODING: STRING; attribute ENUM_ENCODING of STATE_TYPE: type is "0001 0010 0100 1000";

Or leave off attribute, and let the synthesizer choose what it thinks is best . . .

BYU ECEn 493R

Packages
A package is a collection of declarations that can be used by many designs, such as : data types and subtypes constants component declarations subprograms Package structure has two parts : a declaration ( public information ) a body ( private information )
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Package
package package_name is { package_declarative_item } end [ package_name ] ; package_name name of the package package_declarative_item including : use clause (to include other packages) type declaration subtype declaration constant declaration signal declaration subprogram declaration component declaration
BYU ECEn 493R

Signals in a Package
Signals declared in packages cannot be shared across entities. If two entities use a signal from a given package, each entity has its own copy of that signal.

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Package Body
package body package_name is { package_body_declarative_item } end [ package_name ] ;

package_body_declarative_item the implementations (bodies) of subprogams declared in the package declaration and internal declarations and subprograms

BYU ECEn 493R

Library and Use Statements

library LIBRARY_NAME ; use LIBRARY_NAME.PACKAGE_NAME.ALL ;

LIBRARY_NAME the name of the VHDL library PACKAGE_NAME the name of the included package

The Library and Use statements usually immediately proceeds the package or entity that needs to use the package declarations.
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Use Statement Examples

library WORK; use WORK.MYDEFS.ALL; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library unisim; use unisim.vcomponents.all; entity ... architecture ...

BYU ECEn 493R

Generate Statements
A generate statement creates zero or more copies of an enclosed set of concurrent statements. The two kinds of statements are:
label : for identifier in range generate [ { local_declaration } begin ] { concurrent_statement } end generate [ label ] ;

The number of copies is determined by a discrete range.

label : if boolean_expression generate [ { local_declaration } begin ] { concurrent_statement } end generate [ label ] ;

Zero or one copy is made, conditionally.

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Generate Statement Example

signal A,B,SUM : std_logic_vector(3 downto 0); signal CY : std_logic_vector(4 downto 0); component FULL_ADDER port (I1, I2, CYIN : in std_logic; SUM, CYOUT : out std_logic); end component; begin ADDER: for K in 3 downto 0 generate FA: FULL_ADDER ( I1 => A(K), I1 I2 I1 I2 I2 => B(K), CYOUT CYIN CYOUT CYIN SUM SUM CYIN => CY(K), SUM => SUM(K), CYOUT => CY(K+1) ); end generate ADDER; end;
BYU ECEn 493R

I1 I2 CYOUT CYIN SUM

I1 I2 CYOUT CYIN SUM

Simulation and Synthesis

Simulation execute the VHDL model to

approximate the behavior of the digital system in terms of the occurrence events and waveforms on signals.

Synthesis generate the physical design of the

digital system. Infer the hardware structures necessary to implement the behavior modeled by the VHDL code.
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The Discrete Event Simulation Model

Models the passage of time and occurrence of events at various points in time. Concurrent statements create signal change events and then suspend waiting for more input. A scheduler orders events by time, advances time and executes the signal changes.

Signal changes re-activate concurrent statements who are sensitive to those signals.

BYU ECEn 493R

Synthesis
Primitive Digital Circuits : VHDL Model Inference Logic Gates, Flip-Flops, Latches, Small Blocks of Memory, Arithmetic Units, FSMs

Constraints on Speed or Area

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Implementation after Synthesis

Primitive Digital Circuits

Map
FPGA Primitive Resources

Place
FPGA Floorplan

Route

FPGA

BYU ECEn 493R

Architecture of the FPGA

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Architecture of the FPGA

BYU ECEn 493R

Architecture of the FPGA

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Architecture of the FPGA

BYU ECEn 493R

Architecture of the FPGA

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Architecture of the FPGA

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