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1. General description
The SC16C550B is a Universal Asynchronous Receiver and Transmitter (UART) used for serial data communications. Its principal function is to convert parallel data into serial data, and vice versa. The UART can handle serial data rates up to 3 Mbit/s. The SC16C550B is pin compatible with the ST16C550, TL16C550 and PC16C550, and it will power-up to be functionally equivalent to the 16C450. The SC16C550B also provides DMA mode data transfers through FIFO trigger levels and the TXRDY and RXRDY signals (TXRDY and RXRDY are not supported in the HVQFN32 package). On-board status registers provide the user with error indications, operational status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal loopback capability allows on-board diagnostics. The SC16C550B operates at 5 V, 3.3 V and 2.5 V, and the Industrial temperature range, and is available in plastic HVQFN32, DIP40, PLCC44 and LQFP48 packages.
2. Features
I I I I I I I I I I 5 V, 3.3 V and 2.5 V operation Industrial temperature range After reset, all registers are identical to the typical 16C450 register set Capable of running with all existing generic 16C450 software Pin compatibility with the industry-standard ST16C450/550, TL16C450/550, PC16C450/550 Up to 3 Mbit/s transmit/receive operation at 5 V, 2 Mbit/s at 3.3 V, and 1 Mbit/s at 2.5 V 5 V tolerant on input only pins1 16 byte transmit FIFO 16 byte receive FIFO with error ags Programmable auto-RTS and auto-CTS N In auto-CTS mode, CTS controls transmitter N In auto-RTS mode, RX FIFO contents and threshold control RTS Automatic hardware ow control Software selectable baud rate generator Four selectable Receive FIFO interrupt trigger levels Standard modem interface Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun Break) Independent receiver clock input Transmit, Receive, Line Status, and Data Set interrupts independently controlled
I I I I I I I
1.
NXP Semiconductors
SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
I Fully programmable character formatting: N 5, 6, 7, or 8-bit characters N Even, odd, or no-parity formats N 1, 112, or 2-stop bit N Baud generation (up to 3 Mbit/s) I False start-bit detection I Complete status reporting capabilities I 3-state output TTL drive capabilities for bidirectional data bus and control bus I Line break generation and detection I Internal diagnostic capabilities: N Loopback controls for communications link fault isolation I Prioritized interrupt system controls I Modem control functions (CTS, RI, DCD, DSR, DTR, RTS)
3. Ordering information
Table 1. Ordering information Industrial: VDD = 2.5 V, 3.3 V or 5 V 10 %; Tamb = 40 C to +85 C. Type number SC16C550BIA44 SC16C550BIBS SC16C550BIB48 SC16C550BIN40 Package Name PLCC44 HVQFN32 LQFP48 DIP40 Description plastic leaded chip carrier; 44 leads plastic thermal enhanced very thin quad at package; no leads; 32 terminals; body 5 5 0.85 mm plastic low prole quad at package; 48 leads; body 7 7 1.4 mm plastic dual in-line package; 40 leads (600 mil) Version SOT187-2 SOT617-1 SOT313-2 SOT129-1
SC16C550B_5
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NXP Semiconductors
SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
4. Block diagram
SC16C550B
TRANSMIT FIFO REGISTERS TRANSMIT SHIFT REGISTER
TX
RX
DDIS DTR RTS OUT1, OUT2 INT TXRDY RXRDY MODEM CONTROL LOGIC
002aaa585
XTAL1 RCLK
XTAL2 BAUDOUT
Fig 1.
SC16C550B_5
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SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
5. Pinning information
5.1 Pinning
42 DCD 41 DSR 40 CTS 39 RESET 38 OUT1 37 DTR 36 RTS 35 OUT2 34 n.c. 33 INT 32 RXRDY 31 A0 30 A1 29 A2 XTAL1 18 XTAL2 19 IOW 20 IOW 21 VSS 22 n.c. 23 IOR 24 IOR 25 DDIS 26 TXRDY 27 AS 28 19 A0 18 A1 17 A2 XTAL1 10 XTAL2 11 IOW 12 VSS 13 IOR 14 n.c. 15 n.c. 16 9
002aaa582
44 VDD
D0
n.c. 1
D4
D3
D2
D1
D5 D6 D7
7 8 9
SC16C550BIA44
Fig 2.
26 DCD
43 RI
32 D3
31 D2
30 D1
29 D0
D4 n.c. D5 D6 D7 RX TX CS
1 2 3 4 5 6 7 8
27 RI
SC16C550BIBS
VSS
Fig 3.
SC16C550B_5
28 VDD
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NXP Semiconductors
SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
40 DCD
39 DSR
38 CTS
42 VDD
48 n.c.
1 2 3 4 5 6 7 8 9
37 n.c. 36 n.c. 35 RESET 34 OUT1 33 DTR 32 RTS 31 OUT2 30 INT 29 RXRDY 28 A0 27 A1 26 A2 25 n.c. AS 24
002aaa583
47 D4
46 D3
45 D2
44 D1
43 D0 VSS 18
SC16C550BIB48
CS1 10 CS2 11 BAUDOUT 12 n.c. 13 XTAL1 14 XTAL2 15 IOW 16 IOW 17 IOR 19 IOR 20 n.c. 21 DDIS 22 TXRDY 23
Fig 4.
D0 D1 D2 D3 D4 D5 D6 D7 RCLK
1 2 3 4 5 6 7 8 9
41 RI
40 VDD 39 RI 38 DCD 37 DSR 36 CTS 35 RESET 34 OUT1 33 DTR 32 RTS 31 OUT2 30 INT 29 RXRDY 28 A0 27 A1 26 A2 25 AS 24 TXRDY 23 DDIS 22 IOR 21 IOR
002aaa584
SC16C550BIN40
Fig 5.
SC16C550B_5
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SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
BAUDOUT
17
12
15
14 15 16 40
9 10 11 38
12 13 14 36
8 24
D7 to D0
9, 8, 7, 6, 5, 4, 3, 2 42
8, 7, 6, 5, 4, 3, 2, 1 38
I/O
DCD[2]
DDIS
26
22
23
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SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
Pin description continued Pin PLCC44 LQFP48 DIP40 HVQFN32 41 39 37 25 I Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the Modem Status Register. Bit 1 (DSR) of the Modem Status Register indicates DSR has changed levels since the last read from the Modem Status Register. If the modem status interrupt is enabled when DSR changes levels, an interrupt is generated. Data terminal ready. When active (LOW), DTR informs a modem or data set that the UART is ready to establish communication. DTR is placed in the active level by setting the DTR bit of the Modem Control Register. DTR is placed in the inactive level either as a result of a Master Reset, during loopback mode operation, or clearing the DTR bit. Interrupt. When active (HIGH), INT informs the CPU that the UART has an interrupt to be serviced. Four conditions that cause an interrupt to be issued are: a receiver error, received data that is available or timed out (FIFO mode only), an empty Transmitter Holding Register or an enabled modem status interrupt. INT is reset (deactivated) either when the interrupt is serviced or as a result of a Master Reset. not connected Type Description
DTR
37
33
33
22
INT
33
30
30
20
n.c.
1, 12, 23, 34
2, 15, 16
OUT1 OUT2
38 35
Outputs 1 and 2. These are user-designated output terminals that are set to the active (LOW) level by setting respective Modem Control Register (MCR) bits (OUT1 and OUT2). OUT1 and OUT2 are set to inactive the (HIGH) level as a result of Master Reset, during loopback mode operations, or by clearing bit 2 (OUT1) or bit 3 (OUT2) of the MCR. Receiver clock. RCLK is the 16 baud rate clock for the receiver section of the UART. In the HVQFN32 package, BAUDOUT and RCLK are bonded internally. Read inputs. When either IOR or IOR is active (LOW or HIGH, respectively) while the UART is selected, the CPU is allowed to read status information or data from a selected UART register. Only one of these inputs is required for the transfer of data during a read operation; the other input should be tied to its inactive level (that is, IOR tied LOW or IOR tied HIGH). Master reset. When active (HIGH), RESET clears most UART registers and sets the levels of various output signals.
RCLK
10
IOR IOR[2]
25 24
20 19
22 21
14
RESET
39
35
35
23
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SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
Pin description continued Pin PLCC44 LQFP48 DIP40 HVQFN32 43 41 39 27 I Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the Modem Status Register. Bit 2 (RI) of the Modem Status Register indicates that RI has changed from a LOW to a HIGH level since the last read from the Modem Status Register. If the modem status interrupt is enabled when this transition occurs, an interrupt is generated. Request to send. When active, RTS informs the modem or data set that the UART is ready to receive data. RTS is set to the active level by setting the RTS Modem Control Register bit and is set to the inactive (HIGH) level either as a result of a Master Reset or during loopback mode operations or by clearing bit 1 (RTS) of the MCR. This pin has no effect on the UARTs transmit or receive operation. Receiver ready. Receiver Direct Memory Access (DMA) signaling is available with RXRDY. When operating in the FIFO mode, one of two types of DMA signaling can be selected using the FIFO Control Register bit 3 (FCR[3]). When operating in the 16C450 mode, only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made between CPU bus cycles. Mode 1 supports multi-transfer DMA in which multiple transfers are made continuously until the receiver FIFO has been emptied. In DMA mode 0 (FCR[0] = 0 or FCR[0] = 1, FCR[3] = 0), when there is at least one character in the receiver FIFO or Receiver Holding Register, RXRDY is active (LOW). When RXRDY has been active but there are no characters in the FIFO or holding register, RXRDY goes inactive (HIGH). In DMA mode 1 (FCR[0] = 1, FCR[3] = 1), when the trigger level or the time-out has been reached, RXRDY goes active (LOW); when it has been active but there are no more characters in the FIFO or holding register, it goes inactive (HIGH). This function does not exist in the HVQFN32 package. Serial data input. RX is serial data input from a connected communications device. Serial data output. TX is composite serial data output to a connected communication device. TX is set to the marking (HIGH) level as a result of Master Reset. Transmitter ready. Transmitter DMA signaling is available with TXRDY. When operating in the FIFO mode, one of two types of DMA signaling can be selected using FCR[3]. When operating in the 16C450 mode, only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made between CPU bus cycles. Mode 1 supports multi-transfer DMA in which multiple transfers are made continuously until the transmit FIFO has been lled. This function does not exist in the HVQFN32 package. 2.5 V, 3.3 V or 5 V supply voltage. Ground voltage. Type Description
RTS
36
32
32
21
RXRDY
32
29
29
RX TX
11 13
7 8
10 11
6 7
I O
TXRDY
27
23
24
VDD VSS
44 22
42 18
40 20
28 9, 13[1]
power power
SC16C550B_5
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SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
Pin description continued Pin PLCC44 LQFP48 DIP40 HVQFN32 21 20 17 16 19 18 12 I Write inputs. When either IOW or IOW is active (LOW or HIGH, respectively) and while the UART is selected, the CPU is allowed to write control words or data into a selected UART register. Only one of these inputs is required to transfer data during a write operation; the other input should be tied to its inactive level (that is, IOW tied LOW or IOW tied HIGH). Crystal connection or External clock input. Crystal connection or the inversion of XTAL1 if XTAL1 is driven. Type Description
XTAL1 XTAL2[3]
18 19
14 15
16 17
10 11
I O
[1]
HVQFN32 package die supply ground is connected to both the VSS pin and the exposed center pad. The VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the Printed-Circuit Board (PCB) in the thermal pad region. This pin has a pull-up resistor. In Sleep mode, XTAL2 is left oating.
[2] [3]
6. Functional description
The SC16C550B provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. Synchronization for the serial data stream is accomplished by adding start and stop bits to the transmit data to form a data character (character orientated protocol). Data integrity is insured by attaching a parity bit to the data character. The parity bit is checked by the receiver for any transmission bit errors. The SC16C550B is fabricated with an advanced CMOS process to achieve low drain power and high speed requirements. The SC16C550B is an upward solution that provides 16 bytes of transmit and receive FIFO memory, instead of none in the 16C450. The SC16C550B is designed to work with high speed modems and shared network environments that require fast data processing time. Increased performance is realized in the SC16C550B by the larger transmit and receive FIFOs. This allows the external processor to handle more networking tasks within a given time. In addition, the four selectable levels of FIFO trigger interrupt are provided for maximum data throughput performance, especially when operating in a multi-channel environment. The combination of the above greatly reduces the bandwidth requirement of the external controlling CPU, increases performance, and reduces power consumption. The SC16C550B is capable of operation up to 3 Mbit/s with a 48 MHz external clock input (at 5 V).
SC16C550B_5
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SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
Internal registers decoding A1 0 0 1 1 0 0 1 1 0 0 A0 0 1 0 1 0 1 0 1 0 1 Read mode Receive Holding Register Interrupt Enable Register Interrupt Status Register Line Control Register Modem Control Register Line Status Register Modem Status Register Scratchpad Register (DLL/DLM)[2] LSB of Divisor Latch MSB of Divisor Latch LSB of Divisor Latch MSB of Divisor Latch Write mode Transmit Holding Register Interrupt Enable Register FIFO Control Register Line Control Register Modem Control Register n/a n/a Scratchpad Register
These registers are accessible only when LCR[7] is a logic 0. These registers are accessible only when LCR[7] is a logic 1.
SC16C550B_5
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SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
UART 1 SERIAL TO PARALLEL RX FIFO FLOW CONTROL D7 to D0 PARALLEL TO SERIAL TX FIFO FLOW CONTROL CTS RTS TX RX RTS CTS
UART 2 PARALLEL TO SERIAL TX FIFO FLOW CONTROL D7 to D0 SERIAL TO PARALLEL RX FIFO FLOW CONTROL
002aaa228
RX
TX
Fig 6.
6.3.1 Auto-RTS
Auto-RTS data ow control originates in the receiver timing and control block (refer to Figure 1 Block diagram of SC16C550B) and is linked to the programmed receiver FIFO trigger level (see Figure 6). When the receiver FIFO level reaches a trigger level of 1, 4, or 8 (see Figure 8), RTS is de-asserted. With trigger levels of 1, 4, and 8, the sending UART may send an additional byte after the trigger level is reached (assuming the sending UART has another byte to send) because it may not recognize the de-assertion of RTS until after it has begun sending the additional byte. RTS is automatically reasserted once the RX FIFO is emptied by reading the receiver buffer register. When the trigger level is 14 (see Figure 9), RTS is de-asserted after the rst data bit of the 16th character is present on the RX line. RTS is reasserted when the RX FIFO has at least one available byte space.
6.3.2 Auto-CTS
The transmitter circuitry checks CTS before sending the next data byte (see Figure 6). When CTS is active, it sends the next byte. To stop the transmitter from sending the following byte, CTS must be released before the middle of the last stop bit that is currently being sent (see Figure 7). The auto-CTS function reduces interrupts to the host system. When ow control is enabled, CTS level changes do not trigger host interrupts because the device automatically controls its own transmitter. Without auto-CTS, the transmitter sends any data present in the transmit FIFO and a receiver overrun error may result.
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SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
TX
Start
bits 0 to 7
Stop
Start
bits 0 to 7
Stop
Start
bits 0 to 7
Stop
CTS
002aaa049
(1) When CTS is LOW, the transmitter keeps sending serial data out. (2) If CTS goes HIGH before the middle of the last stop bit of the current byte, the transmitter nishes sending the current byte, but it does not send the next byte. (3) When CTS goes from HIGH to LOW, the transmitter begins sending data again.
Fig 7.
The receiver FIFO trigger level can be set to 1, 4, 8, or 14 bytes. These are described in Figure 8 and Figure 9.
RX
Start
byte N
Stop
Start
byte N + 1
Stop
Start
byte
Stop
RTS
IOR
N+1
002aaa050
(1) N = RX FIFO trigger level (1, 4, or 8 bytes). (2) The two blocks in dashed lines cover the case where an additional byte is sent as described in Section 6.3.1.
Fig 8.
SC16C550B_5
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SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
RX
byte 14
Start
byte 16
Stop
Start
byte 18
Stop
RTS
IOR
002aaa051
(1) RTS is de-asserted when the receiver receives the rst data bit of the sixteenth byte. The receive FIFO is full after nishing the sixteenth byte. (2) RTS is asserted again when there is at least one byte of space available and no incoming byte is in processing, or there is more than one byte of space available. (3) When the receive FIFO is full, the rst receive buffer register read re-asserts RTS.
Fig 9.
SC16C550B_5
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SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
XTAL1
XTAL2
XTAL1
XTAL2
1.5 k
X1 1.8432 MHz
X1 1.8432 MHz
C1 22 pF
C2 33 pF
C1 22 pF
C2 47 pF
002aaa870
The generator divides the input 16 clock by any divisor from 1 to (216 1). The SC16C550B divides the basic crystal or external clock by 16. The frequency of the BAUDOUT output pin is exactly 16 (16 times) the selected baud rate (BAUDOUT = 16 baud rate). Customized baud rates can be achieved by selecting the proper divisor values for the MSB and LSB sections of the baud rate generator. Programming the baud rate generator registers DLM (MSB) and DLL (LSB) provides a user capability for selecting the desired nal baud rate. The examples in Table 6 shows selectable baud rates when using a 1.8432 MHz crystal. For custom baud rates, the divisor value can be calculated using the following equation: XTAL1 clock frequency divisor ( in decimal ) = --------------------------------------------------------------serial data rate 16 (1)
SC16C550B_5
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SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
Baud rates using 1.8432 MHz or 3.072 MHz crystal Using 3.072 MHz crystal Baud rate error Desired baud Divisor for rate 16 clock 50 75 0.026 0.058 110 134.5 150 300 600 1200 1800 0.69 2000 2400 3600 4800 7200 9600 19200 38400 2.86 3840 2560 1745 1428 1280 640 320 160 107 96 80 53 40 27 20 10 5 1.23 0.628 0.312 0.026 0.034 Baud rate error
Table 6.
Using 1.8432 MHz crystal Desired baud Divisor for rate 16 clock 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 56000 2304 1536 1047 857 768 384 192 96 64 58 48 32 24 16 12 6 3 2
Table 8.
Effect of DMA mode on state of TXRDY pin DMA mode 1 = FIFO is full 0 = FIFO is empty
SC16C550B_5
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SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
SC16C550B_5
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SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
SC16C550B
TRANSMIT FIFO REGISTERS DATA BUS AND CONTROL LOGIC MCR[4] = 1 TRANSMIT SHIFT REGISTER
TX
RX
RTS DDIS
DSR OUT1
RI OUT2
DCD
002aaa587
XTAL1 RCLK
XTAL2 BAUDOUT
SC16C550B_5
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SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
7. Register descriptions
Table 9 details the assigned bit functions for the twelve SC16C550B internal registers. The assigned bit functions are more fully dened in Section 7.1 through Section 7.10.
Table 9. SC16C550B internal registers Register Default
[1]
A2 A1 A0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
General Register Set[2] 0 0 0 0 0 0 0 0 1 RHR THR IER XX XX 00 bit 7 bit 7 bit 6 bit 6 bit 5 bit 5 bit 4 bit 4 bit 3 bit 3 modem status interrupt RX trigger (MSB) FIFOs enabled divisor latch enable reserved RX trigger (LSB) FIFOs enabled reserved reserved DMA mode select[3] INT priority bit 2 parity enable OUT2[4] bit 2 bit 2 bit 1 bit 1 bit 0 bit 0 receive holding register
receive transmit line status holding interrupt register TX FIFO reset INT priority bit 1 stop bits
FCR
00
RX FIFO FIFO reset enable INT priority bit 0 word length bit 1 RTS INT status word length bit 0 DTR
ISR
01
LCR
00
set break set parity even parity auto ow loopback control enable transmit empty RI bit 6 bit 6 bit 14 transmit holding empty DSR bit 5 bit 5 bit 13 break interrupt CTS bit 4 bit 4 bit 12
MCR
00
OUT1[3]
LSR
60
1 1 0 0
[1] [2] [3] [4] [5]
1 1 0 0
0 1 0 1
X0 FF XX XX
Special Register
The value shown represents the registers initialized hexadecimal value; X = not applicable. These registers are accessible only when LCR[7] is set to a logic 0. These functions are not supported in the HVQFN32 package, and should not be written. OUT2 pin is not supported in the HVQFN32 package. The Special Register set is accessible only when LCR[7] is set to a logic 1.
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SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
7.1 Transmit Holding Register (THR) and Receive Holding Register (RHR)
The serial transmitter section consists of an 8-bit Transmit Holding Register (THR) and Transmit Shift Register (TSR). The status of the THR is provided in the Line Status Register (LSR). Writing to the THR transfers the contents of the data bus (D[7:0]) to the THR, providing that the THR or TSR is empty. The THR empty ag in the LSR register will be set to a logic 1 when the transmitter is empty or when data is transferred to the TSR. Note that a write operation can be performed when the THR empty ag is set (logic 0 = FIFO full; logic 1 = at least one FIFO location available). The serial receive section also contains an 8-bit Receive Holding Register (RHR). Receive data is removed from the SC16C550B and receive FIFO by reading the RHR register. The receive section provides a mechanism to prevent false starts. On the falling edge of a start or false start bit, an internal receiver counter starts counting clocks at the 16 clock rate. After 712 clocks, the start bit time should be shifted to the center of the start bit. At this time the start bit is sampled, and if it is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from assembling a false character. Receiver status codes will be posted in the LSR.
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SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
The receive data available interrupts are issued to the external CPU when the FIFO
has reached the programmed trigger level. It will be cleared when the FIFO drops below the programmed trigger level.
FIFO status will also be reected in the user accessible ISR register when the FIFO
trigger level is reached. Both the ISR register status bit and the interrupt will be cleared when the FIFO drops below the trigger level.
The data ready bit (LSR[0]) is set as soon as a character is transferred from the shift
register to the receive FIFO. It is reset when the FIFO is empty.
LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO. LSR[1:4] will provide the type of errors encountered, if any. LSR[5] will indicate when the transmit FIFO is empty. LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty. LSR[7] will indicate any FIFO data errors.
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SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
FCR[7] (MSB), RX trigger. These bits are used to set the trigger level for the receive FCR[6] (LSB) FIFO interrupt. An interrupt is generated when the number of characters in the FIFO equals the programmed trigger level. However, the FIFO will continue to be loaded until it is full. Refer to Table 12.
5:4 3
FCR[5] (MSB), not used; set to 00 FCR[4] (LSB) FCR[3] DMA mode select. logic 0 = set DMA mode 0 (normal default condition) logic 1 = set DMA mode 1 Transmit operation in mode 0: When the SC16C550B is in the 16C450 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode (FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are no characters in the transmit FIFO or transmit holding register, the TXRDY pin will be a logic 0. Once active, the TXRDY pin will go to a logic 1 after the rst character is loaded into the transmit holding register. Receive operation in mode 0: When the SC16C550B is in 16C450 mode, or in the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and there is at least one character in the receive FIFO, the RXRDY pin will be a logic 0. Once active, the RXRDY pin will go to a logic 1 when there are no more characters in the receiver. Transmit operation in mode 1: When the SC16C550B is in FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin will be a logic 1 when the transmit FIFO is completely full. It will be a logic 0 if the transmit FIFO is completely empty. Receive operation in mode 1: When the SC16C550B is in FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been reached, or a Receive Time-Out has occurred, the RXRDY pin will go to a logic 0. Once activated, it will go to a logic 1 after there are no more characters in the FIFO.
FCR[2]
TX FIFO reset. logic 0 = no FIFO transmit reset (normal default condition) logic 1 = clears the contents of the transmit FIFO and resets the FIFO counter logic (the transmit shift register is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO.
FCR[1]
RX FIFO reset. logic 0 = no FIFO receive reset (normal default condition) logic 1 = clears the contents of the receive FIFO and resets the FIFO counter logic (the receive shift register is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO.
FCR[0]
FIFO enable. logic 0 = disable the transmit and receive FIFO (normal default condition) logic 1 = enable the transmit and receive FIFO. This bit must be a 1 when other FCR bits are written to, or they will not be programmed.
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SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
RX trigger levels FCR[6] 0 1 0 1 RX FIFO trigger level (bytes) 1 4 8 14
Interrupt Status Register bits description Symbol ISR[7:6] Description FIFOs enabled. These bits are set to a logic 0 when the FIFO is not being used. They are set to a logic 1 when the FIFOs are enabled. logic 0 or cleared = default condition not used INT priority bits 2:0. These bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, and 3 (see Table 13). logic 0 or cleared = default condition INT status. logic 0 = an interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt service routine logic 1 = no interrupt pending (normal default condition)
5:4 3:1
ISR[5:4] ISR[3:1]
ISR[0]
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Symbol LCR[7]
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LCR[5] parity selection LCR[4] X 0 1 0 1 LCR[3] 0 1 1 1 1 Parity selection no parity odd parity even parity forced parity 1 forced parity 0
LCR[2] stop bit length Word length 5, 6, 7, 8 5 6, 7, 8 Stop bit length (bit times) 1 112 2
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MCR[1]
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Symbol LSR[7]
LSR[5]
LSR[4]
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Symbol MSR[7]
MSR[6]
MSR[5]
MSR[4]
MSR[3]
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8. Limiting values
Table 24. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD Vn Tamb Tstg Ptot/pack Parameter supply voltage voltage on any other pin ambient temperature storage temperature total power dissipation per package at D7 to D0 pins at any input only pin operating in free air Conditions Min VSS 0.3 VSS 0.3 40 65 Max 7 VDD + 0.3 5.3 +85 +150 500 Unit V V V C C mW
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9. Static characteristics
Table 25. Static characteristics Tamb = 40 C to +85 C; tolerance of VDD = 10 %, unless otherwise specied. Symbol VIL(clk) VIH(clk) VIL VIH VOL Parameter clock LOW-level input voltage clock HIGH-level input voltage LOW-level input voltage HIGH-level input voltage LOW-level output voltage on all outputs IOL = 5 mA (data bus) IOL = 4 mA (other outputs) IOL = 2 mA (data bus) IOL = 1.6 mA (other outputs) VOH HIGH-level output voltage IOH = 5 mA (data bus) IOH = 1 mA (other outputs) IOH = 800 A (data bus) IOH = 400 A (other outputs) ILIL IL(clk) IDD(AV) Ci Rpu(int)
[1]
[1]
Conditions
VDD = 2.5 V Min 0.3 1.8 0.3 1.6 1.85 1.85 Max +0.45 VDD +0.65 0.4 0.4 10 30 3.5 5 -
VDD = 3.3 V Min 0.3 2.4 0.3 2.0 2.0 500 Max +0.6 VDD +0.8 0.4 10 30 4.5 5 -
VDD = 5.0 V Min 0.5 3.0 0.5 2.2 2.4 500 Max +0.6 VDD +0.8 VDD 0.4 10 30 4.5 5 -
Unit V V V V V V V V V V V V A A mA pF k
LOW-level input leakage current clock leakage current average supply current input capacitance internal pull-up resistance f = 5 MHz
500
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Product data sheet Rev. 05 1 October 2008
NXP B.V. 2008. All rights reserved. SC16C550B_5
NXP Semiconductors
Table 26. Dynamic characteristics Tamb = 40 C to +85 C; tolerance of VDD 10 %, unless otherwise specied. Symbol tw1 tw2 fXTAL t4w t5s t5h t6s t6h t6s' t6h t7d t7w t7h t7h' t8d t9d t11d t12d t12h t13d t13w t13h t14d t15d t16s t16h t17d t18d t19d Parameter clock pulse duration clock pulse duration clock frequency address strobe width address setup time address hold time chip select setup time to AS address hold time address setup time chip select hold time IOR delay from chip select IOR strobe width chip select hold time from IOR address hold time IOR delay from address read cycle delay IOR to DDIS delay delay from IOR to data data disable time IOW delay from chip select IOW strobe width chip select hold time from IOW IOW delay from address write cycle delay data setup time data hold time delay from IOW to output delay to reset interrupt from IOR 25 pF load 25 pF load delay to set interrupt from Modem input 25 pF load 25 pF load 25 pF load 25 pF load 25 pF load
[3] [3] [1][2]
Conditions 15 15 45 5 5 10 0 10 0 10 25 pF load 77 0 5 10 20 10 20 0 10 25 20 15 -
Unit ns ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Table 26. Dynamic characteristics continued Tamb = 40 C to +85 C; tolerance of VDD 10 %, unless otherwise specied. Symbol t20d t21d t22d t23d t24d t25d t26d t27d t28d tRESET N
[1] [2] [3] [4] Rev. 05 1 October 2008
NXP B.V. 2008. All rights reserved.
SC16C550B_5
NXP Semiconductors
Parameter delay from stop to set interrupt delay from IOR to reset interrupt delay from start to set interrupt delay from IOW to transmit start delay from IOW to reset interrupt delay from stop to set RXRDY delay from IOR to reset RXRDY delay from IOW to set TXRDY delay from start to reset TXRDY RESET pulse width baud rate divisor
Conditions 25 pF load -
VDD = 2.5 V Min Max 1TRCLK 100 100 24TRCLK 100 1TRCLK 100 100 8TRCLK 216 1 -
Unit s ns ns s ns s ns ns s ns
8TRCLK [4]
8TRCLK 40 1
8TRCLK 40 1
100 1
Applies to external clock, crystal oscillator max 24 MHz. Maximum frequency = ------Applicable only when AS is tied LOW.
1 t w3
RESET pulse must happen when these signals are inactive: CS0 or CS1 or CS2 or CS, and IOW, IOR.
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5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
A0 to A2
active
DDIS t12d D0 to D7
002aaa331
A0 to A2
D0 to D7
data
002aaa332
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A0 to A2 t6s'
CS
active
IOR
D0 to D7
data
002aaa333
A0 to A2 t6s'
CS
active t13w
IOW
t16s
t16h
D0 to D7
data
002aaa334
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IOW
active t17d
RTS DTR
change of state
change of state
change of state
INT
active
active
IOR
active t18d
active
RI
change of state
002aaa347
tw1
002aaa112
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start bit
data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7
parity bit
stop bit
RX
5 data bits 6 data bits 7 data bits INT t20d active t21d active
IOR
start bit
data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7
parity bit
stop bit
RX
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start bit
data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7
parity bit
stop bit
RX
start bit
data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7
parity bit
stop bit
TX
5 data bits 6 data bits 7 data bits INT t22d t23d IOW active active transmitter ready t24d active
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start bit
data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7
parity bit
stop bit
TX
IOW
active
D0 to D7
byte #1
t28d
start bit
data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7
parity bit
stop bit
TX
5 data bits 6 data bits 7 data bits IOW active t28d D0 to D7 byte #16 t27d
TXRDY
FIFO full
002aab061
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seating plane
ME
A2
A1 c Z e b1 b 40 21 MH w M (e 1)
pin 1 index E
20
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.7 0.19 A1 min. 0.51 0.02 A2 max. 4 0.16 b 1.70 1.14 0.067 0.045 b1 0.53 0.38 0.021 0.015 c 0.36 0.23 0.014 0.009 D
(1)
(1)
e 2.54 0.1
e1 15.24 0.6
w 0.254 0.01
Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT129-1 REFERENCES IEC 051G08 JEDEC MO-015 JEITA SC-511-40 EUROPEAN PROJECTION
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SOT187-2
eD y X A ZE
eE
39
29 28
bp
40
b1 w M 44 HE A e A4 A1 (A 3) k 7 e D HD 17 ZD B v M B v M A 6 18 Lp detail X
1
pin 1 index
5 scale
10 mm
DIMENSIONS (mm dimensions are derived from the original inch dimensions) A4 A1 e UNIT A A3 D(1) E(1) eD eE HD bp b1 max. min.
mm inches 4.57 4.19 0.51 0.25 0.01 3.05 0.12 0.53 0.33 0.81 0.66
HE
Lp
1.44 1.02
v
0.18
w
0.18
y
0.1
16.66 16.66 16.00 16.00 17.65 17.65 1.22 1.27 16.51 16.51 14.99 14.99 17.40 17.40 1.07 0.63 0.59 0.63 0.59
45 o
0.695 0.695 0.048 0.057 0.007 0.007 0.004 0.085 0.085 0.685 0.685 0.042 0.040
Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT187-2 REFERENCES IEC 112E10 JEDEC MS-018 JEITA EDR-7319 EUROPEAN PROJECTION
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LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
y X
36 37
25 24 ZE
E HE
A A2
A1
(A 3) Lp L detail X
w M pin 1 index 48 1 12 ZD bp D HD w M B v M B v M A 13 bp
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 7.1 6.9 E (1) 7.1 6.9 e 0.5 HD 9.15 8.85 HE 9.15 8.85 L 1 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 0.95 0.55 0.95 0.55 7 o 0
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT313-2 REFERENCES IEC 136E05 JEDEC MS-026 JEITA EUROPEAN PROJECTION
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HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm
SOT617-1
A A1 c
detail X
e1 e 9 L 8 17 e
1/2 e
C b 16 v M C A B w M C y1 C y
Eh
1/2 e
e2
24 32 Dh 0 2.5 scale E (1) 5.1 4.9 Eh 3.25 2.95 e 0.5 e1 3.5 e2 3.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 5 mm 25 X
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 5.1 4.9 Dh 3.25 2.95
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT617-1 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-18
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Through-hole components Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature prole. Leaded packages, packages with solder balls, and leadless packages are all reow solderable. Key characteristics in both wave and reow soldering are:
Board specications, including the board nish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
Process issues, such as application of adhesive and ux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
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Lead-free versus SnPb soldering; note that a lead-free reow process usually leads to
higher minimum peak temperatures (see Figure 28) than a SnPb process, thus reducing the process window
Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
Reow temperature prole; this prole includes preheat, reow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classied in accordance with Table 27 and 28
Table 27. SnPb eutectic process (from J-STD-020C) Package reow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 28. 235 220 Lead-free process (from J-STD-020C) Package reow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reow soldering, see Figure 28.
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temperature
peak temperature
time
001aac844
For further information on temperature proles, refer to Application Note AN10365 Surface mount reow soldering description.
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Suitability of through-hole mount IC packages for dipping and wave soldering Soldering method Dipping suitable Wave suitable suitable[1] not suitable
For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. For PMFP packages hot bar soldering or manual soldering is suitable.
14. Abbreviations
Table 30. Acronym CMOS CPU DLL DLM DMA FIFO ISDN LSB MSB TTL UART Abbreviations Description Complementary Metal-Oxide Semiconductor Central Processing Unit Divisor Latch LSB Divisor Latch MSB Direct Memory Access First-In, First-Out Integrated Service Digital Network Least Signicant Bit Most Signicant Bit Transistor-Transistor Logic Universal Asynchronous Receiver and Transmitter
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changed all occurrences of VCC to VDD Section 2 Features: added new 7th bullet (and footnote) Table 2 Pin description: Description for signal DDIS changed from DDIS is active (LOW) when the CPU is not reading data. When active, DDIS can disable an external transceiver. to DDIS is active (LOW) when the CPU is reading data. When inactive (HIGH), DDIS can disable an external transceiver. Figure 6 Autoow control (auto-RTS and auto-CTS) example: changed ACE1 to UART 1; changed ACE2 to UART 2 changed RCVR to RX changed XMIT to TX
Section 7 Register descriptions, rst paragraph: changed from ... for the fteen SC16C550B internal registers. to ... for the twelve SC16C550B internal registers. Table 9 SC16C550B internal registers: changed MCR bit 3 from OUT2, INT enable to OUT2 Table 19 Modem Control Register bits description: description of MCR[3] re-written (removed reference to INT enable) description of MCR[4]: changed TX to TX and changed RX to RX
SC16C550B_4 SC16C550B_3 (9397 750 14986) SC16C550B-02 (9397 750 14446) SC16C550B-01 (9397 750 11967)
Table 24 Limiting values: symbol Vn split to show 2 separate conditions: at D7 to D0 pins and at input only pins Table 25 Static characteristics: deleted (old) Table note [2] and its reference at Rpu(int) Table 26 Dynamic characteristics: added Table note [4] and its reference at tRESET updated soldering information Product data sheet Product data sheet Product data Product data SC16C550B_3 SC16C550B-02 SC16C550B-01 -
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Denition This document contains data from the objective specication for product development. This document contains data from the preliminary specication. This document contains the product specication.
Please consult the most recently issued document before initiating or completing a design. The term short data sheet is explained in section Denitions. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
16.2 Denitions
Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales ofce. In case of any inconsistency or conict with the short data sheet, the full data sheet shall prevail.
malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specied use without further testing or modication. Limiting values Stress above one or more limiting values (as dened in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/prole/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
16.3 Disclaimers
General Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
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5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
18. Contents
1 2 3 4 5 5.1 5.2 6 6.1 6.2 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.4 6.5 6.6 6.7 7 7.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . . 9 Internal registers. . . . . . . . . . . . . . . . . . . . . . . 10 FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . 10 Autoow control . . . . . . . . . . . . . . . . . . . . . . . 11 Auto-RTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Auto-CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Enabling autoow control and auto-CTS . . . . 12 Auto-CTS and auto-RTS functional timing . . . 12 Hardware/software and time-out interrupts. . . 13 Programmable baud rate generator . . . . . . . . 14 DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 15 Loopback mode . . . . . . . . . . . . . . . . . . . . . . . 16 Register descriptions . . . . . . . . . . . . . . . . . . . 18 Transmit Holding Register (THR) and Receive Holding Register (RHR) . . . . . . . . . . . . . . . . . 19 7.2 Interrupt Enable Register (IER) . . . . . . . . . . . 19 7.2.1 IER versus Receive FIFO interrupt mode operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.2.2 IER versus Receive/Transmit FIFO polled mode operation . . . . . . . . . . . . . . . . . . 20 7.3 FIFO Control Register (FCR) . . . . . . . . . . . . . 20 7.3.1 DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.3.1.1 Mode 0 (FCR bit 3 = 0) . . . . . . . . . . . . . . . . . . 20 7.3.1.2 Mode 1 (FCR bit 3 = 1) . . . . . . . . . . . . . . . . . . 20 7.3.2 FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.4 Interrupt Status Register (ISR) . . . . . . . . . . . . 22 7.5 Line Control Register (LCR) . . . . . . . . . . . . . . 23 7.6 Modem Control Register (MCR) . . . . . . . . . . . 25 7.7 Line Status Register (LSR) . . . . . . . . . . . . . . . 26 7.8 Modem Status Register (MSR). . . . . . . . . . . . 27 7.9 Scratchpad Register (SPR) . . . . . . . . . . . . . . 28 7.10 SC16C550B external reset conditions . . . . . . 28 8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 28 9 Static characteristics. . . . . . . . . . . . . . . . . . . . 29 10 Dynamic characteristics . . . . . . . . . . . . . . . . . 30 10.1 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 32 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 38 12 Soldering of SMD packages . . . . . . . . . . . . . . 42 12.1 Introduction to soldering . . . . . . . . . . . . . . . . . 42 12.2 12.3 12.4 13 13.1 13.2 13.3 13.4 14 15 16 16.1 16.2 16.3 16.4 17 18 Wave and reow soldering . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Reow soldering. . . . . . . . . . . . . . . . . . . . . . . Soldering of through-hole mount packages . Introduction to soldering through-hole mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . Soldering by dipping or by solder wave . . . . . Manual soldering . . . . . . . . . . . . . . . . . . . . . . Package related soldering information . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Denitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 42 43 44 44 44 44 45 45 46 47 47 47 47 47 47 48
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 1 October 2008 Document identifier: SC16C550B_5