IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO.

6, JUNE 2010

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Digital Average Current-Mode Control Using Current Estimation and Capacitor Charge Balance Principle for DCDC Converters Operating in DCM
Ying Qiu, Xiyou Chen, and Helen Liu
AbstractA new digital average current-mode control technique is proposed for dcdc converters operation in discontinuous conduction mode. In contrast to the regulation of inductor current, this paper focuses on how the suitable charge current is feed to capacitor and load resistor directly. Using the principle of capacitor charge balance, the charge current reference in next switching cycle is predicted in order to drive the output voltage back to its nominal value quickly during transient conditions. The actual average charge current is estimated from a simplied algorithm, which can also be used to calculate the required duty ratio according to the charge current reference. This control technique features good dynamic performance and it is compliant with the performance constraints of digital integrated processor. The effectiveness of the proposed solution has been proved by the simulation and experimental results. Index TermsAverage current estimation, capacitor charge balance principle, dcdc converter, digital control, discontinuous conduction mode (DCM).

I. INTRODUCTION

OWADAYS, there is a trend toward fully digital control of dcdc converters [1][11]. Among the various advantages of digital approach, fast dynamic performance under load or input voltage change is the most valuable. Improvements in dynamic performance usually not only result in a substantial reduction of the size and weight of the power stage lter components, but also reduce voltage and current stress on downstream converters and provide more reliable operation of the supplied equipment. One approach to optimize dynamic performance is to use the digital current-mode control, which maintains the inductor current equal to a reference based on the feedback from current sensor [12][15]. With reference [12], they demonstrated that inductor current in next switching cycle can be predicted in continuous conduction mode (CCM) and can be used to improve dynamic response by employing linear extrapolation. However, since the linear extrapolation is accurate only when using the

Manuscript received June 26, 2009; revised September 20, 2009 and October 27, 2009. Current version published June 3, 2010. This work was supported by the National Natural Science Foundation of China under Grant 50877007. Recommended for publication by Associate Editor P. Mattavelli. Y. Qiu and X. Chen are with the Department of Electrical and Electronics Engineering, Dalian University of Technology, Dalian 116023, China (e-mail: ying.qiu@mail.dlut.edu.cn; chenxy@dlut.edu.cn). H. Liu is with the Faculty of Engineering and Physical Sciences, University of Surrey, Guildford, Surrey GU2 5XH, U.K. (e-mail: liu.h@surrey.ac.uk). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TPEL.2010.2040089

same duty ratio as in the previous switching cycle, the duty ratio can be updated only once in every two switching cycles. As a solution, a predictive digital-current-programmed control algorithm has been proposed [13]. The duty ratio for the next switching cycle is calculated ahead of time based on geometric relation of current waveform, such that the error of the controlled variable is minimized in the next several cycles. Moreover, with the similar principle, extensive work has been conducted, in terms of mimic current-mode control [14], small-signal modelbased control [15], etc. Although the current control methods have been well studied, there still have a number of works to do to improve dynamic performance, since the bandwidth of aforementioned works was limited by voltage control methods. For a given converter topology, there exists a time-optimal response that can be obtained in CCM by using the capacitor charge balance principle [16][22]. It is demonstrated in [23] that by employing a linear control scheme during steady-state conditions and a capacitor charge balance control scheme during load transient, the dynamic response can be signicantly improved. This method requires to implement the complex computations and also relies on precise real-time inductor current sensing. The approach presented in [24] also combines a linear PID controller with a near-time-optimal controller in transients. Based on detecting the valley (or peak) in the output voltage waveform, the duty ratio is chosen and stored in a lookup table. This approach has advantages of requiring no current sensing and having a relative simple realization based on continuoustime DSP. Although the methods described in previous papers worked well on buck converter, no attempt has been made to extend the study to other basic converters. This is probably due to the right-half-plane (RHP) zero in boost and buckboost converters, which induce the algorithm to unstable region. In general, CCM operation is preferred for large current applications, because it can deliver more current than the converter operating in discontinuous conduction mode (DCM). However, a DCM converter usually has a much faster transient response and a loop gain that is easier to compensate than a CCM converter. To benet from the attractive feature in DCM, there are some works that have proposed predictive current control techniques to generate the digital control signal [25], [26]. In [25], the strategy ignore the parasitics and try to estimate the required duty ratio based on the samples of the voltage signals, in order to make the average inductor current to track the input control signal. However, the potential for improvement in dynamic performance of this control technique has not been exploited, since the voltage compensator was omitted in related literature.

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Motivated by the aforementioned research activities, this paper proposes a new current-mode control technique for dcdc converters operating in DCM. The basic idea of this control scheme is to predict the desired average charge current in next switching cycle based on the capacitor charge balance principle, so that the output voltage will track the voltage reference. The duty ratio for the next switching cycle is calculated to enable the practical average charge current to follow its desired value. The algorithm is implemented using estimated current information instead of sampled current to eliminate the requisite for a costly current-sensing circuit. Moreover, the realization of the proposed control technique is considered in three basic converters, including the boost, the buck, and the buckboost converters. This control technique can be widely used in a range of dcdc applications, such as distributed power system, high-end display, and lighting equipments. The experimental results have demonstrated that the proposed control technique can enable high dynamic performance without current sensor. II. CONTROL METHOD In this paper, the design methodology for both current and voltage control methods are discussed. The goal of the proposed current control method is to nd out the duty ratio in order that the average capacitor charge current follows the desired value, which might be the output of the voltage controller. The voltage control method is based on the approach of using the sampled input and output voltages to calculate charge current reference in next switching cycle, so that the difference between charge current and output current can charge the capacitor to voltage reference in few switching cycles. Without loss of generality, we assume that the sample is obtained by sampling the input and output voltages at the beginning of the switching cycle. In all work in this section, the boost converter is used as an example. The results are extended to other basic converters in Section III. A. Current Estimation and Control Technique As mentioned in [27] and [28], the parasitic resistance in converter leads to nonlinear inductor current waveform and signicantly complicates the computational process. To satisfy the resources constraint of digital controller, a simplied algorithm is developed to derive approximate charge current without exponential calculation. Fig. 1 depicts a boost converter with the proposed digital average current-mode controller, where equivalent serial resistance (ESR) of inductor and capacitor are considered as RL and RC , respectively. RDS denotes the MOSFET ON-state resistance, VF denotes the threshold voltage of diode, and RF denotes the forward resistance of diode. iL and iR are inductor current and charge current, respectively. iO is output current. The inductor current can be simply approximated by a ramp in CCM, since the inductor time constant is signicantly larger than the switching cycle. However, for a DCM converter to supply the same load current, a smaller value of inductor has to be used, and the inductor time constant decreases from that of the CCM converter. This situation has become even more critical, given

Fig. 1. Basic diagram of the digital control architecture applied to a boost converter.

Fig. 2.

Ideal, actual, and approximate inductor current waveforms for DCM.

the recent technique trend to regulate inductor current sharply during transient. Therefore, it is reasonable to investigate the exact nonlinear behavior of inductor current while operating in DCM. The typical waveforms of the current passing through the inductor during a single switching cycle are shown in Fig. 2. In Fig. 2, D1 and D2 actual denote the duty ratio of the actual rst and the second subintervals, respectively. iP is actual peak current, and T is switching cycle. As it can be seen that, in the presence of parasitic resistance, the actual inductor current (solid line) deviates from its ideal waveform (dotted line) due to the curvature of the current waveform in each subinterval. Therefore, to capture actual current waveform, the actual peak current iP and actual second duty ratio D2 actual should be derived. Since the input and output voltages are assumed constant during current switching cycle, the state equation of the circuit can be expressed for the rst subinterval as follows: diL + (RL + RDS ) iL = VI . (1) dt From there, the actual inductor current in the rst subinterval can be found as follows: VI (1 e(R L +R D S )t/L ). (2) iL = RL + RDS L To avoid the exponential calculation, the Tustins transformation method that can be expressed as est (2 + st)/(2 st) is adopted. Therefore, actual peak current can be approximated

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by setting t = D1 T iP 2L VI D1 T . L 2L + (RL + RDS )D1 T (3)

To nd actual second duty ratio, some geometric analysis has been performed. As schematically depicted in Fig. 2, once i represents the error between actual current and modied current at the end of the second subinterval, then it can be approximated as follows:
D2 actu al T

i =
0

(RL + RF ) iL dt L

RL + RF iP D2 actual T. (4) 2L However, using the triangular relation in Fig. 2, i can also be expressed as follows: i = D2 m o died D2actual iP . D2 m o died (5)

charge current predicted by voltage controller. Applying this duty ratio to the converter in next switching cycle makes the average charge current to follow the current reference. There is always a design tradeoff between system performance and complexity. Although, the proposed current control method involves relatively complex arithmetic computations (such as division and square-root calculations), the estimated nonlinear current information enable the controller to regulate the charge current sharply without any costly current-sensing circuit. Such advantage of estimating nonlinear inductor current can compensate the computational complexity to a certain extent. Moreover, in actual implementation, the computationally intensive arithmetic operations can be performed using lookup tables in order to comply with the performance constraints of low-end processor. B. Predictive Voltage Control Technique In this section, a new predictive voltage control technique based on capacitor charge balance principle was designed. According to the capacitor charge balance principle, the charge current should uctuate and reach the output current at the exact moment that the charge delivered to the capacitor equals the charge removed from the capacitor. This condition must be satised in order for the output voltage to recover from a transient in minimal time. The objective of the proposed control method is to ensure the immunity of output voltage to various disturbances. For this reason, the desired charge current for next switching cycle is predicted based on the sampled output voltage and the estimated current. From the viewpoint of voltage controller, since duty ratio can be accurately calculated according to current reference, the current controller, inductor, and switching component may be well considered as controlled current sources. The resulting diagram is shown in Fig. 3(a). IR (k) shows average charge current over kth switching cycle, while VO (k) and VI (k) show the output and input voltages sampled at the beginning of kth switching cycle, respectively. By applying the capacitor charge balance principle, the output current in previous switching cycle can be estimated as follows: IO (k 1) = IR (k 1) C [VO (k) VO (k 1)] T (12)

Therefore, based on (4) and (5), the actual second duty ratio is given by D2 actual = 2LD2 m o died 2L + (RL + RF ) D2 m o died T (6)

where D2 m o died denotes the modied second duty ratio, which can be determined by D2 m o died = LiP . (VO + VF VI ) T (7)

It is worth noticing that, the charge current (shown as shade area in Fig. 2.) is being ltered and delivered to load, and thus, the average value of charge current is indeed the output current. By combining (3), (6), and (7), the average charge current in one switching cycle can be approximated as follows: IR
2 2 T f2 VI2 D1 f1 ip D2 actual = 2 2L VO + VF VI

(8)

where f1 and f2 represent correction factors related to parasitic resistance, and can be written as follows: f1 = f2 = 2L 2L + (RL + RDS ) D1 T 2L . 2L + (RL + RF ) D2 m o died T (9) (10)

One can also obtain the duty ratio by solving (8) as follows: D1 = 2L 1 T f2 VI f1 IR (VO + VF VI ). (11)

For a digital controller, (8) can be used as a new method to estimate the approximate average charge current. Equation (11) is used to calculate the required duty ratio in such a way that the average charge current follows the current reference. Thus, at the beginning of each switching cycle, the average charge current is estimated using sampled voltage and the duty ratio and feed to voltage controller. Then, by knowing the dynamic of the converter (11), the required duty ratio for the next switching cycle is calculated based on the sampled voltage and desired

where IO (k 1) is average output current over (k 1) th switching cycle. Equation (12) is used to detect the output current based on estimated average charge current and sampled output voltage. Using the same principle, the sampled output voltage in next switching cycle is predicted as follows: VO (k + 1) = VO (k) + T [IR (k) IO (k)] . C (13)

In principle, the voltage error could be completely canceled by choosing suitable charge current. In this application, to ensure that the charge delivered to the capacitor is equal to the charge delivered by the capacitor at the beginning of alternately switching cycle, shown as VO (k + 2) = Vref , we regulate

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C. Robustness In this section, the robustness of proposed algorithm against parameter variations is analyzed. For such purpose, let us dene I as the estimated value of current I. Moreover, the load is also considered as a constant current source. This assumption is motivated by the fact that ac component of charge current has been well ltered by capacitor. Thus, we discuss how tolerances in the parameters affect the control performance, according to voltage and current control methods, respectively. 1) Robustness of Voltage Control Method: The robustness of the voltage control method is mainly affected by capacitor. To facilitate the derivation, the aforementioned corrected voltage control law shown in (17) can be rearranged as follows: IR (k + 1) = C Vref RC IO (k 1) + RC IO (k) 3VO (k) T + 2VO (k 1) + 2IR (k 1) IR (k). (18)

Fig. 3. (a) Simplied digital control architecture applied to converter. (b) Voltage and current waveforms for boost converter.

desired charge current in next switching cycle as follows: C [Vref VO (k + 1)] . (14) T Equation (14) can be used to compensate the output current as well as charge error in capacitor. We are here implicitly assuming that, after an abrupt disturbance, the uctuation of output current is much smaller than that of charge current, a condition usually satised provided that the voltage uctuation, which is proportional to output current uctuation, is minimized by the charge current regulated sharply. In this case, the output current difference between current and adjacent switching cycles is neglected by setting IO (k) = IO (k 1). Therefore, combining (12)(14), one can obtain the voltage control law for proposed predictive voltage control as follows: C IR (k + 1) = [Vref 3VO (k) + 2VO (k 1)] T (15) + 2IR (k 1) IR (k) IR (k + 1) = IO (k + 1) + where IR (k 1) and IR (k) are average charge currents estimated by current-estimation algorithm mentioned before, while IR (k + 1) is charge current reference. Up to this point, we considered that the sampled voltage is ideal capacitor voltage. However, special care has to be taken for actual converters that have capacitor ESR in it. As shown in Fig. 3(b), the difference between iO and iR will produce some error in actual instantaneous voltage vO from ideal capacitor voltage VO . The major drawback of the discrepancy is that it introduces a residual error in output voltage by sampling at the beginning of switching cycle. To solve this problem, the ideal sampled voltage should be corrected to obtain actual sampled voltage, which is dened as follows: VO A (k) = VO (k) RC IO (k). (16) Considering IO (k) = IO (k 1), and substituting (16) into (15), the corrected voltage control law can now be obtained as follows: C Vref RC IO (k 1) 3VO A (k) IR (k + 1) = T + 2VO A (k 1) + 2IR (k 1) IR (k). (17)

Suppose there is no error in current estimation and control. Taking into account the mismatch factor of assumed capacitor value C, we denote the actual capacitor value as (1 + ) C. In this case, by applying (1 + ) C in (12), the actual charge current is written as follows: (1 + )C [VO (k) VO (k 1)] . T (19) The estimated output current is given by the following equation using (12) and (19) as: IR (k 1) = IO (k 1) + C [VO (k) VO (k 1)] . (20) IO (k 1) = IO (k 1) + T It should be noted that since the C/T multiplier in the front of (18) represents constant gain in controller, the actual varied capacitor value has no inuence on it. Substituting (19) and (20) into (18) and rearranging the terms gives E (k + 2) = 3T CRC E (k) T 1+ 2T CRC E (k 1) T 1+

(21)

where E (k) = Vref V (k) . (22)

The robustness analysis of the algorithm can be approximately performed by applying the Z-transform to (21) and deriving the roots of the expression. If the magnitude of the root is equal to or greater than one, then the resulting system is unstable. A 3-D plot of versus RC with C/T , the ratio of capacitor and switching cycle, on the third axis is shown in Fig. 4. shows maximum absolute value of mismatch factor, which guarantees that the magnitude of all the roots in (21) are less than one. It is clear in Fig. 4 that the presence of RC has the advantage to enhance the robustness. Since RC is parasitic, which cannot be set articially, one can choose a large capacitor to enlarge robustness range. It is worth pointing out that, in DCM, the large capacitor is always been designed to minimize

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Fig. 5.

General sketch of three basic converters.

the voltage error at the beginning of the (k + 2) th switching cycle is found as follows: E (k + 2) =
Fig. 4. Plot of mismatch factor absolute value versus R C and ratio of capacitor and switching cycle C /T .

CRC 3T CRC 2T E (k) E (k 1) T T RC IO (k). (26)

voltage ripple. Therefore, the well-designed converter naturally satises the demand of robustness. Next, let us suppose that there is an error or an offset in capacitor ESR. Thus, the actual capacitor ESR can be expressed using mismatch factor and assumed value as (1 + ) RC . From (17), the resulting voltage control law is given by IR (k + 1) = C Vref RC IO (k 1) + (1 + ) RC IO (k) T 3VO (k) + 2VO (k 1) + 2IR (k 1) IR (k). (23)

Substituting (12) into (23) results in a constant offset in the output voltage E = RC IO . (24)

As we can observe from the rst and second terms in (26), the mismatch factor in current estimation and control gives a very similar performance, as shown in (21). Therefore, in order to ensure that the error decreases with time, we should have a large capacitor. This condition is not difcult to meet in a welldesigned converter in DCM. Thus, the proposed solution can guarantee the control performance, which is not signicantly affected by current estimation and control error. The third term is responsible for a constant voltage error. The steady-state error can be written as follows: RC IO . (27) E= 1+ In conclusion, the proposed voltage and current control methods are relatively immune to parameters tolerances. III. EXTENSIONS TO OTHER CONVERTERS In this section, basic principle of proposed digital average current-mode control can be easily extended to other basic converters, i.e., the buck converter and the buckboost converter. Fig. 5 shows the general sketch of three basic converters. The only difference between the boost converter and the other basic converters is that the former employs the inductor in series with voltage source, whereas corresponding components in different positions are used in the latter. Therefore, the average charge current can be generally expressed as a function of the actual peak current, the duty ratio, and the actual second duty ratio. For the basic nonisolated converters, the current waveform parameters are given in Table I. By using the expressions for iP and D2 actual from Table I, we obtain the following average charge current for the buck converter, (28) as shown at the bottom of the next page. Equation (28) can be solved for the duty ratio as follows: D1 = 2L T f1 1 VI VF VO IR (VO + VF ) (VI VF VO ) . (VO + VF ) + f1 f2 (VI VF VO ) (29)

Therefore, the output voltage will be slightly different from the reference because of the mismatch of RC . However, for a well-designed converter, the product of and RC is very small and in most cases, the offset can be ignored. 2) Robustness of Current Estimation and Control Method: The proposed current estimation and control method require the value of inductor and other parasitics. Since it is common for such parameters to have initial tolerances and to be further affected by changes in temperature or aging, the algorithm robustness must be assessed in order to characterize its range of stability. Neglecting the error between assumed value and actual value of C and RC , we thus assume that there is no error in voltage control. In this simplied case, the voltage control law using estimated average charge current can be rewritten as follows: C Vref RC IO (k 1) + RC IO (k) 3VO (k) IR (k + 1) = T + 2VO (k 1) + 2IR (k 1) IR (k) (25) where the estimated average charge current IR (k) can be expressed using mismatch factor and actual value as IR (k)/(1 + ). The similar analysis approach used for voltage control can also be used for current control. Based on (25),

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TABLE I CURRENT WAVEFORM PARAMETERS IN BASIC CONVERTERS

Equations (28) and (29) give the basic current estimation and control method for the buck converter. Using the similar approach, the average charge current for the buckboost converter can be derived as follows: IR
2 2 T f2 VI2 D1 f1 ip D2 actual = . 2 2L VO + VF

(30)
Fig. 6. Charge current resulting from increasing the second duty ratio. (a) Detailed simulation. (b) Ideal estimation method [25]. (c) Proposed estimation method. (d) Corrected estimation method [27].

From (30), the duty ratio can be expressed as follows: D1 = 2L 1 T f2 VI f1 IR (VO + VF ). (31)

Since the predictive voltage control technique is independent of circuit topology, the control law mentioned in (15) is valid for all basic converters. Moreover, the robustness conditions, which were discussed in Section II for the boost converter, apply to all basic converters operating in DCM. IV. SIMULATION AND EXPERIMENTAL RESULTS Simulation and experiment were performed to verify the effectiveness of the proposed digital average current-mode control technique. The parameters of the boost converter are listed as follows: L = 4.25 H, C = 48 F, RL = 0.07 , RC = 0.11 , RDS = 0.2 , RF = 0.1 , VF = 0.36 V, f = 100 kHz, VO = 12 V, VI = 6 V, and R = 30 . First, the effectiveness of current estimation method has been veried. In the following study, the controlled boost converter initially operates in a steady state. Then, the input voltage increases linearly from 6 to 11 V and the load resistor reduces linearly from 30 to 6 . In this case, to maintain the output voltage, the duty ratio will be chosen by controller to enlarge second duty ratio from 0.22 to 0.82. As shown in Fig. 6, three current estimation methods that are used to calculate the average value of charge current (line a) have been simulated and compared. The ideal estimation method [25], which ignores the parasitics in the converter, results in relatively large offset (line b). The improvement can be obtained from both proposed estimation method (line c) and corrected estimation method [27] (line d). Since the exponential calculation is substituted by simplied algorithm, the proposed method can save processor resource and is more competitive in digital implement.

To verify the superior transient response, the proposed algorithm was compared with a digitally implemented voltage-mode PI controller with an approximate system bandwidth of 16 kHz. The simulation was performed under the similar condition, as mentioned in literature [22] and [24]. In this condition, the step disturbance occurred immediately before the beginning of the switching cycle. Figs. 7 and 8 show a voltage-mode-controlled converter and the proposed controller undergoing step load resistor change (30 20 30 ), respectively. The disturbance time is denoted as a dotted line. Simulation results show that the proposed controller results in better load transient response. It can be observed that with the proposed method, the inductor current quickly contributes a spike or valley to charge the capacitor, and then, soon achieve to new steady-state value and nish the transient response in only three switching cycles. With PI controller, the inductor current is slightly above the new steady-state value and the recovery of the output voltage is much slower. It is also demonstrated through simulation that the proposed algorithm reacts to the load resistor change with two skipped switching cycles. This phenomenon is seen because of delays introduced by output current estimation and duty-ratio update. However, such nonideal character is considered in our design methodology by regulating the output voltage in alternately switching cycle and applying the capacitor charge balance principle. Thus, the inevitable delay does not affect the stability of the proposed algorithm. Fig. 9 reports the dynamic behavior of the converter with the proposed controller undergoing step input voltage change (6 V 9 V 6 V). In this case, since the disturbance of input

IR

2 2 T f1 (VO + VF ) (VI VF VO ) D1 + (VI VF VO )2 D1 f1 f2 ip (D1 + D2 actual ) = . 2 2L VO + VF

(28)

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Fig. 7. Simulated result of voltage-mode PI controller response to a 30 20 30 load resistor step change. (Top) Output voltage. (Bottom) Inductor current.

Fig. 9. Simulated result of proposed controller response to a 6 V9 V6 V input voltage step change. (Top) Output voltage. (Bottom) Inductor current.

Fig. 8. Simulated result of proposed controller response to a 30 20 30 load resistor step change. (Top) Output voltage. (Bottom) Inductor current.

Fig. 10. Simulated result of proposed controller response to a 30 20 load resistor step change with incorrect capacitor information. (Top) Output voltage. (Bottom) Inductor current.

voltage can be directly sampled, the controller is able to react to the input voltage change at the next switching cycle. It is shown that the inductor current exceeds the load current to make up for the capacitor charge and returns to the new steady state, once the output voltage is equal to voltage reference. Since the voltage-mode counterpart based on feedback loop cannot attain superior performance during input voltage disturbance, its simulation result is omitted here. As shown in Figs. 79, the waveforms of output voltage are the results of ripple current owing through the capacitor and its ESR. For constant input voltage, the higher load resistor leads to lower ripple charge current, and consequently, lower ripple output voltage. For constant load resistor, although the average charge current is constant, ripple charge current decreases for higher input voltage. However, in steady state, the output voltage averaged over one switching cycle reaches its voltage reference and is independent from the operating point.

As mentioned before, the stability of proposed control method relies on parameters tolerance. Considering that the inuence of parameter variations on capacitor gives a similar performance as that of inductor and parasitics, only a representative simulation was conducted to verify the robustness of the proposed algorithm under different capacitor values. By substituting the simulation parameters into (21), the maximum absolute value of mismatch factor can be approximately derived as 24%. In order to approach tolerance threshold and consider a typical component tolerance, the capacitor was varied by 20%. Fig. 10 illustrates the dynamic behavior of the converter, following step load resistor change when the capacitor information is incorrect. It can be observed from Fig. 10 that the voltage and current suffer transient oscillation due to unsuitable charge current regulated by voltage controller. This may result in a few extra switching cycles before the transient settles. However, the response of the converter is still accurate and fast. Therefore, it

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Fig. 11. Experimental result of proposed controller response to load resistor step change from 20 to 30 . (Top) Output voltage. (Bottom) Inductor current.

Fig. 13. Experimental result of proposed controller response to input voltage step change from 6 to 9 V. (Top) Output voltage. (Bottom) Inductor current.

Fig. 12. Experimental result of proposed controller response to load resistor step change from 30 to 20 . (Top) Output voltage. (Bottom) Inductor current.

Fig. 14. Experimental result of proposed controller response to input voltage step change from 9 to 6 V. (Top) Output voltage. (Bottom) Inductor current.

can be concluded that poorly dened parameters will degrade performance slightly, but still allow the algorithm to function. A prototype was constructed in order to experimentally test the dynamic performance of the proposed control method. The boost converter parameters are identical to that of the simulation. The control algorithm was implemented in a TMS320F2812 DSP system. In the experiment, a 12-bit A/D converter integrated in DSP is used to sense the input and output voltages. In general, although the A/D converter must have a ne voltage resolution to maintain the ability to regulate the output voltage precisely, the proposed algorithm can also be implemented in the system with low-resolution A/D converter. In this case, a dead zone with constant threshold could be introduced. The dead zone can avoid incorrect regulation due to sampling noise and quantization noise, while caused minor inaccuracies in the algorithms operation. The similar experimented tests with sudden variations in the load resistor or the input voltage have been made. The voltage and current waveforms of interest were obtained using a twoinput oscilloscope. The oscilloscope was triggered by the same step signal used to disturb the converter. Figs. 11 and 12 depict

the dynamic behavior of the converter with the proposed controller following step load resistor change. A dotted line is used to denote the trigger time. It is demonstrated, for a positive or negative load resistor step change, that the transient is fast and well damped, without any overshoots. Figs. 13 and 14 depict the dynamic behavior of the converter with the proposed controller following step-input voltage change. Note the output voltage has only slight deviation from initial value and soon returns in several switching cycles, the transient response is fast. It is clear that the proposed solution has the ability to reject various disturbances, and the experimental results are consistent with the simulation results, as shown before. V. CONCLUSION A digital average current-mode control technique without current sensor for improving the dynamic performance of dc dc converters in DCM is presented. It shows that the controller can enable a high dynamic performance in DCM by using the capacitor charge balance principle and controlling the average charge current directly. The proposed digital control technique

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can be used in a range of dcdc converters, including buck, boost, and buckboost. The simulation and experimental results have proved that the dynamic performance in boost converters is achievable by using the proposed solution. The digital control technique described here can be used in several dcdc application elds, where high dynamic performance is required. REFERENCES
[1] D. Trevisan, P. Mattavelli, and P. Tenti, Digital control of single-inductor multiple-output step-down DC-DC converters in CCM, IEEE Trans. Ind. Electron., vol. 55, no. 9, pp. 34763483, Sep. 2008. [2] S. Saggini, M. Ghioni, and A. Geraci, An innovative digital control architecture for low-voltage, high-current DC-DC converters with tight voltage regulation, IEEE Trans. Power Electron., vol. 19, no. 1, pp. 210 218, Jan. 2004. [3] L. Corradini, E. Orietti, P. Mattavelli, and S. Saggini, Digital hysteretic voltage-mode control for DC-DC converters based on asynchronous sampling, IEEE Trans. Power Electron., vol. 24, no. 1, pp. 201211, Jan. 2009. [4] M. Barai, S. Sengupta, and J. Biswas, Dual-mode multiple-band digital controller for high-frequency DC-DC converter, IEEE Trans. Power Electron., vol. 24, no. 3, pp. 752766, Mar. 2009. [5] H. Peng, D. Maksimovic, A. Prodic, and E. Alarcon, Modeling of quantization effects in digitally controlled DC-DC converters, IEEE Trans. Power Electron., vol. 22, no. 1, pp. 208215, Jan. 2004. [6] B. Miao, R. Zane, and D. Maksimovic, System identication of power converters with digital control through cross-correlation methods, IEEE Trans. Power Electron., vol. 20, no. 5, pp. 10931099, Sep. 2005. [7] M. Ilic and D. Maksimovic, Digital average current-mode controller for DC-DC converters in physical vapor deposition applications, IEEE Trans. Power Electron., vol. 23, no. 3, pp. 14281436, May 2008. [8] R. O. Alejandro, S. A. Simon, and E. B. Gustavo, Digital control of a voltage-mode synchronous buck converter, IEEE Trans. Power Electron., vol. 21, no. 1, pp. 157163, Jan. 2006. [9] V. Yousefzadeh, W. Naris, Z. Popovic, and D. Maksimovic, A digitally controlled DC/DC converter for an RF power amplier, IEEE Trans. Power Electron., vol. 21, no. 1, pp. 164172, Jan. 2006. [10] S. Chae, B. Hyun, P. Agarwal, W. Kim, and B. Cho, Digital predictive feed-forward controller for a DC-DC converter in plasma display panel, IEEE Trans. Power Electron., vol. 23, no. 2, pp. 627634, Mar. 2008. [11] S. Saggini, W. Stefanutti, E. Tedeschi, and P. Mattavelli, Digital deadbeat control tuning for dc-dc converters using error correlation, IEEE Trans. Power Electron., vol. 22, no. 4, pp. 15661570, Jul. 2007. [12] S. Bibian and J. Hua, High performance predictive dead-beat digital controller for DC power supplies, IEEE Trans. Power Electron., vol. 17, no. 3, pp. 420427, May 2002. [13] C. Jingquan, A. Prodic, R. W. Erickson, and D. Maksimovic, Predictive digital current programmed control, IEEE Trans. Power Electron., vol. 18, no. 1, pp. 411419, Jan. 2003. [14] S. Chattopadhyay and D. Somshubhra, A digital current-mode control technique for DC-DC converters, IEEE Trans. Power Electron., vol. 21, no. 6, pp. 17181726, Nov. 2006. [15] Y.-S. Jung, Small-signal model-based design of digital current-mode control, IEE Proc. Electr. Power Appl., vol. 152, no. 4, pp. 871877, Jul. 2005. [16] A. Soto, A. D. Castro, P. Alou, J. A. Cobos, J. Uceda, and A. Lofti, Analysis of the buck converter for scaling the supply voltage of digital circuits, IEEE Trans. Power Electron., vol. 22, no. 6, pp. 24322443, Nov. 2007. [17] G. Feng, E. Meyer, and Y.-F. Liu, A digital two-switching-cycle compensation algorithm for input-voltage transients in DC-DC converters, IEEE Trans. Power Electron., vol. 24, no. 1, pp. 181191, Jan. 2009. [18] K. S. Leung and H. S. Chung, Dynamic hysteresis band control of the buck converter with fast transient response, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 7, pp. 398402, Jul. 2005. [19] K. S. Leung and H. S. Chung, Derivation of a second-order switching surface in the boundary control of buck converters, IEEE Power Electron. Lett., vol. 2, no. 2, pp. 6367, Jun. 2004. [20] K. S. Leung and H. S. Chung, A comparative study of boundary control with rst- and second-order switching surfaces for buck converters operating in DCM, IEEE Trans. Power Electron., vol. 22, no. 4, pp. 11961209, Jul. 2007.

[21] G. Feng, E. Meyer, and Y.-F. Liu, Novel digital controller improves dynamic response and simplies design process of voltage regulator module, in Proc. IEEE Appl. Power Electron. Conf., 2007, pp. 14471453. [22] E. Meyer, Z. Zhang, and Y.-F. Liu, An optimal control method for buck converters using a practical capacitor charge balance technique, IEEE Trans. Power Electron., vol. 23, no. 4, pp. 18021812, Jul. 2008. [23] G. Feng, E. Meyer, and Y.-F. Liu, A new digital control algorithm to achieve optimal dynamic performance in DC-to-DC converters, IEEE Trans. Power Electron., vol. 22, no. 4, pp. 14891498, Jul. 2007. [24] Z. Zhao and A. Prodic, Continuous-time digital controller for high frequency DC-DC converters, IEEE Trans. Power Electron., vol. 23, no. 2, pp. 564573, Mar. 2008. [25] M. Ferdowsi and A. Emadi, Estimative current mode control technique for DC-DC converters operating in discontinuous conduction mode, IEEE Power Electron. Lett., vol. 2, no. 1, pp. 2023, Mar. 2004. [26] P. Athalye, D. Maksimovic, and R. Erickson, Variable-frequency predictive digital current mode control, IEEE Power Electron. Lett., vol. 2, no. 4, pp. 113116, Dec. 2004. [27] A. Davoudi and J. Jatskevich, Parasitic resistance realization in statespace average-value modeling of PWM DC-DC converters using an equal area method, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 9, pp. 19601967, Sep. 2007. [28] A. Davoudi, J. Jatskevich, and P. L. Chapman, Averaged modelling of switched-inductor cells considering conduction losses in discontinuous mode, IET Electr. Power Appl., vol. 1, no. 3, pp. 402406, May 2007.

Ying Qiu received the B.Sc. and M.Sc. degrees from the School of Electronic and Information Engineering, Dalian University of Technology, Dalian, China, in 2005 and 2008, respectively, from where he is currently working toward the Ph.D. degree with the Department of Electrical and Electronics Engineering. His current research interests include modeling, analysis, and control of dcdc power electronics systems.

Xiyou Chen received the B.Sc., M.Sc., and Ph.D. degrees from Harbin Institute of Technology, Harbin, China, in 1982, 1985, and 2000, respectively. From April 2004 to March 2005, he was a Visiting Scholar in the Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON, Canada. He is currently a Professor with the Department of Electrical and Electronics Engineering, Dalian University of Technology, Dalian, China. His research interests include the areas of power electronics and its control, green power conversion, renewable power generation, matrix converters, and motor drive.

Helen Liu received the Ph.D. degree from the School of Engineering, Cardiff University, Wales, U.K. She is currently with the Faculty of Engineering and Physical Sciences, University of Surrey, Guildford, U.K. She has been engaged in academic and industrial sectors for teaching, research, and design in electronics, automatic control, precision measurement, signal detection, analysis, and processing for more than 20 years. Her research interests include the areas of automation, production systems and computer control, precision measurement, signal analysis, and processing.