ASTABLE MULTIVIBRATOR USING 555IC

AIM :-

a) To study the operation of Astable multi vibrator using 555 trainer IC and
compare the theoretical and practical results. COMPONENTS AND EQUIPMENTS REQUIRED:1. 2. 3. 4. 555 TRAINER. ..1NO. D.C POWER SUPPLY (0-30) V , 1A .1NO. CATHODE RAY OSCILLOSCOPE..1NO. PATCH CORDS.

CIRCUIT DIAGRAM:

VCC 10V

8 Ra 4 RST VCC

Rb

7 3 OUT 6 DIS 555 2 THR TRI 5 CON GND C2 1

Vo

C1

THEORY: Take Ra 1. 2. 3. 4. 5. Calculate the charging time period, T1 =0.69 (Ra +Rb)C Calculate the dis charging time period, T2 = 0.69RbC The time period of the outputVo is T =T1 +T2 Free runnig frequency of output F =1/T Percentage duty cycle =T1/T1+T2'100

EXPECTED WAVE FORMS:

PROCEDURE :1. Connect the circuit as per the diagram. 2. Apply a voltage of 10v from DC power supply as shown in the diagram. 3. Observe the output(vo) at pin 3 and capacitor voltage(vc) at pin 6 with respective to ground (pin 1), on the Cathode Ray Oscilloscope. 4. Calculate t1 ,t2 ,t and f from the observed waveforms and compare with the theoretical values. 5. Calculate the duty cycle and compare with the theoretical values. 6. Tabulate the results

BINARY SUBTRACTORS

AIM:- To design a half subtractor and a full subtractor using minimum number of NAND gates and verify the truth table

EQUIPMENT:- 1) +5V DC regulated Power Supply 2) Bread board 3) IC 7400 Quad 2 input NAND gates --------- 3NO

CIRCUIT DIAGRAM:1) HALF SUBTRACTOR: A logic circuit for the subtraction of two 1 bit numbers A and B is half subtrctor.A and Bare two inputs and D (difference) and B (borrow) are the two outputs of a half subtractor the truth table is as shown in table1

TABLE 1

Truth Table for half subtractor

1 2

Difference D ! A B

1 2

Barrow, B ! A.B

3
Half-Subtractor Truth Table INPUT OUTPUT A B Diff Borr 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0

2.FULL SUBTRACTOR

A full subtractor consists of two half subtractor and an OR gate the logic circuit is as shown below.

4 5 7400N

4 5 7400N 12 13 7400N 11 1 2 7400N 9 10 7400N 3

A B

1 2 7400N

12 13 7400N 8

Bi = ABBI
11

9 10 7400N

1 2 7400N

B0 ! A B.Bi  AB

Full Subtract or Truth Table A 0 0 0 0 1 1 1 1 INPUT B 0 0 1 1 0 0 1 1 OUTPUT C Diff Borr 0 0 0 1 1 1 0 1 1 1 0 1 0 1 0 1 0 0 0 0 0 1 1 1

PROCEDURE:- Connect the circuit as shown above and verify truth tables for half subtractor and full subtractor. Gates 1 to 4 constitute half subtractor the borrow bit obtained at gate 3 output is B = AB check the borrow bit for half subtractor by connecting NAND gate 9 as inverte

OP-AMP APPLICATIONS-II (Differentiator) AIM :a. To study the operation of a differentiator. b. To plot the frequency response of an op-amp differentiator and to compare the theoretical and practical values of fa & fb. COMPONENT AND EQUIPMENT REQUIRED :1. 2. 3. 4. 5. Resistors 100;, 1K; Capacitors 0.1Qf , 0.01Qf Audio Signal Generator Op-amp IC 741 Cathode Ray Oscilloscope

CIRCUIT DIAGRAM:-

Rf

R1 V1

C1 2

-15 v
4 741 3

Cf

Vo

Vin

7 1 5

+15

THEORY:- Frequency at which gain is zero db

Fa =1/2T Rf C1 Gain limiting frequency fb =1/2T R1 C1 Where R1 C1= Rf Cf

PROCEDURE:1. Connect the circuit as per as the circuit diagram. 2. The circuit functions as a differentiator when Rf C1 < t, where t is the time period of the input signal say Rf C1 = t/10. 3. Apply a square wave signal of frequency 1kHz and observe the output to contain the positive and negative spikes. 4. Apply a sinusoidal signal of frequency 100Hz and amplitude vi =0.1v and note down the v0 . Calculate the voltage gain Av = v0/ vin and Av in dB, Av in dB = 20 log (v0/ vin). Vary the frequency in step upto 1MHz. Keeping vi constant and note down v0. Calculate fa & fb from the graph and verify with the theoretical values.

Expected Graph :

INTEGRATOR USING IC 741 OP AMP

AIM :a) To study the operations of an integrators. b) To plot the frequency response of an op-amp integrator and compare the theoretical and practical values of fa & fb . COMPONENTS AND EQUIPMENT REQUIRED :1) 2) 3) 4) 5) Resistors 100;, 1k;, 10k; ..1no each. Capacitor 0.1Qf, 0.01Qf 1no each. Audio signal generator. Op-amp IC 741. Cathode Ray Oscilloscope.

CIRCUIT DIAGRAM :10kOhm_5% Rf 0.01uF Cf 100Ohm_5% R1 Vs 2 3 7 4 6 OPAMP_IC741

+ Vo
_

THEORY: - Gain limiting frequency f a !

1 2TR f C f 1 2TR1C f

Frequency at which gains is zero f b !

Take Rf =10k;, R1 = 100; Cf =0.01Qf for step 3 PROCEDURE: 1) Connect the circuit as per the diagram.

2) The circuit function as an integrators when R1Cf >>t (i.e.) say R1Cf=10t.LetR1=1k;,Rf=100;,Cf=0.1Qf. t=1000v0.1v10-6 v10-1 = 0.01ms where t =time period of input signal. apply a square wave signal frequency f=1/t. (i.e.) 100 khz and observe the output to be a triangular wave. adjust the amplitude of square wave, vi =0.1v. 3) Apply a sinusoidal signal of frequency 100Hz and amplitude. vi=0.1V and note down the output vo. Calculate the voltage gain Av= vo/ vi and Av in db log10 vo/ vi . varying the frequency in steps up to 1MHz keeping vi constant and note down v0.calculate Av in db for each reading plot frequency (Hz) on x-axis and Av (in db) on y- axis. Calculate fa and fb from the graph.

OBSERVATIONS: Frequency f (Hz) Output Voltage V0 (V) AV = V0 / Vi AV in dB = 20 log10(V0 / Vi)

EXPECTED GRAPH:-

(dB) RESULT:Compare the theoretical and practical results.

Study of FLIP-FLOPS

Aim : To construct the following Flip-Flops using TTL NAND gate s and verify the Truth Table (i) R-S Flip Flop (ii) JK Flip-Flop (iii) T and D Flip-Flop (iv) Master slave J-K Flip Flop. Equipment: (i) +5V regulated power supply (ii) Source to give logic level inputs and clock input (iii) Bread Board and connecting wires (iv) Components as per circuit diagram IC 7400 (v) Triple 3 nput NAND Gate IC 7410

Circuit Diagram: Flip-Flop

7400N 3 9 10 7400N 8

1 2

Clk
4 5 7400N 12 13 7400N 11

S-R Flip Flop Truth Table INPUT OUTPUT S R Qn+1 0 0 Qn 0 1 0 1 0 1 1 1 N.A

7410N 1 2 13

7400N 12 1 2 3
Q

Clk

9 10 11 7410N
J-K Flip-Flop Truth Table

4 5 7400N

INPUT OUTPUT J K Qn+1 0 0 Qn 0 1 0 1 0 1 1 1 Qn

D
2 3 1

J Q D- Type Q K

Clk

D-Flip-Flop Truth Table INPUT OUTPUT Dn Qn+1 0 0 1 1

J Q D- Type Q K

T-Flip-Flop Truth Table: INPUT OUTPUT Tn Qn+1 0 Qn Qn 1

JnKn-Flip-Flop

J Clk

Procedure: Connect the circuits as shown in figures and verify the corresponding Truth Tables by giving the logic inputs as shown and observing the outputs on LED indication

IC-7400 (Quad 2 Input NAND Gate) Truth Table

INPUT-1 INPUT-2 OUTPUT-1 INPUT-4 INPUT-2 OUTPUT-2 GROUND

1 2 3 4 5 6 7

14 13

Vcc INPUT-4 INPUT-4 OUTPUT-4 INPUT-3 INPUT-3 OUTPUT-3

IC 12 7400 11
10 9 8

INPUT OUTPUT Jn Kn Qn+1 0 0 Qn 0 1 0 1 0 1 1 1

IC-7410 (Triple 3 Input 1 AND Gate)

INPUT-1 INPUT-1 INPUT-2 INPUT-2 INPUT-2 OUTPUT-2 GROUND

1 2 3 4 5 6 7

14 13

Vcc INPUT-1 OUTPUT-1 INPUT-3 INPUT-3 INPUT-3 OUTPUT-3

IC 7410

12 11 10 9 8

BCD TO SEVEN-SEGMENT DECODER

AIM :To study the operation of BCD to Seven segment decoder IC 7447 and verify its truth table. CIRCUIT DIAGRAM :Pin diagram: IC 7447 D1 D2 LT BI / RBO RBI D3 D0 GND 1 2 3 4 IC 7447 5 6 7 8 12 11 10 9 16 15 14 13 VCC f g a b c d e

Truth Table 1: BCD to Seven segment decoder (IC 7447)

DECIMAL DIGIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

INPUTS D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 a 1 0 1 1 0 1 0 1 1 1 0 0 0 1 0 0 b 1 1 1 1 1 0 0 1 1 1 0 0 1 0 0 0 c 1 1 0 1 1 1 1 1 1 1 0 1 0 0 0 0

OUTPUTS d 1 0 1 1 0 1 1 0 1 0 1 1 0 1 1 0 e 1 0 1 0 0 0 1 0 1 0 1 0 0 0 1 0 f 1 0 0 0 1 1 1 0 1 1 0 0 1 1 1 0 g 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 0

NUMERICAL DESIGNATION AND RESULTANT DISPLAYS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Truth Table 2: Function of Control inputs INPUTS D3 X X L L L L D2 X X L L L L D1 X X L L L H D0 X X L L H L LT L X H H H H IN/OUT OUTPUT RBI BI/RBO X H X L L L H H X H X H Q* 8 Off Off 0 1 2 . . . . 14

H H H L H

* Decoded figure, segments outputs L. PROCEDURE :1. Connect the trainer to the mains and the switch ON the power supply. 2. Connect LT, RBI, BI/RBO inputs to logic 1. 3. Verify the output (seven segment display reading) for different BCD input conditions as per Truth table 1. The resultant output for each digit is shown above. 4. Verify the operation of LT, RBI, BI/RB0 with the help of Truth table 2.

LOGIC GATES (DISCRETE VERSION)

AIM:- To construct the following logic gates using discrete components and verify their truth tables COMPONENTS &EQUIPMENT REQUIRED 1).D.C Power Supply (0-30)V, 1A ----------- 1NO 2). Diodes IN4003 3).Resistors, ----------- 2NO

2.2K;, 10K, 22K ---------- 1NO ---------- 1NO ---------- 1NO

4).Transistor, 2N2369, 5).DMM

CIRCUIT DIAGRAM &TRUTH TABLE

BASIC LOGIC GATES 1. AND GATE Truth Table

1 2

INPUT A B 0 0 0 1 1 0 1 1

OUT PUT Y=A.B 0 0 0 1

2. NOT GATE Truth Table

1 2

INPUT A B 0 0 0 1 1 0 1 1

OUT PUT Y=A+B 0 1 1 1

3. NOT GATE Truth Table INPUT A 0 1 OUTPUT Y= A 1 0

4. NAND GATE Truth Table

1 2

INPUT A B 0 0 0 1 1 1 0 1

OUTPUT Y = AB 1 1 1 0

5. NOR GATE Truth Table

2 3

INPUT A B 0 0 0 1 1 1 0 1

OUTPUT Y = A B 1 0 0 0

6. EXCLUSIVE OR GATE Truth Table

1 2

INPUT A B 0 0 0 1 1 1 0 1

OUTPUT Y =AB 0 1 1 0

PROCEDURE:According to truth tables give inputs and note down the output voltage using DMMfor all the above circuits

THREE TERMINAL VOLTAGE REGULATORS Aim Equipments required: 1. Voltage Regulator trainer AET-67 2. Digital Multimeter 2No. 3. DC Ammeter 0-200mA Procedure 1. Connect the trainer to the mains and switch on the supply 2. Measure the output of the Regulated power supply that 0 to + 40 and 0 to 40 using digital multimeter. Fixed voltage regulators 7805 (+5V): 1. Connect the circuit as shown in the figure to observe the line regulation

Vin 0 to +35V
DMM

7805
2

3
DMM

+5V

C 22/25V

Vo

GND By varying Vin supply in steps measure the corresponding output Vo and record in a tabulated from as shown below.

Vin

Vout

Plot the graph between Vin, Vo and observe the line regulation Connect the circuit as shown below to observe the load regulation.

Vin 0 to +35V

7805
2

200mA A

+
C 22/25V -

250E

+5V

Vo

GND Measure and record the output voltage Vo (no load) at 0 load current

By varying the load (250 ; potentiometer) in steps, measure the load current IL, corresponding output voltage Vo and record them as shown below. IL (mA) Vo (V) Load regulation

Calculate load regulation using Vo (no load)-Vo Vo

Plot the graph between IL, Vo and observe the load regulation.

7905 (-5V): Connect the circuit as shown below fig. for line line regulation.

Vin 0 to -35V
DMM

7905
1

3 -5V 22/25V C DMM

Vo

GND

Repeat the steps 5 and 6. Connect the circuit as shown below for load regulation
200mA

Vin 0 to -35V
DMM

7905
1

+
C 22/25V -

250E

-5V

Vo

GND

Repeat the steps 8 to 11.

BINARY ADDERS

AIM:- To design a half adder and full adder using minimum number of NAND gates and verify the truth table.

EQUIPMENT:- 1) DC Regulated Power Supply 2) Bread Board 3) Components as per circuit diagram IC 7400

CIRCUIT DIAGRAM:

1) HALF ADDER

A logic circuit for the addition of two 1 bit number A and B is Half adder A and B are two inputs and S (sum) and C (carry) are the two outputs. The truth table is shown in table1 Table 1 Truth Table for half adder

1 2

AB Carry

1 2

A B ! = AB  AB

Half Adder Truth Tale INPUT OUTPUT A B Sum Carry 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1

FULL ADDER A full adder consists of two half adder and an OR gate the truth table is shown in table-2 Table-2 Truth Table for full adder

Ci

4 5 7400N

4 5 7400N 1 2 7400N 3

1 2 7400N 12 13 7400N 11

12 13 7400N 9 10 7400N 8

S ! A B Ci
11

9 10 7400N

8 1 2 7400N

C o ! AB  BC i  Ci A
3

Full-Adder Truth Table INPUT OUTPUT A B C Sum Carry 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1

PROCEDURE:- Connect the circuit diagram as above and verify the truth tables for half a Gates 1 to 4 Constitute Half Adder .

Pin conifiguretion of IC 7400 is as shown dder and full adder . Gates 1 to 4 Constitute Half Adder . Pin conifiguretion of IC 7400 is as shown

PROCEDURE:- Connect the circuit diagram as above and verify the truth tables for half adder and full adder . Gates 1 to 4 Constitute Half Adder . Pin configuration of IC 7400 is as shown

7490 COUNTER

Aim:Truth table verification of decoder counter IC7490.

Truth table verification of decoder counter IC 7490.

Procedure
1. Connect the trainer to the mains and switch ON the power supply, measure the output of the regulated power supply + 5V (Note: supply is internally connected to the circuits so no need to connect externally). Observe the outputs of clock generator and pulse circuit using CRO. Connect R01, R02, S91 and S92 to logic 0 (Note: To set counter in count mode) Connect pulser output to A input and short B input and Q0 output. Verify the counter outputs as per the truth table 1. Now connect counter outputs (Q0, Q1, Q2, Q3) to the seven segment display (D0, D1, D2, D3) to observe counter output in decimal reading Repeat the steps 4 to 6 by replacing manual pulse with 1 Hz clock. Verify the operations of R01, R02, S91 and S92 according to the truth table 2.

2. 3. 4. 5. 6. 7. 8.

Truth table 1:

COUNT A 0 1 2 3 4 5 6 7 8 9

OUTPUTS Q3 Q2 Q1 Q0 L L L L L L L H L L H L L L H H L H L L L H L H L H H L L H H H H L L L H L L H

Truth table 2:

INPUTS RO1 R02 S91 S92 H H X L X L X H H X X L X L L X H L X X L X L H X L L X Q3 L L H

OUTPUTS Q2 Q1 Q0 L L L L L L L L H

Cont Cont Cont Cont

Pin diagram and truth tables

R01 R02 S91 S92

(2) (3)

&

CTR CT = 0

(6) & (7)

Z3 (14) DIV A - 3CT=1 DIV5 0 (1) CT 3CT =4 2 (9) (8) (11) Q1 Q2 Q3 (12) Q0

MONOSTABLE MULTIVIBRATOR USING 555 IC AIM:- To study the operation of monostable multivibrator using 555 timer IC and compare the theoretical and practical resultes EQUIPMENT:- 1)555 Trainer 2)D.C Power Supply 3)C.R.O 4)Components as per circuit diagram.

THEORY:A monostable multivibrator produces a single fixed pulse, each time a trigger pulse is applied to pin 2 is trigger input of 555. The trigger input is a narrow pulse with a quiescent value of Vcc . When the trigger input drops to 1/3 Vcc, the output goes high and the capacitor starts charging. When the threshold voltage at pin 6 is slightly greater tha n 2/3Vcc, the output goes low. The width of the output can be designed by the formula.

Tp=1.1.R.C CIRCUIT DIAGRAM:-

VCC 10V

8 VCC 4 R RST VCC

7 3 OUT 6 DIS 2 555 2 THR TRI 5 CON 3 GND C2 0 1

Vo

PROCEDURE:- 1)Connect the circuit as shown in the circuit diagram. 2)The trigger circuit generates the negative going triggering pulses connected to trigger input of 555 observe these pulses. 3)Observe the output Vo at pin no .3 and capacitor voltage at pin 6. 4)Measure the time period tp of the monostable multivibrator using CRO and compare with the theoretical value. 5)Vary the resistance value by connecting another 4.7K; parallel to Rand observe the change at the output. 6)Note the observations and draw the waveforms.

WAVE FORMS:-

Input and Out put Waveforms:-

FUNCTION GENERATOR USING OP-AMP

Aim : To generate signals that produce various specific wave forms using IC-741 OpAmp. Equipment Required : 1. Sine wave generator (wein bridge oscillator) 2. Zero crossing detector 3. Active Integrator 4. Switching circuit for function selection and 5. Amplifier

Circuit Diagram :

1KpF

1N4148 10KE

1N4148

472KE 22KE
2

0.1/250
5

O/P

1 4

1KpF 472KE

0.1/250

472KE
3

In Put

1KE
2

0.1/250 741
5

O/P

1 4

1KE

COMPONENTS AND EQUIPMENT REQUIRED: 1.Function Generator using op-amp trainer kit. 2.Dualtrace Oscilloscope. 3.Digital Multimeter. PROCEDURE: 1.Connect trainer to the mains and switch ON the supply. 2.Observe the output of the sine wave oscillator(wein-bridge oscillator).If signal is not coming or distorted in shape adjust the gain trim pot until you get the good signal. Measure the signal frequency using oscilloscope. 3.Observe output of the zero crossing detector(square wave) by varying the input signal(sine waves internally connected to the circuit) frequency. 4.Observe the output of the integrator(triangle) by varying the input signal frequency(square wave is internally connected to the circuit). 5.Now connect sine, square, triangle signals to the switching circuit 6.Connect output of the switching circuit to the output amplifier. Select the desired signal using switch. 7.Observe the final output. 8.Make the same circuits on bread board observe the output wave forms.

4-BIT D/A CONVERTOR AIM :- To convert 4-bit digital signal to analog signal. COMPONENTS AND EQUIPMENT :1. 4-Bit D/A converter (R-2R) ET 43 2. Digital Multimeter (DMM) THEORY :Digital to analog conversion is necessary in all computer application to enable the computer to communicate with o contro real world analog devices. The purpose of theis experiment is to introduce you to a common 4-bit digital to analog convertor. Pacifig trainer kit AET43 is self contained educational kit to demonstrate 4-bit D/A converter using Op-Amp and R-2R ladder network. This bit consists of wired circuit of regulated power supply and 4-bit D/A converter.

Rf R R R
2 4 1

+12 3

V V 0

2R

2R

2R

2R

2R

-12V

R L

b0 (LSB) + 5V

b1

b2

b3 (MSB)

CIRCUIT DISCRIPTION :For this operation Op-Amp is connected in inverting configuration. The binary inputs are simulated by switches b0 through b3 and the output is proprotianl to the binary inputs. Binary inputs can either be the high (+5V) or low (0V) state. The output voltage equation is give by. b b b1 b  0 V0 !  R f 3  2  2 R 4 R 8 R 16 R In this expression Rf = 11K; and R = 11K;, for example. 1. When b3 is high and all other inputs are low then the O/p voltage is 0 0 0 5    V0 =  R f 2 R 4 R 8 R 16 R

 5 =  11 2 x11 = -2.5 V 2. When all inputs are in high state then O/P voltage is 5 5 5 5 V0 =  11    2 x11 4 x11 8 x11 16 x11 = -4.6875 V PROCEDURE : 1. Study the operation of the circuit 2. As the circuit is already wired you just have to trace the circuit according to the circuit diagram give above. 3. Connect trainer to the mains and switch on the power supply. 4. Measure the O/P voltage of regulated power supply circuit i.e +12V and 12 V. 5. Note down the O/P voltages for different combination of digital inputs and compare it with the theoretical values.

RESULTS : We observed that the theoretical and practical values at analog output voltage by the given digital inputs.

3-BIT A/D CONVERTER

AIM : - To study the operation of the 3 bit flash type A/D converter.

COMPONENTS AND EQUIPMENT :1. A/D converter trainer kit 2. Digital multi meter (DMM) THEORY :The process of converting an analog voltage into an equivalent digital signal is known as Analog to Digital conversion. Flash type is the simplest and fastest method of conversion. The simultaneous method of A/D conversion is based on the use of number of comparator circuits. A 3-bit A/D converter is shown in the circuit diagram.

The analog signal is to be a digitalized server as one of the inputs to each comparator the 2nd input is a standard reference volt. When the analog I/P signal exceeds the reference voltage at any comparator the comparator output goes high. The comparator output is given to an encoder circuit. The 3-bit A/D converter shown in the circuit diagram has Va as the analog voltage. To be converted in to digital form. The voltage corresponding to full scale V from which the reference voltage VR1, VR2,. Are generated using the resistor divider N/W. The reference voltages generated from a supply of +5V are +V/8, +3V/8, +V/2, +5V/8, +3V/4, 7V/8. The system is capable of accepting analog I/P voltage b/w 0 to 5V. the analog voltage V is compared simultaneously with the reference voltages using comparators. A 1 bit is obtained from the comparators. This 1 bit digital signal is converted into 3 bit output by using a 74LS1148 priority encoder circuit the comparator output and the 3 bit digital output for each interval of the analog voltage are given below in table 1. CIRCUIT DIAGRAM :-

PROCEDURE 1. Connect the circuit as shown in circuit diagram. 2. Apply the variable 0-5V as analog input in steps of 0.5V measure the analog input using a DDM. 3. Verify the digital outputs for each corresponding analog inputs and note down. THEORITICAL VALUE :1. LSB value = Vcc 5 5 ! 3 ! ! 0.625 n 8 2 2

(a) If input voltage Va = 1 Volt. The output voltage = InputVoltage 1 LSB Value

1 0.625 = (1.6)10 = (1)16 = (0.01)2 =

(b) If input voltage Va = 5 Volts. The output voltage = Input Voltage 1 LSB Value

5 0.652

= (8)10 = (8)16 = (111)2 RESULTS : The operation of a 3 bit flash type A/D converter is studied.

VOLTAGE CONTROLLED OSCILLATOR

COMPONENTS AND EQUIPMENT REQUIRED : 1. Voltage Controlled Oscillator trainer kit 2. Dual trace oscilloscope 3. digital multimeter.

CIRCUIT DIAGRAM :-

Ground NC Software-Wave O/P Triangle-Wave O/P

1 2 3 4 NS/SE 566 VCO

8 7 6 5

+V C1 R1 Modulation I/P

+12V R1 7.5K 10K 15K 1uF

6 P1
1000pF

4 10K

Triangle - O/P

Input R2

5 7

IC 566
3 1

Square - O/P

1KpF

10KpF

0.1uF

10K

THEORY : -/ CIRCUIT DISCRIPTION : Voltage Controlled Oscillator (VCO) is a circuit in which this output frequency is controlled by means of input voltage. VCO also called a voltage to freqnuecy converter. A typical example is the Signetic NE/SE 566 VCO, which provides simultaneious square wave and triangular wave outputs as a function of input voltage. Figure 1.1 is a block diagram of the 566. the frequency of oscillation is determined by an external resistor R, external capacitor C and the voltage Vc applied to the control terminal 5. the triangular wave is generated by alternately charging the external capacitor C by one current source and then linearly discharging it by another. The charge and discharge levels are determined by Schmitt trigger action. The Schmitt trigger also provides the square wave output. Both theoutput waveforms are buffered so that the output impedance of each is 50;. The typical amplitude of the triangular wave is 2.4 V pp and that of the square wave is 5.4 V pp. Figure 1.2 is a typical connection diagram. in this arrangement, the external resistors (7.5k, 10k and 15K) and external capacitors (1Kpf, 10Kpf, and 0.1Qf) combination determines the free-running frequency, and the control voltage Vc at terminal 5 is set by the voltage divider formed with R1 and R2. The initial voltage Vc at 5 must be in the range. (+V) e Vc e +V Where +V is the total supply voltage. The frequency of the output waveforms is approximated by f0= 2(+V-Vc) / (RC(+V)) Where R should be in the range 2K;<R<20K;. For a fixed Vc and constant C, the frequency f0 can be varied over a 10:1 frequency range by the choice of R between 2K; and 20K; . Similarly, for a c constant RC product, the frequency f0 can be modulated over a 10:1 range by the control voltage Vc. in either case the maximum output frequency is 1MHz. A small capacitor 1Kpf should be connected between pins 5 and 6 to eliminate possible oscillations in the control current source. EXPERIMENTAL PROCEDURE : 1. switch on the trainer and measure the output voltage of the regulated power supply i.e +12 V. 2. Connect one of the range resistors (7.5K, 10K and 15K) and (Power supplies are connected internally so no external is connection is required). 3. Connect dual trace oscilloscope to square and triangular outputs.

4. connect digital multimeter to VCO input. 5. By varying the voltage at VCO input (with the help of potentiometer given ) observe the output signal on CRO and measure the outputfrequency 6. Compare output frequency with theoretical value given by f0 |2(+V-Vc)/(RC(+V))

7. Repeat the steps 3 to 7 for different values of R, C and compare the theoretical and practical frequencies

PHASE LOCKED LOOP Aim : To study the characteristics of phase locked loop like lock range, capture range and free running frequency. Apparatus: 1. Phase locked loop trainer 2. Digital Multimeter 3. CRO and Probes 4. Signal Generator 5. Connecting wires. Procedure: 1. Switch ON the trainer and measure the o/p of the regulated power supplies i.e +12V and s5V. 2. Observe the o/p of the square wave generator using oscilloscope and measure the frequency range with the help of frequency counter. Frequency range should be around 1KHz to 10 KHz. 3. Calculate the free running frequency rage of the circuit. For different values of timing resistor Rt (to measure the Rt switch off the trainer and measure the Rt value using digital multi meter between two given test points) and record the frequency values in table. 4. Connect 0.1QF capacitor (Cc ) to the circuit and short the pins 4 & 5. Measure the minimum and maximum free running frequency obtainable at the o/p of he PLL (Pin 4) by varying the potentiometer. Compare your results with your calculations from step 3 (theoretical value). Simultaneously you can you can observe the o/p signal using CRO Lock Range : 5. Calculate the lock range of the circuit for a 5 KHz free running frequency and record table.

6. Connect pins 4 & 5 with the help of springs and adjust potentiometer to get free running frequency of 5KHz. Connect square wave generator o/p to the i/p of the PLL circuit. Provide a 5KHz square signal of 1V (p-p) approximately make this i/p frequency as close to the Vo frequency as possible. 7. Connect the frequency counters to the i/p and o/p of the PLL (you can also connect oscilloscope simultaneously). 8. Observe the i/p and o/p frequencies while slowly increasing the frequency of he square wave at the i/p. for same range o/p and i/p are equal (this is known as locking and PLL said to be locked with i/p signal). Record the frequency at which the PLL breaks lock (o/p frequency of he PLL will be around Vco frequency and in oscilloscope you will se a glittering form when it breaks lock instead of clean square wave). This frequency is called as upper end of the lock range and record this as F2. 9. Beginning at 5KHz, slowly decrease the frequency at the i/p and determine the frequency of at the PLL breaks lock on the low end and record it a as F1. 10. Find lock range from F2-F1 and compare with the theoretical values from step 5. 11. Calculate the capture range of he circuit. For a 5KHz free running frequency consider filter capacitor Cc i.e 0.1QF. 12. With the oscilloscope and counter still on pin4, slowly increase the i/p frequency from minimum (say 1KHz). Record frequency (as F3) at which the i/p and o/p frequencies of he PLL equal. This is known as lower end of the capture range. 13. Now keep i/p frequency at maximum possible (say 10KHz) and slowly reduce and record the frequency (asF4) at which the i/p and o/p frequency of PLL are equal. This is known as upper end of capture range. 14. Find capture range from F4-F3 and compare it with the theoretical value from step 11. 15. Repeat steps from 11 to 14 for Cc of 0.2QF.

Theory : Phase locked loop is a versatile electronic servo system that compares the phase and frequency of a given signal with those of an internally generated reference signal. It is used for the frequency multiplication. Fm stereo detector, FM demodulator frequency shift keying decoders, local oscillator in TV and FM tuner PLLs can be used at relatively high frequencies.

The PLL kit consists of : 1. Regulated power supply ( +12V and s5V) 2. Square wave generator 3. PLL circuit using (M 565 frequency running frequency fo) When there is no i/p signal to the pin2 PLL said to be in free running mode with its frequency determined by its circuit elements Rt and Ct. Free running frequency is given by . 0.3 Rt Ct

fo =

Lock Range (FL) : Lock Range of he PLL is the range of frequencies in which the already locked PLL will remain in lock and is given by

fL = s

8 fo Vcc

capture Range (fc) : The capture range of he PLL is the range of frequencies onto which it will lock prior to being in lock. The capacitor Cc and internal resistance 3.6 KE from Low Pass RC filter to remove the digital frequencies, their harmonics and the sum frequency and approximately given by.

1 fc = s 2T

2Tf c 3.6 x103 xCc

Conclusion : The lock range, capture range and free running frequency are calculated thus characteristics of phase locked loop are studied PHASED LOCKEDLOOP OBSERVATIONS fo S.No Rt K; T practical (Qs) practical (KHz) fo theoretical (KHz)