PHASE CHANGE MEMORY Seminar Report 2011-2012 Submitted in partial fulllment for the award of the Degree of Bachelor

of Technology in Electrical and Electronics By

ARJUN P RAJ Univ roll no:65309 Under the guidance of THOMAS K P

Department of Electrical and Electronics RAJAGIRI SCHOOL OF ENGINEERING AND TECHNOLOGY Rajagiri Valley, Cochin-682039 Kerala, India

CERTIFICATE

This is to certify that the report entitled PHASE CHANGE MEMORY is a bonade record of the project done by Arjun P Raj, of 7th semester Electrical and Electronics Engineering in partial fulllment of the requirements for the award of Degree of Bachelor of Technology in Electrical & Electronics Engineering of the Mahatma Gandhi University, Kottayam during the academic year 2011 2012.

Mr. Thomas K P (guide) Asst Professor Dept. of Electrical & Electronics Engineering

Place:Kakkanad Date:19-12-2011

Prof. K R Varmah Professor & HOD Dept. of Electrical & Electronics Engineering

Acknowledgement

The satisfaction and euphoria that accompanies the successful completion of any task would be incomplete sans the mention of the people who made it possible, whose constant guidance and encouragement crowd our eort with success. First and foremost, I would like to express my whole hearted thanks to the invisible, indomitable God for his blessings showered upon me in enabling to complete this seminar on time. I would like to extend my heartiest thanks to the management of our college, who provided me with necessities for the completion of the seminar. I would also like to extend my heartfelt thanks to Prof.Rajendra Varmah (H.O.D., EEE) for the inspiration inculcated in me and for apt guidance. It would be a grave error if I forget to take a mention of my seminar guide, Asst. Prof. Thomas K P and coordinator,Lecturer Jebin Francis whose constant persistence and support helped me in the completion of this seminar. I also remember the teachers of the Department of Electrical Engineering, who were always a support in my academics. I am also thankful to my friends and well-wishers for their support and prayers. With a heart full of gratitude I submit this report.Once again I thank all who walked with me to make this venture a grant success.

ARJUN P RAJ

Abstract

The memory subsystem accounts for a signicant cost and power budget of a computer system. Current DRAM-based main memory systems are starting to hit the power and cost limit. An alternative memory technology that uses resistance contrast in phase-change materials is being actively investigated in the circuits community. Phase Change Memory (PCM) devices oer more density relative to DRAM, and can help increase main memory capacity of future systems while remaining within the cost and power constraints. A PCM-based hybrid main memory system using an architecture level model of PCM is analyzed and the trade-os for a main memory system consisting of PCM storage coupled with a small DRAM buer is explored. Such an architecture has the latency benets of DRAM and the capacity benets of PCM.

Contents
1 Introduction 2 What is PCM? 3 Chalcogenide materials 4 Theory Of Operation 4.1 Writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Main Features 6 Disadvantages 7 Comparison 8 PCM Based Memory Model 9 Hybrid Main Memory Organization 9.1 Lazy Write Organization . . . . . . . . 9.2 Line Level Writes . . . . . . . . . . . . 9.3 Fine-Grained Wear-Leveling for PCM 9.4 Page Level Bypass for Write Filtering 9.5 Impact Of These Techniques . . . . . 10 Conclusion 1 2 4 5 6 8 9 11 12 14 16 16 17 17 19 20 21

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List of Figures
2.1 2.2 3.1 4.1 4.2 4.3 4.4 7.1 7.2 7.3 8.1 9.1 9.2 Typical PCM cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCM storage cell and its implementation . . . . . . . . . . . . . . . . . . Periodic table-Chalcogenides . . . . . . . . . . . . . . . . . . . . . . . . . Amorphous and Polycrystalline current-voltage characteristic . Set Pulse And Reset Pulse . . . Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 4 5 6 7 8

Typical Access Latencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 PCM VS FLASH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Main Memory Organisations . . . . . . . . . . . . . . . . . . . . . . . . . 14

Lazy write Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Fine Grained Wear Leveling . . . . . . . . . . . . . . . . . . . . . . . . . . 18

iii

List of Tables
4.1 9.1 9.2 Set operation VS Reset Operation . . . . . . . . . . . . . . . . . . . . . . 7

Impact of the dierent techniques on performance . . . . . . . . . . . . . 20 Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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List of Abbreviations
1. PCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phase Change Memory 2. DRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dynamic Random Access Memory 3. OS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating System 4. HDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hard Disk Drive 5. LLWB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Line Level Write Back 6. FGWL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fine Grained Wear Leveling 7. PLB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page Level Bypass

Chapter 1

Introduction
Current computer systems consist of several cores on a chip, and sometimes several chips in a system. As the number of cores in the system increases, the number of concurrently running applications (or threads) increases, which in turn increases the combined working set of the system.The memory system must be capable of supporting this growth in the total working set. For several decades, DRAM has been the building block of the main memories of computer systems. However, with the increasing size of the memory system, a signicant portion of the total system power and the total system cost is spent in the memory system. Current DRAM-based main memory systems are starting to hit the power and cost limit. Therefore, technology researchers have been studying new memory technologies that can provide more memory capacity than DRAM while still being competitive in terms of performance, cost, and power. An alternative memory technology that uses resistance contrast in phase-change materials is being actively investigated in the circuits community.this is known as Phase Change Memory (PCM).These devices oer more density relative to DRAM, and can help increase main memory capacity of future systems while remaining within the cost and power constraints. There are several challenges to overcome before PCM can become a part of the main memory system. First, PCM being much slower than DRAM, makes a memory system comprising exclusively of PCM, to have much increased memory access latency; thereby, adversely impacting system performance. Second, PCM devices are likely to sustain signicantly reduced number of writes compared to DRAM, therefore the write trac to these devices must be reduced. Otherwise, the short lifetime may signicantly limit the usefulness of PCM for commercial systems.

Chapter 2

What is PCM?
PCM or Phase change memory is a type of non-volatile memory that exploits the property of chalcogenide glass to switch between two states, amorphous and crystalline, with the application of heat using electrical pulses. The phase change material can be switched from one phase to another reliably, quickly, and a large number of times. The amorphous phase has low optical reexivity and high electrical resistivity. Whereas, the crystalline phase has high reexivity and low resistance. PCM exploits dierences in the electrical resistivity of a material in these dierent phases. The dierence in resistance between the two states is typically about ve orders of magnitude and can be used to infer logical states of binary data namely 1(high bit) and 0 (low bit).

Figure 2.1: Typical PCM cell The gure shows a graphical representation of a basic PCM storage element. As shown on the left, a layer of chalcogenide is sandwiched between a top electrode and a bottom electrode. A resistive heating element extends from the bottom electrode and contacts a layer of the chalcogenide material. Current injected into the junction of the chalcogenide and the heater induces the phase change through Joule heating. Figure at right is the actual implementation of the concept, showing an amorphous bit formed in

Figure 2.2: PCM storage cell and its implementation a layer of polycrystalline chalcogenide. Because of the change in reectivity, the amorphous bit appears as a mushroom cap shaped structure in the layer of polycrystalline chalcogenide.

Chapter 3

Chalcogenide materials
The PCM technology uses a class of materials known as chalcogenides (prounounced kal-KOJ-uh-nydes). Chalcogenides are alloys that contain an element in the Oxygen/Sulphur family of the Periodic Table i.e Group 16 in the new style or Group VIa in the old style Periodic Table (usually combined with IV and V group elements)

Figure 3.1: Periodic table-Chalcogenides The history of phase-change materials can be traced back to work starting in the 1950s by Dr. Stanford Ovshinsky who was researching the properties of a class of glassy materials that exhibited the ability to easily and stably change between two phases. By the late 1960s, he had reported that certain of these materials exhibited a reversible change both in resistivity and reectivity when changing between an ordered (polycrystalline) state and a disordered (amorphous) state. It was recognized that this eect could be exploited both for optical memory as well as electronic memory Phase-change materials have been in use for many years for high-volume rewritable CDs and DVDs which make use of the dierence in optical properties. Numonyx PCM is using an alloy of Germanium, Antimony and Tellurium (Ge2Sb2Te5), known more commonly as GST. Most companies performing research and development in PCM today are using GST or closely related alloys. Other alloys that are being used for the research purposes of PCM are Nitrogen-doped GST, Sb2Te3 with N-doping (STN), AgInSbTe (silver-indium-antimony-tellurium)

Chapter 4

Theory Of Operation
Phase-change chalcogenides exhibit a reversible phase change between the amorphous phase and the crystalline phase. As illustrated in Figure 4.1, in the amorphous phase, there is an absence of regular order to the crystalline lattice. In this phase, the material demonstrates high resistivity and low reectivity. In contrast, in the polycrystalline phase, the material has a regular crystalline structure and exhibits high reectivity and low resistivity.

Figure 4.1: Amorphous and Polycrystalline In PCM, we are exploiting the dierence in resistivity between the two phases of the material.This phase change is induced in the material through localized Joule heating caused by current injection. The nal phase of the material is modulated by the magnitude of the injected current and the time of the operation.

4.1

Writing

The PCM material is between a top and a bottom electrode with a heating element that extends from the bottom electrode, and establishes contact with the PCM material. When current is injected into the junction of the material and the heating element, it induces the phase change. Crystallizing the phase-change material by heating it above the crystallization temperature (but below the melting temperature) is called the SET operation. The SET operation is controlled by moderate power, and long duration of electrical pulses and this returns the cell to a low-resistance state, and logically stores a 1. Melt-quenching the material is called the RESET operation, and it makes the material amorphous. The RESET operation is controlled by high-power pulses which places the memory cell in high-resistance state and logically stores a 0. In the phase-change memory, threshold switching provides a means to deliver the required programming current needed to program a bit in the high-resistance state at low voltage. From a high-resistance (RESET) state, a pcm bit is programmed into a low-resistance (SET) state by applying programming voltage in excess of Vth, allowing the bit to enter the dynamic ON state. Current then is allowed to ow for a length of time sucient to ensure crystallization. The device can then be programmed to the RESET state by applying a short, somewhat larger current pulse to a bit in the polycrystalline state. The reset pulse only needs to be of sucient magnitude and duration to melt the programmed volume of chalcogenide alloy and to have a fast enough falling edge to permit the molten programmed volume of material to cool fast enough to vitrify. The duration of the reset pulse can be short, since the material in the programmed volume can be heated to the melting point in a few nanoseconds.

Figure 4.2: current-voltage characteristic gure 4.2:Current-voltage characteristics for an Ovonic Unied Memory (OUM) cell element in both the RESET (amorphous, high-resistance) and SET (crystalline, lowresistance) states,showing key device parameters: Read/SET/RESET regimes and SET and RESET states.Vh is the holding voltage, and Vth is the switching threshold voltage. 6

Figure 4.3: Set Pulse And Reset Pulse gure 4.3:Ta-amorphization temperature, Tx-crystallization temperature

SET OPERATION Crystallizing the pcm Pulse of Moderate power but long duration To Low resistance state Logically stores 1 pulse of 150 microampere ,1.2V A SET dissipates 90 microWatt for 150ns A set operation consumes around 13.5 picojoules

RESET OPERATION Melt quenching to make it amorphous Pulse of higher power but short duration To high resistance state Logically stores 0 pulse of 300 microampere, 1.6V A RESET dissipates 480 microWatts for 40ns A RESET operation consumes about 19.2pJ

Table 4.1: Set operation VS Reset Operation

4.2

Reading

Figure 4.4: Reading To read the data, the chips use a smaller current to determine which state the chalcogenide is in.Information stored in the cell is read out by measurement of the cells resistance. In read mode, verifying the cell resistance is accomplished at a Voltage Less than Vth, typically 0.4 V. This ensures that while reading the state of the cell is not aected and no writing can take place. Prior to reading the cell, the bitline is precharged to the read voltage. The wordline is active low when using a BJT access transistor. If a selected cell is in a crystalline state,having low resistance, the bitline is discharged with current owing through the storage element and access transistor. Otherwise,if the cell is in an amorphous state,it prevents or limits bitline current since in this state the material has high resistance.

Chapter 5

Main Features
1.Bit-alterabile Like RAM or EEpROM, PCM is bit alterable. Flash technology requires a separate erase step in order to change information. Information stored in bit-alterable memory can be switched from a one to zero or zero to a one without a separate erase step. 2.Scaling Both NOR and NAND rely on memory structures which are dicult to shrink at small lithos. This is due to gate thickness remaining constant and the need for operation voltage of more than 10V while the operation of CMOS logic has been scaled to 1V or even less. This scaling eect is often referred to as Moores Law, where memory densities double with each smaller generation. Flash rely on oating gate memory structures, which are also dicult to shrink. With PCM, as the memory cell shrinks, the volume of GST material shrinks as well, providing a truly scalable solution. Chalcogenide lms have already been proven to have stable characteristics to a 5nm node. As the PCM memory cell shrinks, the volume of GST material involved in the state change shrinks resulting in reduced power consumption or higher write performance. This unique feature of PCM technology supports the promise of scalability beyond that of other memory technologies. 3.Density PCM is a dense technology with feature size comparable to DRAM cells. Furthermore, a PCM cell can be in dierent degrees of partial crystallization thereby enabling more than one bit to be stored in each cell, Recently, a prototype with two logical bits in each physical cell has been demonstrated. This means four states with dierent degrees of partial crystallization are possible, which allows twice as many bits to be stored in the same physical area.Hence the density of PCM is almost four times to that of DRAM. Hence more amount of information can be stored in a PCM, than that of a DRAM for a given size. 4.Non-volatile PCM is non-volatile.It does not require a constant power supply to retain information, while DRAM does.Hence there is no need of refreshing circuits inorder to maintain the data in a PCM.

5.Read performance Like RAM and NOR-type ash, the technology features fast random access times. This enables the execution of code directly from the memory, without an intermediate copy to RAM. The read latency of PCM is comparable to single bit per cell NOR ash, while the read bandwidth can match DRAM. In contrast, NAND ash suers from long random access times on the order of 10s of microseconds that prevent direct code execution. 6.Write/erase performance PCM is capable of achieving write speeds like NAND, but with lower latency and with no separate erase step required. NOR ash features moderate write speeds but long erase times. As with RAM, no separate erase step is required with PCM, but the write speed (bandwidth and latency) does not match the capability of RAM today. The capability of PCM is expected, however, however, to improve with each process generation as the PCM cell area decreases.

10

Chapter 6

Disadvantages
1.Limited Lifetime The number of writes to a PCM is limited about 109 ,afterwhich the memory cell begin to wear out.Due to the fact that the operation is temperature dependant.Expansion and contraction. 2.High access latencies PCM also suers from high access latencies compared to DRAM.It is around 250 ns for PCM whereas 60 ns in case of DRAM 3.High energy consumption Though PCM enjoys the advantage of having almost zero leakage power, it suers from higher dynamic power consumption. This mainly supported by the fact that the read and write operations are temperature dependant.

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Chapter 7

Comparison

Figure 7.1: Typical Access Latencies Figure 7.1 shows the typical access latency (in cycles, assuming a 4GHz machine) of dierent memory technologies, and their relative place in the overall memory hierarchy. Hard disk drive (HDD) latency is typically about four to ve orders of magnitude higher than DRAM . A technology denser than DRAM and access latency between DRAM and hard disk can bridge this speed gap. Flash-based disk caches have already been proposed to bridge the gap between DRAM and hard disk, and to reduce the power consumed in HDD. However, with Flash being 28 times slower than DRAM, it is still important to increase DRAM capacity to reduce the accesses to the Flash-based disk cache. The access latency of PCM is much closer to DRAM, and coupled with its density advantage, PCM is an attractive technology to increase memory capacity while remaining within the system cost and power budget. Furthermore, PCM cells can sustain 1000x more writes than Flash cells, which makes the lifetime of PCM-based memory system in the range of years as opposed to days for a Flash-based main memory system. Write endurance is the maximum number of writes for each cell. Data retention is the duration for which the non-volatile technologies can retain data. It can be found from the gure 7.2 that it has Density similar to NAND ash and Read latency similar to NOR ash PCM oers a density advantage similar to NAND Flash, which means more main memory capacity for the same chip area. The read latency of PCM is similar to NOR 12

Figure 7.2: Comparison Flash, which is only about 4X slower compared to DRAM. The write latency of PCM is about an order of magnitude slower than read latency. However, write latency is typically not in the critical path and can be tolerated using buers. Finally, PCM is also expected to have higher write endurance (106 to 108 writes) relative to Flash (104 writes).

Figure 7.3: PCM VS FLASH

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Chapter 8

PCM Based Memory Model

There are several challenges to overcome before PCM can become a part of the main memory system. First, PCM being much slower than DRAM, makes a memory system comprising exclusively of PCM, to have much increased memory access latency; thereby, adversely impacting system performance. Second, PCM devices are likely to sustain signicantly reduced number of writes compared to DRAM, therefore the write trac to these devices must be reduced. Otherwise, the short lifetime may signicantly limit the usefulness of PCM for commercial systems. There is active research on PCM, and several PCM prototypes have been proposed, each optimizing for some important device characteristics (such as density, latency, bandwidth, or lifetime). While the PCM technology matures, and becomes ready to be used as a complement to DRAM, it is believed that system architecture solutions can be explored to make these memories part of the main memory to improve system performance.

Figure 8.1: Main Memory Organisations Figure 8.1 (a) shows a traditional system in which DRAM main memory is backed by a disk. Flash memory is nding widespread use to reduce the latency and power requirement of disks. In fact, some systems have only Flash-based storage without the hard disks; for example, the MacBook Air laptop has DRAM backed by a 64GB Flash 14

drive. It is therefore reasonable to expect future highperformance systems to have Flashbased disk caches such as shown in Figure 8.1(b). However, because there is still two orders of magnitude dierence in the access latency of DRAM memories and the next level of storage, a large amount of DRAM main memory is still needed to avoid going to the disks. PCM can be used instead of DRAM to increase main memory capacity as shown in Figure 8.1(c). However, the relatively higher latency of PCM compared to DRAM will signicantly decrease the system performance. Therefore, to get the best capacity and latency, Figure 8.1(d) shows the hybrid system we foresee emerging for future high-performance systems. The larger PCM storage will have the capacity to hold most of the pages needed during program execution, thereby reducing disk accesses due to paging. The fast DRAM memory will act as both a buer for main memory, and as an interface between the PCM main memory and the processor system. We show that a relatively small DRAM buer (3 percentage size of the PCM storage) can bridge most of the latency gap between DRAM and PCM.

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Chapter 9

Hybrid Main Memory Organization

In a hybrid main memory organization, the PCM storage is managed by the Operating System (OS) using a Page Table, in a manner similar to current DRAM main memory systems. The DRAM buer is organized similar to a hardware cache that is not visible to the OS, and is managed by the DRAM controller. Although, the DRAM buer can be organized at any granularity, it can be assumed that both the DRAM buer and the PCM storage are organized at a page granularity. DRAM memory acts as a buer as well as an interface between the PCM and processor Dierent techniques used in this hybrid main memory organization are 1.Lazy write organization 2.Line level writes 3.Fine grained wear levelling 4.Page level bypass

9.1

Lazy Write Organization

The Lazy-Write organization reduces the number of writes to the PCM and overcomes the slow write speed of the PCM, both without incurring any performance overhead. When a page fault is serviced, the page fetched from the hard disk (HDD) is written only to the DRAM cache. Although allocating a page table entry at the time of page fetch from HDD automatically allocates the space for this page in the PCM, the allocated PCM page is not written with the data brought from the HDD. This eliminates the overhead of writing the PCM. To track the pages present only in the DRAM, and not in the PCM, the DRAM tag directory is extended with a presence (P) bit. When the page from HDD is stored in the DRAM cache, the P bit in the DRAM tag directory is set to 0. In the lazy write organization, a page is written to the PCM only when it is evicted from the DRAM storage, and the P bit is 0, or the dirty bit is set. If on a DRAM miss, the page is fetched from the PCM then the P bit in the DRAM tag directory entry of that page is set to 1. When a page with P bit set is evicted from the DRAM, it is not written back to the PCM unless it is dirty. Furthermore, to account for the larger write latency of the PCM a write queue is associated with the PCM. We assume that tags of both the write queue and the DRAM buer are made of SRAM in order to help 16

Figure 9.1: Lazy write Organization in probing these structures while incurring low latency. Given the PCM write latency, a write queue of 100 pages is sucient to avoid stalls due to write queue being full.

9.2

Line Level Writes

Typically, the main memory is read and written in pages. However, endurance limits of the PCM require exploring mechanisms to reduce the number of writes to the PCM. We propose writing to the PCM memory in smaller chunks instead of a whole page. For example, if writes to a page can be tracked at the granularity of a processors cache line, the number of writes to the PCM page can be minimized by writing only dirty lines within a page. We propose Line Level WriteBack (LLWB), that tracks the writes to pages held in the DRAM on the basis of processors cache lines. To do so, the DRAM tag directory shown in Figure 9.1 is extended to hold a dirty bit for each cache line in the page. In this organization, when a dirty page is evicted from the DRAM, if the P bit is 1 (i.e., the page is already present in the PCM), only the dirty lines of the page are written to the PCM.When the P bit of a dirty page chosen for eviction is 0, all the lines of the page will have to be written to the PCM. LLWB signicantly reduces wasteful writes from DRAM to PCMfor workloads which write to very few lines in a dirty page. To support LLWB we need dirty bits per line of a page. For example, for the baseline system with 4096B page and 256B linesize, we need 16 dirty bits per page in the tag store of DRAM buer.

9.3

Fine-Grained Wear-Leveling for PCM

Memories with limited endurance typically employ wear-leveling algorithms to extend their life expectancy. For example, in Flash memories, wear-leveling algorithms arrange data in a manner so that sector erasures are distributed more evenly across the Flash cell array and single sector failures due to high concentration of erase cycles are minimized.

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LLWB reduces write trac to PCM. However, if only some cache lines within a page are written to frequently, they will wear out sooner than the other lines in that page. We analyze the distribution of write trac to each line in a PCM page. Figure 9.2 shows the total writeback trac per dirty page for the two database applications, db1 and db2. The average number of writes per line is also shown. The page size is 4KB and line size is 256B, giving a total of 16 lines per page, numbered from 0 to 15. The lifetime of PCM can be increased if the writes can be made uniform across all lines in the page. This can be done by tracking number of writes on a per line basis, however, this would incur huge tracking overhead.

Figure 9.2: Fine Grained Wear Leveling Fine Grained Wear-Leveling (FGWL),is used for making the writes uniform (in the average case) while avoiding per line storage. In FGWL, the lines in each page are stored in the PCM in a rotated manner. For a system with 16 lines per page the rotate amount is between 0 and 15 lines. If the rotate value is 0, the page is stored in a traditional manner. If it is 1, then the Line 0 of the address space is stored in Line 1 of the physical PCM page, each line is stored shifted, and Line 15 of address space is stored in Line 0. When a PCM page is read, it is realigned. The pages are written from the Write Queue to the PCM in a line-shifted format. On a page fault, when the page is fetched from the hard disk, a Pseudo Random Number Generator (PRNG) is consulted to get a random 4-bit rotate value, and this value is stored in the WearLevelShift (W) eld associated with the PCM page as shown in Figure 9.1. This value remains constant until the page is replaced, at which point the PRNG is consulted again for the new page allocated in the same physical space of the PCM.

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9.4

Page Level Bypass for Write Filtering

Not all applications benet from more memory capacity. For example, streaming applications typically access a large amount of data but have poor reuse. Such applications do not benet from the capacity boost provided by PCM. In fact, storing pages of such applications only accelerates the endurance related wear-out of PCM. As PCM serves as the main memory, it is necessary to allocate space in PCM when a page table entry is allocated for a page. But, the actual writing of such pages in the PCM can be avoided by leveraging the lazy write architecture. We call this Page Level By- pass (PLB). When a page is evicted from DRAM, PLB invalidates the Page Table Entry associated with the page, and does not install the page in PCM. We assume that the OS enables/disables PLB for each application using a conguration bit. If the PLB bit is turned on, all pages of that application bypass the PCM storage.

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9.5

Impact Of These Techniques

No.of bytes per cycle 0.317 0.807 0.725 0.316 0.247 Average Lifetime 7.6yrs 3.0 yrs 3.4 yrs 7.6 yrs 9.7 yrs

Conguration PCM 32GB +1 GB DRAM +LAZY WRITE +LLWB +PLB

Table 9.1: Impact of the dierent techniques on performance No. 1 2. 3. 4. 5. 6. 7. Parameter scalabality Density latency(read) write speed dynamic power static power crosstalk eect DRAM less less less high less high high PCM high high high low high nil nil Hybrid limited high medium medium medium medium less

Table 9.2: Comparison

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Chapter 10

Conclusion
Phase change memory can be exploited by the memory system and by the convergence of consumer, computer and communication electronic systems. The caching of the existing memory technologies, reducing the overall system cost and system complexity will be the compelling motivation for PCM adoption. Bandwidth will drive the sustaining side of PCM in code and data transfer applications, while reduction in power dissipation will represent a further added value of this technology. However, PCM comes with the drawback of increased access latency and limited number of writes. Inorder to overcome these disadvantages we can use it in conjunction with a DRAM buer and make use of three techniques: Lazy Write, LLWB, and PLB. These simple techniques can reduce the write trac by 3X and increase the average lifetime of PCM from 3 years to 9.7 years. Fine Grained Wear Leveling (FGWL) technique can be used to make the wear-out of PCM storage uniform across all lines in a page. PCM is todays memory breakthrough. Like ash, PCM is a non-volatile memory that can store bits even without a power supply. But unlike ash, data can be written to cells much faster, at rates comparable to the dynamic and static random-access memory (DRAM and SRAM) used in all computers and cell phones today. Quite simply, PCM blends together the best attributes of NOR ash, NAND ash, EEpROM and RAMdelivering a new category of memory for new usage models.

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[3] Wong, H.-S.P.; SangBum Kim; Byoungil Lee; Caldwell, M.A.; Jiale Liang; Yi Wu; Jeyasingh, R.G.D.; Shimeng Yu, Recent progress of phase change memory (PCM) and resistive switching random access memory (RRAM) , IEEE 10.1109/ICSICT.2010.5667542, 2010, pp: 1055 - 1060

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