LMV 108 VLSI Design Lab Technology, Vazhakulam Experiment No: 1 Date: 10 09 2011

Department of Electronics and Communication Engineering Viswajyothi College of Engineering and

SEQUENCE DETECTOR
AIM To design and implement sequence detector (1101) SOFTWARES USED 1. ModelSim (Versions) 2. Xilinx (Versions) 3. Iverilog 4. Gtkwave

CIRCUIT DIAGRAM

0/0

0/0 1/0 0/0 B 1/0

0/0

1/0

E 1/0 1/1 C 0/0 D

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LMV 108 VLSI Design Lab Technology, Vazhakulam

Department of Electronics and Communication Engineering Viswajyothi College of Engineering and

Truth table NEXT STATE PRESENT STATE A B C D E X=0 A A D A A Z 0 0 0 0 0 X=1 B C E E E Z 0 0 0 1 0

PROGRAM Design module

module seqnonover(x,clk,reset,z); input x,clk,reset; output reg z; reg [2:0]ps,ns; always@(posedge clk) begin if(reset==1'b1) begin ps=3'b0; z=1'b0; ns=3'b0; end else begin 2

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LMV 108 VLSI Design Lab Technology, Vazhakulam

Department of Electronics and Communication Engineering Viswajyothi College of Engineering and

case(ps) 3'b000:begin if(x==1'b0) begin ns=3'b0; ps=ns; z=1'b0; end else begin ns=3'b001; ps=ns; z=1'b0; end end 3'b001:begin if(x==1'b0) begin ns=3'b0; ps=ns; z=1'b0; end else begin ns=3'b010; ps=ns;
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LMV 108 VLSI Design Lab Technology, Vazhakulam

Department of Electronics and Communication Engineering Viswajyothi College of Engineering and

z=1'b0; end end 3'b010:begin if(x==1'b0) begin ns=3'b011; ps=ns; z=1'b0; end else begin ns=3'b100; ps=ns; z=1'b0; end end 3'b011:begin if(x==1'b0) begin ns=3'b000; ps=ns; z=1'b0; end else begin
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LMV 108 VLSI Design Lab Technology, Vazhakulam

Department of Electronics and Communication Engineering Viswajyothi College of Engineering and

ns=3'b100; ps=ns; z=1'b1; end end 3'b100:begin if(x==1'b0) begin ns=3'b0; ps=ns; z=1'b0; end else begin ns=3'b100; ps=ns; z=1'b0; end end endcase end end endmodule

Testbench `timescale 1ns/1ps

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LMV 108 VLSI Design Lab Technology, Vazhakulam

Department of Electronics and Communication Engineering Viswajyothi College of Engineering and

`include "seqnonoverlap.v" module seqnonover_tb; reg clk,reset,x; wire z; seqnonover t1(x,clk,reset,z); initial begin $dumpfile("senonovdump.vcd"); $dumpvars(2,seqnonover_tb.t1); end initial begin clk=1'b1; reset=1'b1; x=1'b0; #10 reset=1'b0; x=1'b0; #10 x=1'b1; #10 x=1'b1; #10 x=1'b0; #10 x=1'b1; #10 x=1'b1; #10 x=1'b1; #10 x=1'b0; #10 x=1'b1;
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LMV 108 VLSI Design Lab Technology, Vazhakulam

Department of Electronics and Communication Engineering Viswajyothi College of Engineering and

#10 x=1'b0; #10 x=1'b1; #10 x=1'b1; #10 x=1'b0; #10 x=1'b1; #10 x=1'b1; #10 x=1'b0; #10 x=1'b1; #10 x=1'b1; end always #5 clk=~clk; initial #100 $finish; endmodule

OBSERVATION

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LMV 108 VLSI Design Lab Technology, Vazhakulam

Department of Electronics and Communication Engineering Viswajyothi College of Engineering and

RESUULT A sequence detector has been designed and implemented

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