VIVA VOCE QUESTIONS: 1. What is a Simulator? 2. What are the different levels of abstractions in the Verilog? 3.

. What are the differences between C language and Verilog? 4. What is the basic component in Verilog programme? 5. What is the difference between wire and reg data types? VIVA VOCE QUESTIONS: 1. What are the different logic minimization techniques and name them? 2. What is the difference between Minterm and Maxterm? 3. What is the difference between POS and SOP? 4. In logic minimization, which method is preferred if the number of variables are more than 5? 5. How many Boolean equations are possible with n variables? VIVA VOCE QUESTIONS: 1. What is module instantiation? 2. What are the different ways of association of ports in module instantiation? 3. Which is the fastest Adder? 4. What are the applications of Adders and Subtractors? 5. Which level of abstraction is suitable for combinational circuits? 6. What is the data type supports for the assignment of data in data flow modeling? VIVA VOCE QUESTIONS: 1. What are the differences between tasks and function declarations? 2. How many values can be returned using functions? 3. How many values can be returned using tasks? 4. Are the tasks and functions synthesizable? 5. Can you call a task in a function? VIVA VOCE QUESTIONS:

1. How many 2 x 1 multiplexers are required in implementing a n x 1 multiplexer where n is multiple of 2? 2. What are the applications of multiplexers and demultiplexers? 3. How many select lines are required for n x 1 multiplexer? 4. What is other name of behavioral level of abstraction? 5. Why the multiplexer can be called as a Universal element? VIVA VOCE QUESTIONS: 1. What is an Encoder and Decoder? 2. What are the applications of Encoder and Decoder? 3. How a priority encoder is different from normal encoder? 4. Why the decoder is widely used than demultiplexer? 5. Design a 3 x 8 line decoder using a 2 x 4 line decoder? VIVA VOCE QUESTIONS: 1. Write verilog code for 4 bit comparator in gate level model? 2. What are the differences between gate level and data flow models? 3. Explain gate delays using comparator? 4. What are the differences between data flow model and behavioral model? VIVA VOCE QUESTIONS: 1. What are the differences between tasks and functions? 2. Write a program for ALU using tasks and functions? 3. What are various delays in behavioral model? 4. What are various delays in data flow model? 5. What is the use of generate statement? Give its syntax? VIVA VOCE QUESTIONS: 1. Write a verilog program for D flip flop in gate level model? 2. What are user defined primitives and gate primitives? 3. What are the differences between latch and flip flop?

4. What are the differences between edge triggered flip flop and level triggered flip flop? 5. Explain synthesis of T flip flop? 6. What is Synthesis? VIVA VOCE QUESTIONS: 1. Why constructs are not supported in synthesis? 2. What is gate level net list? 3. Write verilog program for counter using instantiation? 4. Explain delay with respect to counters? 5. What is universal shift register? 6. What are the differences between synchronous and asynchronous counters? 7. What are the components that are needed to construct decade counter? VIVA VOCE QUESTIONS: 1. What is mealy machine? 2. What is moore machine? 3. What are the differences between mealy and moore machine? 4. What is state diagram? 5. Draw state diagram for module counter? 6. Generate synthesis report for mealy machine? 7. What is gate level net list? 8. What is the purpose of parameter in verilog? 9. Give the syntax of case statement? VIVA VOCE QUESTIONS: 1. Write verilog program to generate square wave of duty cycle with 66.6 %? 2. Write a program to explain pin pin delay? 3. Write a verilog program to generate rectangular wave? 4. What are timing constraints? 5. What are the differences between always and initial statements?