LAB1: Introduction and PS/2 Keyboard Interface with VHDL

Abstract Learn to use the Altera Quartus development environment and the DE2 boards by implementing a small hardware design that interfaces with a PS/2 keyboard and displays scan codes on LEDs and seven segment displays. 1 Introduction Use the Altera DE2 board to implement a simple hardware design. Describe its behavior using the VHDL language and use Alteras Quartus tools to synthesize and program the FPGA device. Use a VHDL simulator to verify and debug the design. The circuit you program into the FPGA will read the scan codes from a PS/2 keyboard and display them on LEDs and HEX seven segment displays. The circuit should retain the last three bytes received from the keyboard and display them on six seven segment displays. You will learn to set up a project in the Altera Quartus tool, run a VHDL simulation, and compile and download your design to the FPGA. VHDL is a hardware description language, and the process of using it is very different than developing programs in C++ or Java. You will need these skills in later labs and while you are developing your project. 2 The DE2 Board Altera DE2 board consists of an Altera Cyclone II FPGA connected to a variety of peripherals including 512K of SRAM, 4MB of Flash, 8 MB of SDRAM, VGA output, Ethernet, audio input and output, and USB ports. There are three USB connectors on the top of the board. The leftmost onethe one nearest the 9V DC connectoris for connecting the Altera Blaster cable to the workstation. It is through this connection that the FPGA will be programmed, that debugging information flows, etc. The other two USB ports can be used in projects. The DE2 board holds two quartz crystal oscillators (clock sources: little silver boxes labeled with their frequencies). We will use the 50 MHz clock for this lab; there is also a 27 MHz clock designed for VGA timing. The DE2 board has built-in configuration for testing and demonstration purpose. You can verify the board is working properly by observing this default behavior. Use the following procedure to power up the DE2 board. First, connect the USB blaster cable from the USB port on the workstation to the USB Blaster connector on the DE2 board. Next, connect the 9V adapter to the DE2 power connector at the top left corner. Third, verify the RUN/PROG switch on the left edge of the DE2 board (just to the left of the LCD display) is in the RUN position. Power on the DE2 board by pressing the red ON/OFF switch in the upper left corner. The LEDs should flash and the LCD should display Welcome to the Altera DE2 Board. To download our design and override the default configuration of the FPGA, we use a JTAG port (JTAG is a ubiquitous standard that stands for the IEEE Joint Test Action Group). The Altera Quartus tool running on the workstation sends the configuration bit stream through the USB cable to the Cyclone II FPGA. Once programmed, the FPGA retains its configuration as long as power is applied to the board; it is lost when the power is turned off.

3 Part 1: Top Level Design Setup

Quartus is Alteras development environment for FPGAs. It consists of an IDE and a compiler that can translate circuits described in VHDL into configuration data for the FPGA. Altera provides a variety of reference designs for the DE2. For lab 1, we start with the DE2_Top design, which contains information about what each pin on the FPGA is connected to and a top-level VHDL module with a port for each pin. Download the DE2_Top.zip from the class website and open the project. DE2_TOP.qpf is the top Quartus project file. For Quartus to configure an FPGA, it must know which pins on the FPGA perform what roles (i.e., what each is named). This information is board-specific since the pins on the FPGA can be wired to arbitrary peripherals. An easy way of making the pin assignments when we use the same pin names as in the DE2 User Manual is to import the assignments given in the file called DE2_pin_assignments.csv in the DE2_Top directory. Compile and download the supplied project to the board. If all goes well, the design should spring to life.

4 Part 2: PS/2 Keyboard Interface Simulation Hardware is usually much harder to design than software for a variety of reasons. One is that the usual edit-compile-debug cycle is longer because it takes longer to compile hardware. Another reason is that the behavior of hardware is harder to observe. It is difficult to put a print statement in hardware. It is even harder to probe a wire inside a chip. To help you get started, a PS/2 keyboard hardware controller is provided (keyboard.vhd) [1]. This controller can be used to read the PS/2 keyboard scan codes [2-3]. This controller converts the serial data from the keyboard to parallel format to produce the scan code output. The interface of this entity is shown in Fig. 1. ENTITY keyboard IS PORT ( keyboard_clk, keyboard_data, clock_50MHz, reset, read : IN STD_LOGIC; scan_code : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 ); scan_ready : OUT STD_LOGIC ); END keyboard; Fig. 1. Keyboard controller interface Clock_50MHz is an input that must be connected to the on-board clock oscillator (CLOCK_50). Keyboard_clk and keyboard_data are PS/2 input clock and data lines from the keyboard. They must be connected to PS2_CLK and PS2_DAT pins. Scan_code contains the 8-bit scan codes transmitted by the keyboard when a key is pressed or released. Scan-ready is a handshake output signal that goes High or 1 when a new scan code is received from the keyboard. The read input signal clears the scan_ready signal.

In this lab, we will only look a keyboard-to-host communication. No command will be sent to the keyboard. So, clock and data lines are driven by the keyboard. The provided controller filters out reflected pulses, noise, timing hazard from the clock line by the clock_filter process. This filtering process is achieved by determining if the clock pulses generated by the keyboard have been High or Low for eight successive 25 MHz clock cycles. The controller waits for the start bit then receives the 8 data bits, 1 parity bit, and a stop bit. It then assigns the received 8

data bits to the scan_code output and sets the output scan_ready signal to High to indicate a new scan code is available. Add this file to your project and set it as Top-Level Entity. Compile and simulate this vhdl file using Quartus II. Verify the functionality of this controller. You should screen-capture the timing waveforms to include in your lab report.

5 Part 3: PS/2 Keyboard Interface with LEDs Develop a lab1_part3 module that has an interface as shown in Fig. 2. This module should read the scan codes from a PS/2 keyboard and save the last three bytes received to byte3, byte2 and byte1 respectively (byte1 is the last scan code received). ENTITY lab1_part3 IS PORT ( ps2_clk, ps2_dat, clock_50, reset_n: in std_logic; byte3, byte2, byte1: out std_logic_vector (7 downto 0) ); END lab1_part3; Fig. 2. Lab1_part3 interface Instantiate this module in the top-level architecture in DE2_Top.vhd (note: remember to set the DE2_Top.vhd as Top-Level entity). For this design: reset_n should be connected to KEY(0). Assign byte3 to LEDR[17:10] (red LEDs). Assign byte2 to LEDR[7:0] (red LEDs). Assign byte1 to LEDG[7:0] (green LEDs). Remember to disable the constant assignments to LEDR and LEDG before you add your lab1_part3 component. Download your design to configure the FPGA on the DE2 board. Connect a PS/2 keyboard to the DE2 board and demonstrate your design. Document your design/debug/verification steps in your lab report. 6 Part 4: PS/2 Keyboard Interface with LEDs and Seven Segment Displays Starting from the code developed for lab1_part3, create a module named lab1_part4 that has an interface as shown in Fig. 3. ENTITY lab1_part4 IS PORT ( ps2_clk, ps2_dat, clock_50, reset_n : in std_logic; hex5,hex4,hex3,hex2,hex1,hex0: out std_logic_vector(6 downto 0); byte3, byte2, byte1: out std_logic_vector (7 downto 0) ); END lab1_part4 ; Fig. 3. Lab1_part4 interface

Modify your design to convert byte3, byte2 and byte1 to six 7-bit patterns that can be used to display six hex numbers on the 7-segment LEDs. Specifically, patterns to display 2 hex digits for byte3 should be assigned to hex5 and hex4. Patterns to display 2 hex digits for byte2 should be assigned to hex3 and hex2. Patterns to display 2 hex digits for byte1 should be assigned to hex1 and hex0. Instantiate this module in the top-level architecture in DE2_Top.vhd. For this design: reset_n should be connected to KEY(0). Assign byte3 to LEDR[17:10] (red LEDs). Assign byte2 to LEDR[7:0] (red LEDs). Assign byte1 to LEDG[7:0] (green LEDs). Assign the six hex-number patterns to HEX0, HEX1, HEX2, HEX3, HEX4 and HEX5. Remember to disable the constant assignments to LEDR, LEDG, HEX0 to HEX5 before you add your lab1_part4 component. Download your design to configure the FPGA on the DE2 board. Connect a PS/2 keyboard to the DE2 board and demonstrate your design. Document your design/debug/verification steps in your lab report. 7 Reference
[1] J. O. Hamblen, T. S. Hall, and M. D. Furman, Rapid Prototyping of Digital Systems, SOPC Edition, New York, Springer, 2008. [2] Interfacing the AT keyboard, http://www.beyondlogic.org/keyboard/keybrd.htm [3] Keyboard Scan Codes, http://www.computer-engineering.org/ps2keyboard/scancodes2.html