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Procedia Engineering
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Procedia Engineering 00 (2011) 000000 3143 Procedia Engineering 15 (2011) 3139

Advanced in Control Engineering and Information Science

Scaling down the supply voltage of CPL circuits

Jianping Hua, Jindan Chenb a*
a ,b

Faculty of Information Science and Technology, Ningbo University, 315211 Ningbo City, China

Abstract Scaling supply voltage is an efficient technique to achieve low energy delay product (EDP). This paper investigates CPL (Complementary Pass-Transistor Logic) circuits operating on near-threshold regions in terms of low EDP. All circuits are simulated with HSPICE at a PTM 0.13m CMOS technology by varying supply voltages from 0.6V to 1.2V with 0.1V steps. The results demonstrate that lowering supply voltage of the CPL circuits is advantageous especially in medium-voltage regions (700mv-800mv), which yield the best EDP.

2011 Published by Elsevier Ltd. Selection and/or peer-review under responsibility of [CEIS 2011]
Keywords: Nanometer integrated circuit; Medium-voltage opereting; Low power; Complementary pass-transistor logic

1. Introduction High performance, low energy and small area are main objectives of IC designs. Technology scaling increases the density and performance of integrated circuits, resulting in large power dissipations [1]. In order to achieve low energy consumption, sub-threshold computing is one good solution [2]. However, the performance of the sub-threshold circuits is at least 10 times lower than super-threshold circuits due to the exponential relationship between delay and supply voltage [3, 4]. EDP (Energy Delay Product) metric provides a good compromise between speed and energy consumption. In this work, the EDP characteristics of CPL (Complementary Pass-Transistor Logic) circuits [5] with different voltages from sub-threshold region to super-threshold region have been addressed. All circuits are simulated with HSPICE at a PTM 0.13m CMOS technology [6] by varying
* Corresponding author. Tel.: +086-574-87609493; fax: +086-574-87600940. E-mail address: nbhjp@yahoo.com.cn.

1877-7058 2011 Published by Elsevier Ltd. doi:10.1016/j.proeng.2011.08.589

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supply voltages from 0.6V to 1.2V with 0.1V steps. The results demonstrate that lowering supply voltage is advantageous, especially in medium-voltage region (700mv-800mv), which yields the best EDP. In addition, it is shown that the optimum supply voltage of the CPL gates varies slightly according to gate types. 2. CPL Circuits The basic idea of the CPL is to accept true and complementary inputs and produces true and complementary outputs by using pass-transistor logic [5]. Several CPL gates (Buffer/Inverter, AND/NAND, OR/NOR, and XOR/XNOR) are shown in Fig 1.
A A 3 A 3 Ab VDD VDD 6 Outb 6 (a) Buffer/Inverter Ab Bb Bb 3 3 B VDD VDD 6 A B 6 (c) OR/NOR 6 P1 3/3 3/3 P2 VDD 6 A B A B 6 (d) XOR/XNOR 6 VDD 6 P1 3/3 3/3 B 3 A 3 Bb B Ab 3 A 3 Bb VDD P2 VDD 6 A B 6 P1 3/3 3/3 P2 VDD 6 Out A B 6 (b) AND/NAND Ab 3 A 3 B 6 VDD 6 P1 3/3 3/3 Ab Ab 3 3 A B Ab 3 A 3 Bb VDD P2 VDD 6 A B Ab 3 A 3 B

Fig. 1. Basic gates based on complementary pass-transistor logic (CPL)

These gates have some interesting properties: Since the circuits are differential, complementary data inputs and outputs are always available. Although generating the differential signals requires extra circuits, the differential style has the advantage that some complex gates such as XOR/XNOR and adders can be realized efficiently with a small number of transistors. Furthermore, the availability of both polarities of every signal eliminates the need for extra inverters, as is often the case in static CMOS. CPL belongs to the class of static gates, because the output-defining nodes are always connected to either power source (VDD) or GND through a low-resistance path. This is advantageous for the noise

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resilience. This design is very modular. In effect, all gates use exactly the same topology. Only the inputs are permutated. This makes the design of a library of gates very simple. More complex gates can be built by cascading the standard pass-transistor modules. 3. Scaling Down Supply Voltage for CPL Circuits Scaling down supply voltage for CPL circuits is investigated in terms of low EDP. HSPICE simulations have been carried out for the four CPL gates (Buffer/Inverter, AND/NAND, OR/NOR, and XOR/XNOR) and the corresponding static CMOS circuits with different voltages from sub-threshold regions to super-threshold regions. All circuits are simulated with HSPICE at a PTM 0.13m CMOS technology by varying supply voltages from 0.6V to 1.2V with 0.1V steps. In order to simulate the work environment of the CPL gates, the testing platforms for the four CPL gates and static CMOS circuits are shown in Fig 2. The power dissipations of the circuits in the box are tested. In order to assure the fairness of the comparison, the same input is given to these circuits.

Fig. 2. (a) Test bench of the static CMOS circuits, and (b) Test bench of the CPL gates

A size optimization considering delay and power has been carried out for all the four gates based on CPL and static logic. The channel length of all the transistors is taken as L=2 (=60nm) except for the transistors P1 and P2 shown in Fig 1. The channel widths of the transistors are shown in Fig 1. 3.1. Propagation delay Propagation delay is expressed as

tdelay = (tpLH + tpHL ) / 2 ,

where tpLH and tpHL are low-to-high and high-to-low output transition time, respectively. The propagation delay of the four CPL gates and four static CMOS circuits are show in Fig 3. With the lowering of the source voltage, propagation delay increases.

(1)

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350 300 250 Delay (ns) 200 150 100 5 0 0 0.6 0.7

Jianping Hu and Jindan / Procedia Engineering 00 (2011) 000000 Jianping Hu, Jindan ChenChen / Procedia Engineering 15 (2011) 3139 3143

Buffer/Inverter(CPL) AND/NAND(CPL) OR/NOR(CPL) XOR/XNOR(CPL) Buffer/Inverter(static) AND/NAND(static) OR/NOR(static) XOR/XNOR(static) 0.8 0.9 VDD (V) 1.0 1.1 1.2

Fig. 3. Propagation delay of the CPL gates and corresponding static CMOS gates

3.2. Max operation frequency The maximum operation frequency is defined as

f = 1 / T = 1 /[10 (t r + tf )] ,

(2)

where tr and tf are measured maximum rise and fall times of the four CPL gates, respectively. The energy dissipations per cycle of the four CPL gates depend highly on their operation frequencies. The minimum of maximum operation frequencies for the four CPL gates has been investigated, as shown Fig 4.
600 500

Frequency (MHz)

400

300 200

0.6

0.7

0.8

0.9 VDD (V)

1.0

1.1

1.2

Fig. 4. Maximum operation frequency of CPL gates

3.3. Energy consumption and energy delay product Fig 5 (a) shows the energy consumption per switching. The operation frequency of all CPL gates is chosen by the minimum value of the maximum operation frequencies of the four CPL gates. With the decrease of the supply voltage, energy consumption is reduced rapidly.

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The energy delay product of the four CPL gates is shown in Fig 5 (b). All CPL gates achieve the minimum EDP at the supply voltage of about 0.7V. The CPL Buffer/Inverter, AND/NAND, OR/NOR, and XOR/XNOR operated in medium-voltage region provide an EDP reduction of 45.93%, 50.38%, 39.1% and 51.93% as compared to nominal supply voltage operation (1.2V), respectively.

Energy loss (fF)

Fig. 5. (a) Energy consumption per switching of the four CPL gates and static CMOS circuits, and (b) EDP of the four CPL gates and static CMOS circuits

4. Conclusions Lowering supply voltage is an effective way to achieve low EDP for the CPL circuits, especially in medium-voltage region (700mv-800mv), which yields the best EDP. The optimum supply voltage of the basic CPL gates varies slightly with gate style. Acknowledgements Project is supported by National Natural Science Foundation of China (No. 61071049), Zhejiang Science and Technology Project of China (No. 2010C31116), Scientific Research Fund of Zhejiang Provincial Education Department (No. Z200908632), and Ningbo Natural Science Foundation (No. 2009A610066). References
[1] Agarwal A, Kim CH, Mukhopadhyay S, Roy K. Leakage in nano-scale technologies: Mechanisms, impact and design considerations. Proceedings of the 41st annual Design Automation Conference 2004, p. 6-11. [2] Wang A, Calhoun BH, and Chandrakasan AP. Sub-threshold design for ultra low-power systems. Springer; 2006. [3] Dreslinski R, Wieckowski M, Blaauw D, Sylvester D, Mudge T.L. Near-threshold computing: Reclaiming Moores Law through energy efficient integrated circuits. Proceedings of the IEEE 2010, vol. 98, p. 253-266. [4] Hu J, Yu X. Near-threshold full adders for ultra low-power applications. in IEEE PACCCAS 2010, p. 300-303. [5] Yano K, Yamanaka T, Nishida T, Saito M, Shimohigashi K, Shimizu A. A 3.8-ns CMOS 16 x 16 multiplier using complementary pass-transistor logic. IEEE Journal of Solid-State Circuits 1990, vol. 25, p.388-395. [6] Zhao W, Cao Y. New generation of predictive technology model for sub-45nm design exploration. in Proc. ISQED 2006, p.585-590.

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