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VICKRAM COLLEGE OF ENGINEERING

ENATHI 630561, TAMILNADU DEPARTMENT OF ELECTRONICS AND COMMUNICATION

LAB MANUAL

SUBJECT CODE : EC 1356 SUBJECT NAME : VLSI DESIGN LAB

SEM / YEAR : VI SEM ESTER/ III YEAR

PREPARED BY

Ms. A. Yasodai
Asst.Prof / ECE

Mr.M. Sakthimohan
Lecturer/ECE

H.O.D / ECE

PRINCIPAL

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INDEX

S.No

DATE

NAME OF THE EXPERIMENTS

MARKS SIGNATURE

STUDY OF SIMULATION TOOLS

STUDY OF SYNTHESIS TOOLS

STUDY OF DEVELOPMENT TOOL FOR FPGA USING SCHEMATIC ENTRY AND VERILOG STUDY OF FPGA BOARD AND TESTING ON BOARD LEDS AND SWITCHES SIMULATION OF PARALLEL ADDER

SIMULATION OF SERIAL ADDER

SIMULATION OF TRAFFIC LIGHT CONTROLLER SIMULATION OF 8- BIT MULTIPLIER

DESIGN AND IMPLEMENTATION OF REAL TIME CLOCK WITH FPGA BOARD DESIGN &IMPLEMENTATION OF TRAFFIC LIGHT CONTROL WITH FPGA BOARD

10

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VLSI DESIGN FLOW

Page |4 Ex.pt no Date:

STUDY OF SIMULATION TOOLS

Aim:
To study the simulation tools using XILINXISE 9.12 Simulator

Apparatus Required:
PC with XILINX Software

Theory:
Simulation is the functional emulation of the circuit design through software programs that uses models to replicate system, how it will perform that in terms of timings and results.The approach to verify functionality is to simulate net lists with the same of stimulus as used describing design model simulation, Save the results in a result file and compare to see if the results are identical. To avoid the delays in a design model from causing functional mismatches the maximum delay in the model must be greater than its maximum delay The fact that different values are used describing design model stimulation a potential across exists for functional mismatches to occur due to different values being the default in the two different domain.

Procedure:
1) Start the XILINX project navigator by using Start program -> XILINX 2) Select the file menu in the select new project 3) Specify the project location and project name in the window and click Next 4) Select family (Sparton 3E), Device(XC 3S400), Package(TQ 144),Speed grade(-5), Simulator(ISE) from now project wizard window and click Next. Project will be displayed and click Finish to start the project 5) Right click on device name and select New Source 6) Select Verilog module in the new project wizard. Give suitable project name and click Next for the define module window. 7) Assign the require points in this window and click Next to write the Verilog code

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8) Write the statement in the verilog code and save. 9) Check for the error using synthesis tools 10) After Synthesis again click on the device named and select new source 11) Select the test bench waveform and give suitable filename and finish 12) Duty cycle will appear for clock select then finish that one 13) Select the behavioural simulation from the scroll down list 14) Give input waveform signals and same 15) Double click on Simulate behavioral model for simulation 16) View the output according to the input

3 to 8 Decoder Logic Diagram:

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3 to 8 Decoder Truth Table:

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Program:
3-8 decoder module decoder (a,en,y); input [2:0]a; input en; output [7:0]y; reg[7:0]y; always @ (a or en) begin if(!en) y=4b0000; else case(a) 3b000 : y = 8b00000001; 3b001 : y = 8b00000010; 3b010 : y = 8b00000100; 3b011 : y = 8b00001000; 3b100 : y = 8b00010000; 3b101 : y = 8b00100000; 3b110 : y = 8b01000000; 3b111 : y = 8b10000000;

Result:
Thus the study of simulation tools in XILINX ISE 9.1i was completed

Page |8 Expt.no: Date :

STUDY OF SYNTHESIS TOOLS

Aim:
To study the synthesis tools in XILINX ISE 9.1i Simulator

Apparatus Required:
PC with XILINX Software

Theory:
Synthesis describes the process of transformation of the model of the design from one level of abstract in one domain(HDL) to a lower level of abstraction in same or other domain.Synthesis is the process of constructing a gate level net list from a register transfer level blocks.The Synthesis methodology checker is needed to ensure that the model being written is Synthesizable.Some case of functional mismatches between the design model and its synthesized net list that may possibly occur, describe their cause and provide recommendations for using them.When synthesizing an synchronous circuit preset and clear the flip flop the recommendations is to design only constant values under the asynchronous conditions.

Procedure:
1) Start the XILINX project navigator by using Start program -> XILINX 2) Select the file menu in the select new project 3) Specify the project location and project name in the window and click Next 4) Select family (Sparton 3E), Device(XC 3S400), Package(TQ 144),Speed grade(-5), Simulator(ISE) from now project wizard window and click Next. Project will be displayed and click Finish to start the project 5) Right click on device name and select New Source 6) Select Verilog module in the new project wizard. Give suitable project name and click Next for the define module window. 7) Assign the required points in this window and click Next to write the Verilog code

Page |9 8) Check syntax by process window -> Synthesize -> check syntax and remove errors if present 9) Translate your design into gates and optimize it for the target architecture.This is synthesize phase. 10) Highlight file in the source and run the synthesize process 11) Synthesize will run a green tick will appear,when synthesize is completed successfully.Red cross indicates error.Then it should be corrected.Exclamation indicates warning. 12) Now running process can be done

4 to 1 MUX:

P a g e | 10

4 to 1 MUX Truth table:

C1 0 0 1 1 C0 0 1 0 1 M X0 X1 X2 X3

Program:
module multi(y,c0,c1,x0,x1,x2,x3); input a,b,x0,x1,x2,x3; output y; wire z0,z1,z2,z3,c,d; not n1(c,c0); not n2(d,c1); and g1(z0,x0,c,d); and g2(z1,x1,c,c1); and g3(z1,x1,c0,d); and g4(z3,x3,c0,c1); or g5(y,z0,z1,z2,z3); end module;

Result:
Thus the study of synthesis tools in XILINX ISE 9.1i was completed

P a g e | 11 Ex.pt no: Date

STUDY OF DEVELOPMENT TOOL FOR FPGA USING SCHEMATIC ENTRY AND VERILOG

Aim:
To study about the development tool for FPGA using schematic entry and verilog.

Apparatus Required:
System with XILINX software

Theory:
A typical design flow for creating VLSI circuits consists of a sequence of steps beginning with design entry some CAD system include an editing program for creating and modifying the schematic.This process is called as schematic entry. The verification is performed by applying inputs to the circuit and using a logic simulator to determine the output.An important development in the design system is HDL.HDL represents logic diagram and other digital information in textual form.

Procedure:
1) Select schematic from new source and assign name to the file 2) From the sources select logic and from symbols pick and drop gates as required 3) Once the component is selected, use Add wire option to provide connection of other components or external input 4) Use Add I/O mark to assign parts. 5) Complete the schematic diagram 6) After the schematic is completed.synthesize the design 7) After the synthesize implement or simulate the same using XILINX procedure.

P a g e | 12

FULL SUBTRACTOR LOGIC DIAGRAM:

TRUTH TABLE a 0 0 0 0 1 1 1 1 b 0 0 1 1 0 0 1 1 c 0 1 0 1 0 1 0 1 D 0 1 1 1 0 0 0 1 B 0 1 1 0 1 0 0 1

Result:
Thus the study of development tool for FPGA schematic entry was completed.

P a g e | 13 Expt.no: Date

STUDY OF FPGA BOARD AND TESTING ON BOARD LEDS AND SWITCHES

Aim:
To study and test the board LEDs and switches using verilog codes.

Apparatus Required:
1. FPGA universal kit 2. Adapter 3. FRC cables 2 4. JTAG cables 1

Connections:
1) Connect FRC1 of main board connector to switch 2) Connect FRC2 of main board connector to LED

Procedure:
1) Download the program to the FPGA kit 2) Then switch on the switches and verify the corresponding LEDs glow or not

P a g e | 14

Program:
module buffer(a,y); input [7:0]a; output[7:0]y; reg[7:0]y;

always @ (a) begin y=a; end end module

User Constraint File:

NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] y[0] y[1] y[2] y[3] y[4] y[5] y[6] y[7] LOC = P83; LOC = P80; LOC = P82; LOC = P78; LOC = P79; LOC = P77; LOC = P76; LOC = P74; LOC = P96; LOC = P92; LOC = P90; LOC = P89; LOC = P87; LOC = P86; LOC = P85; LOC = P84;

Result:
Thus the testing of FPGA on board LEDS and switches was performed by using verilog codes.

P a g e | 15 Expt.no: Date :

SIMULATION OF PARALLEL ADDER

Aim:
Write a program using Verilog code to simulate a parallel adder of 48 numbers with 12 bits each.

Apparatus Required:
PC with XILINX Software

Procedure:
1) Start the XILINX project navigator by using Start program -> XILINX 2) Select the file menu in the select new project 3) Specify the project location and project name in the window and click Next 4) Select family (Sparton 3E), Device(XC 3S400), Package(TQ 144),Speed grade(-5), Simulator(ISE) from now project wizard window and click Next. Project will be displayed and click Finish to start the project 5) Right click on device name and select New Source 6) Select Verilog module in the new project wizard. Give suitable project name and click Next for the define module window. 7) Assign the require points in this window and click Next to write the Verilog code 8) Write the statement in the verilog code and save. 9) Check for the error using synthesis tools

10) After Synthesis again click on the device named and select new source 11) Select the test bench waveform and give suitable filename and finish 12) Duty cycle will appear for clock select then finish that one 13) Select the behavioural simulation from the scroll down list 14) Give input waveform signals and same

P a g e | 16

15) Double click on Simulate behavioral model for simulation 16) View the output according to the input

Block diagram of parallel adder

program:
module paralleladder(sum,carry); output[11:0] sum; output[3:0] carry; reg[11:0] sum; reg[3:0] carry; reg in1=12'b111100101100; reg in2=12'b110111000101; reg in3=12'b000100110011; reg in4=12'b010101101001; reg in5=12'b101001000111; reg in6=12'b011010001101; reg in7=12'b100111001111; reg in8=12'b111101110110; reg[12:0] temp=13'b1000000000000; reg[11:0] a1,a2,a3,a4,a5,a6,a7,a8; reg[14:0] c=15'b000000000000000; reg[15:0] res=16'b0000000000000000; reg[15:0] temp1=16'b1000000000000000; always@(temp,in1,in2,in3,in4,in5,in6,in7,in8,a1,a2,a3,a4,a5,a6,a7,a8,temp, c,res)

P a g e | 17

begin a1<=temp-in1; a2<=temp-in2; a3<=temp-in3; a4<=temp-in4; a5<=temp-in5; a6<=temp-in6; a7<=temp-in7; a8<=temp-in8; c<=a1+a2+a3+a4+a5+a6+a7+a8; res<=temp1-c; sum<=res[11:0]; carry<=res[15:12]; end endmodule

Result: Simulation of parallel adder was done successfully.

P a g e | 18

Expt no: Date :

SIMULATION OF SERIAL ADDER

Aim:
Write a program using Verilog code to simulate a serial adder of 8 numbers with 12 bits each.

Apparatus Required:
PC with XILINX Software

Procedure:
1) Start the XILINX project navigator by using Start program -> XILINX 2) Select the file menu in the select new project 3) Specify the project location and project name in the window and click Next 4) Select family (Sparton 3E), Device(XC 3S400), Package(TQ 144),Speed grade(-5), Simulator(ISE) from now project wizard window and click Next. Project will be displayed and click Finish to start the project 5) Right click on device name and select New Source 6) Select Verilog module in the new project wizard. Give suitable project name and click Next for the define module window. 7) Assign the require points in this window and click Next to write the Verilog code 8) Write the statement in the verilog code and save. 9) Check for the error using synthesis tools

10) After Synthesis again click on the device named and select new source 11) Select the test bench waveform and give suitable filename and finish 12) Duty cycle will appear for clock select then finish that one 13) Select the behavioural simulation from the scroll down list

P a g e | 19

14) Give input waveform signals and same 15) Double click on Simulate behavioral model for simulation 16) View the output according to the input

Block diagram of serial Adder

P a g e | 20

program:
module sadd(sum,carry); output[11:0]sum; output[3:0]carry; reg[11:0]sum; reg[3:0]carry; reg[11:0]in1=12'b111100101100;//F2C reg[11:0]in2=12'b110111000101;//DC5 reg[11:0]in3=12'b000100110011;//133 reg[11:0]in4=12'b010101101001;//569 reg[11:0]in5=12'b101001000111;//A47 reg[11:0]in6=12'b011010001101;//68D reg[11:0]in7=12'b100111001111;//9CF reg[11:0]in8=12'b111001110110;//E76 reg[12:0]temp=13'b1000000000000; reg[15:0]temp1=16'b1000000000000000; wire[11:0]sum1; reg[12:0]a1,a2,a3,a4,a5,a6,a7,a8; reg[2:0]car0=3'b000; wire[2:0]car1,car2,car3,car4,car5,car6,car7,car8,car9,car10,car11,car12; reg[14:0]c=15'b000000000000000; reg[15:0]res=16'b0000000000000000; always@(temp,in1,in2,in3,in4,in5,in6,in7,in8) begin a1<=temp-in1; a2<=temp-in2; a3<=temp-in3; a4<=temp-in4; a5<=temp-in5; a6<=temp-in6; a7<=temp-in7; a8<=temp-in8; end fhadd bitadd1(a1[0],a2[0],a3[0],a4[0],a5[0],a6[0],a7[0],a8[0],car0,sum1[0],car1); fhadd bitadd2(a1[1],a2[1],a3[1],a4[1],a5[1],a6[1],a7[1],a8[1],car1,sum1[1],car2); fhadd bitadd3(a1[2],a2[2],a3[2],a4[2],a5[2],a6[2],a7[2],a8[2],car2,sum1[2],car3); fhadd bitadd4(a1[3],a2[3],a3[3],a4[3],a5[3],a6[3],a7[3],a8[3],car3,sum1[3],car4); fhadd bitadd5(a1[4],a2[4],a3[4],a4[4],a5[4],a6[4],a7[4],a8[4],car4,sum1[4],car5); fhadd bitadd6(a1[5],a2[5],a3[5],a4[5],a5[5],a6[5],a7[5],a8[5],car5,sum1[5],car6); fhadd bitadd7(a1[6],a2[6],a3[6],a4[6],a5[6],a6[6],a7[6],a8[6],car6,sum1[6],car7); fhadd bitadd8(a1[7],a2[7],a3[7],a4[7],a5[7],a6[7],a7[7],a8[7],car7,sum1[7],car8); fhadd bitadd9(a1[8],a2[8],a3[8],a4[8],a5[8],a6[8],a7[8],a8[8],car8,sum1[8],car9);

P a g e | 21

fhadd bitadd10(a1[9],a2[9],a3[9],a4[9],a5[9],a6[9],a7[9],a8[9],car9,sum1[9],car10); fhadd bitadd11(a1[10],a2[10],a3[10],a4[10],a5[10],a6[10],a7[10],a8[10],car10,sum1[10], car11); fhadd bitadd12(a1[11],a2[11],a3[11],a4[11],a5[11],a6[11],a7[11],a8[11],car11,sum1[11], car12); always@(car12,sum1,temp1,c,res) begin c<={car12,sum1}; res<=temp1-c; sum<=res[11:0]; carry<=res[15:12]; end endmodule //fhadd(8 bit addition) module fhadd(i1,i2,i3,i4,i5,i6,i7,i8,cp,s,c); input i1,i2,i3,i4,i5,i6,i7,i8; input [2:0]cp; output s; output [2:0]c; reg s; reg [2:0]c; reg [3:0]s2; wire [3:0]s1; wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17,x18; wire ca1,ca2,ca3,ca4,ca5,ca6,ca7,ca8,ca9,ca10,ca11,ca12; wire ca13,ca14,ca15,ca16,ca17,ca18,ca19,ca20,ca21,ca22; hala ha1(i1,i2,x1,ca1); hala ha2(x1,i3,x2,ca2); hala ha3(x2,i4,x3,ca3); hala ha4(x3,i5,x4,ca4); hala ha5(x4,i6,x5,ca5); hala ha6(x5,i7,x6,ca6); hala ha7(x6,i8,s1[0],ca7); hala ha8(ca1,ca2,x7,ca8); hala ha9(ca3,x7,x8,ca9); hala hal0(ca4,x8,x9,ca10); hala hal1(ca5,x9,x10,ca11); hala hal2(ca6,x10,x11,ca12); hala hal3(ca7,x11,s1[1],ca13); hala hal4(ca8,ca9,x12,ca14); hala hal5(ca10,x12,x13,ca15); hala hal6(ca11,x13,x14,ca16); hala hal7(ca12,x14,x15,ca17); hala hal8(ca13,x15,s1[2],ca18);

P a g e | 22

hala hal9(ca14,ca15,x16,ca19); hala ha20(ca16,x16,x17,ca20); hala ha21(ca17,x17,x18,ca21); hala ha22(ca18,x18,s1[3],ca22); always@(s1,cp,s2) begin s2<=s1+cp; s<=s2[0]; c<=s2[3:1]; end endmodule // hala(2 bit addition) module hala(a,b,s,c); input a,b; output s,c; reg s,c; always@(a,b) begin s=a^b; c=a&b; end endmodule

Result:
Simulation of serial adder was done successfully.

P a g e | 23 Expt. no: Date :

SIMULATION OF TRAFFIC LIGHT CONTROLLER

Aim :
Write a program in Verilog HDL for 4-way traffic light control and simulate it using Xilinx ISE9.2i si mulator.

Apparatus Required:
PC with XILINX Software

Procedure:
1) Start the XILINX project navigator by using Start program -> XILINX 2) Select the file menu in the select new project 3) Specify the project location and project name in the window and click Next 4) Select family (Sparton 3E), Device(XC 3S400), Package(TQ 144),Speed grade(-5), Simulator(ISE) from now project wizard window and click Next. Project will be displayed and click Finish to start the project 5) Right click on device name and select New Source 6) Select Verilog module in the new project wizard. Give suitable project name and click Next for the define module window. 7) Assign the require points in this window and click Next to write the Verilog code 8) Write the statement in the verilog code and save. 9) Check for the error using synthesis tools

10) After Synthesis again click on the device named and select new source 11) Select the test bench waveform and give suitable filename and finish 12) Duty cycle will appear for clock select then finish that one 13) Select the behavioural simulation from the scroll down list 14) Give input waveform signals and same

P a g e | 24 15) Double click on Simulate behavioral model for simulation view the output according to the input

Block diagram 4way traffic light controller

P a g e | 25

Program:
module tlc(clk,reset,p1,p2,p3,p4,pl); input clk; input reset; output[4:0]p1; output[4:0]p2; output[4:0]p3; output[4:0]p4; output[3:0]pl; reg[4:0]p1; reg[4:0]p2; reg[4:0]p3; reg[4:0]p4; reg[3:0]pl; reg[5:0]sig; always @(posedge clk or negedge reset) begin if(reset==1'b0) begin p1<=5'b00100; p2<=5'b00100; p3<=5'b00100; p4<=5'b00100; pl<=4'b1111; sig<=6'b000000; end else begin sig<=sig+1; case(sig[5:0]) 6'b000000: begin p1<=5'b10011; p2<=5'b00100; p3<=5'b00100; p4<=5'b00100; pl<=4'b1111; end 6'b000100: begin p1<=5'b01000; p2<=5'b00100; p3<=5'b00100;

P a g e | 26 p4<=5'b00100; pl<=4'b1111; end 6'b001000: begin p1<=5'b00100; p2<=5'b10011; p3<=5'b00100; p4<=5'b00100; pl<=4'b1111; end 6'b001100: begin p1<=5'b00100; p2<=5'b01000; p3<=5'b00100; p4<=5'b00100; pl<=4'b1111; end 6'b010000: begin p1<=5'b00100; p2<=5'b00100; p3<=5'b10011; p4<=5'b00100; pl<=4'b1111; end 6'b010100: begin p1<=5'b00100; p2<=5'b00100; p3<=5'b01000; p4<=5'b00100; pl<=4'b1111; end 6'b011000: begin p1<=5'b00100; p2<=5'b00100; p3<=5'b00100; p4<=5'b10011; pl<=4'b1111; end 6'b011100: begin p1<=5'b00100;

P a g e | 27 p2<=5'b00100; p3<=5'b00100; p4<=5'b01000; pl<=4'b1111; end 6'b100000: begin p1<=5'b00100; p2<=5'b00100; p3<=5'b00100; p4<=5'b00100; pl<=4'b0000; end 6'b100100:sig<=6'b000000; default:begin end endcase end end endmodule

Result:
Thus the simulation of 4-way traffic light controller was completed successfully using Xilinx ISE9.2i

P a g e | 28 Expt.no: Date : Aim : Write a program in verilog HDL to mutliply two 8 bit numbers & simulate it on Xilinx ISE 9.2i.

SIMULATION OF 8- BIT MULTIPLIER

Apparatus Required:
PC with XILINX Software

Procedure:
1) Start the XILINX project navigator by using Start program -> XILINX 2) Select the file menu in the select new project 3) Specify the project location and project name in the window and click Next 4) Select family (Sparton 3E), Device(XC 3S400), Package(TQ 144),Speed grade(-5), Simulator(ISE) from now project wizard window and click Next. Project will be displayed and click Finish to start the project 5) Right click on device name and select New Source 6) Select Verilog module in the new project wizard. Give suitable project name and click Next for the define module window. 7) Assign the require points in this window and click Next to write the Verilog code 8) Write the statement in the verilog code and save. 9) Check for the error using synthesis tools

10) After Synthesis again click on the device named and select new source 11) Select the test bench waveform and give suitable filename and finish 12) Duty cycle will appear for clock select then finish that one 13) Select the behavioural simulation from the scroll down list 14) Give input waveform signals and same

P a g e | 29

15) Double click on Simulate behavioral model for simulation view the output according to the input

BLOCK DIAGRAM OF MULTIPLIER

PROGRAM: module mul_new_verilog(clk,addr,load,clear,data_in,calc,result); input clk,clear,calc,load; input addr; input [7:0]data_in; output reg [15:0]result; reg [7:0]ram[1:0]; always@(posedge clk) begin if(~clear) begin ram[0]=8'b0; ram[1]=8'b0; end else if(~load)

P a g e | 30 ram[addr]=data_in; end always@(posedge clk) begin if(~load) result={8'b0,data_in}; else if(~calc) result=multiply_8x8_2sC(ram[0],ram[1]); else result={8'b0,ram[addr]}; end function[15:0] multiply_8x8_2sC; input[7:0] a,b; reg[7:0] a_mag,b_mag; reg[14:0] y_mag; reg[14:0] y_neg; begin case(a[7]) 0:a_mag=a[6:0]; 1:a_mag=128-a[6:0]; endcase case(b[7]) 0:b_mag=b[6:0]; 1:b_mag=128-b[6:0]; endcase y_mag=a_mag*b_mag; if((a[7]^b[7])&(y_mag!=0)) begin y_neg=32768-y_mag[13:0]; multiply_8x8_2sC={1'b1,y_neg}; end else multiply_8x8_2sC=y_mag; end endfunction endmodule

RESULT: Verilog program for 8 bit multiplication was written & it was succcessfully simulated usng xilinx ise 9.2i simulator

P a g e | 31 Ex.pt no: Date :

DESIGN AND IMPLEMENTATION OF REAL TIME CLOCK WITH FPGA BOARD

Aim:
Write a program in Verilog HDL to implement Real Time Clock

Apparatus required:
pc with xilinx software FPGA kit Anna university card 1 FRC cables JTAG cable

Connections:
1) 2) 3) 4) 5) 6) connect FRC 5 of main board to CN2of card 1 connect FRC 10 of main board to CN1 of card 1 connect FRC 8 of main board to CN3 of card 1 connect FRC 4 of main board to CN4of card 1 connect FRC 1 of main board to CN8 of card 1 connect FRC 2 of main board to CN2 of card 1

procedure:
1) connections are made as above and implement the design into FPGA device. 2) Real time clock is on , all 7 Segment displays will be in on position and starts counting . 3) The time can be set by the switches & reset pin resets the clock

Program:
module real_time_clk_verilog(clk,clear,hour1,hour2,minute1,minute2,second1,second2,hour_A2, min_A1,sec_A0,load,data_in); input clk,clear; output reg[6:0]hour1,hour2,minute1,minute2,second1,second2; input load; input hour_A2,min_A1,sec_A0; input [7:0]data_in; reg clk_sec,clk,clk_msec; reg[7:0]sec,min,hr; integer timer_count1=0,timer_counter2=0; always@(posedge clk) begin if(timer_counter1==3999) begin timer_counter1=0; clk_msec=1'b1;

P a g e | 32 end else begin timer_count1=timer_count1+1; clk_msec=1'b0; end end always@(posedge clk_msec) begin if(timer_count2==999) begin timer_count2=0; clk_sec=1'b1; end else begin timer_counter2=timer_counter2+1; clk_sec=1'b0; end end always@(negedge clk_sec) begin if(~clear) begin sec=0; min=0; hr=0; end

else if(~load) begin if(hour_A2) begin if(hr[7:4]==4'b0010) begin if(hr[3:0]<4'b0100) hr=data_in; end else if(hr[7:4]<4'b0010) hr=data_in; else hr=8'b0;

P a g e | 33 end if(min_A1) begin if(min[7:4]<4'b0110) min=data_in; else min=8'b0; end if(sec_A0) begin if(sec[7:4]<4'b0110) sec=data_in; else sec=8'b0; end end else begin if(sec[3:0]==4'b1001) begin sec[3:0]=4'b0; if(sec[7:4]==4'b0101) begin sec[7:4]=4'b0; if(min[3:0]==4'b1001) begin min[3:0]=4'b0; if(min[7:4]==4'b0101) begin min[7:4]=4'b0; if(hr==8'b00100100) hr=0;

else if(hr[3:0]==4'b1001) begin hr[3:0]=4'b0; hr[7:4]=hr[7:4]+1; end else hr[3:0]=hr[3:0]+1;

P a g e | 34 end else min[7:4]=min[7:4]+1; end else in[3:0]=min[3:0]+1; end else sec[7:4]=sec[7:4]+1; end else sec[3:0]=sec[3:0]+1; end end

always@(sec) begin case(sec[3:0]) 4'b0000:second1=7'b1111110; 4'b0001:second1=7'b0110000; 4'b0010:second1=7'b1101101; 4'b0011:second1=7'b1111001; 4'b0100:second1=7'b0110011; 4'b0101:second1=7'b1011011; 4'b0110:second1=7'b1011111; 4'b0111:second1=7'b1110000; 4'b1000:second1=7'b1111111; 4'b1001:second1=7'b1111011; default:second1=7'b0; endcase end always@(sec) begin case(sec[7:4]) 4'b0000:second2=7'b1111110; 4'b0001:second2=7'b0110000; 4'b0010:second2=7'b1101101; 4'b0011:second2=7'b1111001; 4'b0100:second2=7'b0110011; 4'b0101:second2=7'b1011011; 4'b0110:second2=7'b1011111;

P a g e | 35 4'b0111:second2=7'b1110000; 4'b1000:second2=7'b1111111; 4'b1001:second2=7'b1111011; default:second2=7'b0; endcase end always@(min) begin case(min[3:0]) 4'b0000:minute1=7'b1111110; 4'b0001:minute1=7'b0110000; 4'b0010:minute1=7'b1101101; 4'b0011:minute1=7'b1111001; 4'b0100:minute1=7'b0110011; 4'b0101:minute1=7'b1011011; 4'b0110:minute1=7'b1011111; 4'b0111:minute1=7'b1110000; 4'b1000:minute1=7'b1111111; 4'b1001:minute1=7'b1111011; default:minute1=7'b0; endcase end

always@(min) begin case(min[7:4]) 4'b0000:minute2=7'b1111110; 4'b0001:minute2=7'b0110000; 4'b0010:minute2=7'b1101101; 4'b0011:minute2=7'b1111001; 4'b0100:minute2=7'b0110011; 4'b0101:minute2=7'b1011011; 4'b0110:minute2=7'b1011111; 4'b0111:minute2=7'b1110000; 4'b1000:minute2=7'b1111111; 4'b1001:minute2=7'b1111011; default:minute2=7'b0; endcase end

always@(hr) begin

P a g e | 36 case(hr[3:0]) 4'b0000:hour1=7'b1111110; 4'b0001:hour1=7'b0110000; 4'b0010:hour1=7'b1101101; 4'b0011:hour1=7'b1111001; 4'b0100:hour1=7'b0110011; 4'b0101:hour1=7'b1011011; 4'b0110:hour1=7'b1011111; 4'b0111:hour1=7'b1110000; 4'b1000:hour1=7'b1111111; 4'b1001:hour1=7'b1111011; default:hour1=7'b0; endcase end

always@(hr) begin case(hr[7:4]) 4'b0000:hour2=7'b1111110; 4'b0001:hour2=7'b0110000; 4'b0010:hour2=7'b1101101; 4'b0011:hour2=7'b1111001; 4'b0100:hour2=7'b0110011; 4'b0101:hour2=7'b1011011; 4'b0110:hour2=7'b1011111; 4'b0111:hour2=7'b1110000; 4'b1000:hour2=7'b1111111; 4'b1001:hour2=7'b1111011; default:hour2=7'b0; endcase end endmodule

P a g e | 37

UCF file(User Constraint File)

NETclearLOC=p137; NETclkLOC=p52; NETdata_in<0>LOC=p92; NETdata_in<1>LOC=p96; NETdata_in<2>LOC=p74; NETdata_in<3>LOC=p76; NETdata_in<4>LOC=p77; NETdata_in<5>LOC=p79; NETdata_in<6>LOC=p84; NETdata_in<7>LOC=p85; NEThour1<0>LOC=p95; NEThour1<1>LOC=p97; NEThour1<2>LOC=p98; NEThour1<3>LOC=p99; NEThour1<4>LOC=p104; NEThour1<5>LOC=p125; NEThour1<6>LOC=p122; NEThour2<0>LOC=p112; NEThour2<1>LOC=p116; NEThour2<2>LOC=p119; NEThour2<3>LOC=p118; NEThour2<4>LOC=p123; NEThour2<5>LOC=p131; NEThour2<6>LOC=p93; NEThour_A2LOC=p78; NETloadLOC=p83; NETmin_A1LOC=p82; NETminute1<0>LOC=p14; NETminute1<1>LOC=p15; NETminute1<2>LOC=p17; NETminute1<3>LOC=p18; NETminute1<4>LOC=p21; NETminute1<5>LOC=p23; NETminute1<6>LOC=p24; NETminute2<0>LOC=p129; NETminute2<1>LOC=p132; NETminute2<2>LOC=p135; NETminute2<3>LOC=p140; NETminute2<4>LOC=p1; NETminute2<5>LOC=p12; NETminute2<6>LOC=p13; NETsec_A0LOC=p80; NETsecond1<0>LOC=p32; NETsecond1<1>LOC=p35;

P a g e | 38 NETsecond1<2>LOC=p36; NETsecond1<3>LOC=p40; NETsecond1<4>LOC=p41; NETsecond1<5>LOC=p56; NETsecond1<6>LOC=p60; NETsecond2<0>LOC=p26; NETsecond2<1>LOC=p27; NETsecond2<2>LOC=p6; NETsecond2<3>LOC=p7; NETsecond2<4>LOC=p8; NETsecond2<5>LOC=p11; NETsecond2<6>LOC=p10

RESULT: Real Time Clock is designed with Verilog HDL code & it was implented with FPGA kit

P a g e | 39 Expt no: Date :

DESIGN &IMPLEMENTATION OF TRAFFIC LIGHT CONTROL WITH FPGA BOARD

Aim :
Write Verilog Code for 4 way traffic light control and implement the same with FPGA Board

Apparatus Required:
pc with xilinx software FPGA kit Anna university card 2 FRC cables JTAG cable.

Connections:
1) connect FRC 5 of main board to CN1of card2 2) connect FRC 1 of main board to CN2of card2 3)connect FRC 8 of main board to CN3 of card2

Procedure:
1) Download the program into FPGA kit. 2) Connect FRC connections as specified. 3) On card 2 ,load the timer count signals. 4) Set the clock, state of signals and output was verified.

P a g e | 40

Block diagram of four way traffic light controller

P a g e | 41 PROGRAM: module traffic_verilog(seg_1,R1,R2,R3,G1,G2,G3,Y1,Y2,Y3,PR,PG,clk,rst); output reg R1,R2,R3,G1,G2,G3,Y1,Y2,Y3,PR,PG; output reg[13:0]seg_1; input clk,rst; integer timer_count1=0,timer_count2=0; reg clk_msec,clk_sec: reg[4:0]count; reg[1:0]state=2'b0; always@(posedge clk) begin if(timer_count1++3999) begin timer_count1=0; clk-msec=1'b1; end else begin timer_count1=timer_count1+1; clk_msec=1'b0; end end always@(posedge clk_msec) begin if(timer_count2==999) begin if(timer_count2=0; clk_sec=1'b1; end else begin

P a g e | 42 timer_count2=timer_count2+1; clk_sec=1'b0; end end always@(poedge clk_sec) begin if(~rst) begin R1=1'b1;G1=1'b0;Y1=1'b0; R2=1'b1;G2=1'b0;Y2=1'b0; R3=1'b1;G3=1'b0;Y3=1'b0; state=2'b00; end else begin case(state) 2'b00://SIGNAL AT SIGNAL LIGHTS ONE begin if(count==5'b11100) begin G1=1'b0; R1=1'b0; Y1=1'b1; Y3=1'b0; G3=1'b0; end if(count==5'b11111) begin G1=1'b1; y1=1'b0; state=2'b01;

P a g e | 43 end else state=2'b00; end 2'b01://SIGNAL AT SIGNAL LIGHTS TWO begin if(count==5'b 11100) begin Y1=1'b1; G1=1'b0; R2=1'b0; Y2=1'b1; G2=1'b0; end if(count==5'b11111) begin R1=1'b1; Y1=1'b0; Y2=1'b0; G2=1'b1; state=2'b10; end else state=2'b01; end 2'b10://SIGNAL AT SIGNAL LIGHTS THREE begin if(count==5'b 11100) begin Y2=1'b1; G2=1'b0;

P a g e | 44 R3=1'b0; Y3=1'b1; G3=1'b0; end if(count==5'b11111) begin R2=1'b1; Y2=1'b0; Y3=1'b0; G3=1b1; state=2'b11; end else state=2'b10; end 2'b11://ALL SIGNAL HIGH TO ALLOW PEDESTRIALS TO CROSS begin if(count==5'b11100) begin Y1=1'b0; Y3=1'b1; G3=1'b0; end if(count==5'b11111) begin Y1=1'b0; R3=1'b1; Y3=1'b0; state=2'b00; end else

P a g e | 45 state=2b11; end endcase end end always@(count.state) begin if((state==2'b00)&&(count<=5'b11100)) begin PR=1'b0; PG=1'b1; end else begin PR=1'b1; PG=1'b0; end end always@(posedge clk_sec) begin if((clk_sec) begin count[4:0]=count[4:0]+1; //if(count[4:0==8'b10011) //count[4:0]=4'b00000; end end always@(count) begin case(count[40]) 5'b00001:seg_1=14'b11111100110000;//01

P a g e | 46 5b00010:seg_1=14'b11111101101101;//02 5'b00010:seg_1=14'b11111101111001;//03 5'b00100:seg_1=14'b11111100110011;//04 5'b00101:seg_1=14'b11111101011011;//05 5'b00110:seg_1=14'b11111101011111;//06 5'b00111:seg_1=14'b11111101110000;//07 5'b01000:seg_1=14'b11111101111111;//08 5'b01001:seg_1=14'b11111101111011;//09 5'b01010:seg_1=14'b01100001111110;//10 5'b01011:seg_1=14'b01100000110000;//11 5'b01100:seg_1=14'b01100001101101;//12 5'b01101:seg_1=14'b01100001111001;//13 5'b01110:seg_1=14'b01100000110011;//14 5'b01111:seg_1=14'b01100001011011;//15 5'b10000:seg_1=14'b01100001011111;//16 5'b10001:seg_1=14'b01100001110000;//17 5'b10010:seg_1=14'b01100001111111;//18 5'b10011:seg_1=14'b01100001111011;//19 5'b10100:seg_1=14'b11011011111110;//20 5'b10101:seg_1=14'b11011010110000;//21 5'b10110:seg_1=14'b11011011101101;//22 5'b10111:seg_1=14'b11011011111001;//23 5'b11000:seg_1=14'b11011010110011;//24 5'b11001:seg_1=14'b11011011011011;//25 5'b11010:seg_1=14'b11011011011111;//26 5'b11011:seg_1=14'b11011011110000;//27 5'b11100:seg_1=14'b11011011111111;//28 5'b11101:seg_1=14'b11011011111011;//29 5'b11110:seg_1=14'b11110011111110;//30 5'b11111:seg_1=14'b11110010110000;//31 //default:seg_1=14'b000000000000000;//off

P a g e | 47 endcase end endmodule UCF file(use constraint file)

NET clk LOC =p52; NET G1 LOC =p97; NET G2 LOC =p98; NET G3 LOC =p125; NET PG LOC =p132; NET PR LOC =p135; NET R1 LOC =p93; NET R2 LOC =104; NET R3 LOC =p129; NET rst LOC =p78; NET seg_1<6> LOC =p27; NET seg_1<5> LOC =p26; NET seg_1<4> LOC =p24; NET seg_1<3> LOC=P23; NET seg_1<2> LOC=P21; NET seg_1<1> LOC=P18; NET seg_1<0> LOC=p17; NET seg_2<6> LOC=p15; NET seg_2<5> LOC=P14; NET seg_2<4> LOC=p13; NET seg_2<3> LOC=p12; NET seg_2<2> LOC=P1; NET seg_2<1> LOC=p83; NET seg_2<0> LOC=P80; NET Y1 LOC =P95; NET Y2 LOC =P99; NET Y3 LOC=P122;

RESULT:

Thus the Verilog code for 4 way traffic controller was written and it was implemented on FPGA.