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HyperTransport Overview
HyperTransport (HT) is a state-of-art packet-based, high-bandwidth, scalable, low latency point-topoint interconnect technology that links processors to each other, processors to coprocessors and processors to I/O and peripheral controllers.

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HyperTransport is an open standard technology managed, promoted and licensed to the industry at large by the HyperTransport Consortium HyperTransports market-proven solidity and highly efficient protocol make it the ideal choice as chip-to-chip, board-to-board and chassis-to-chassis high-performance interconnect, successfully deployed in the widest rage of consumer, commercial and mission-critical applications, including gaming systems, embedded designs, networking equipment, personal computers, workstations, servers, and supercomputers.

HyperTransport Evolution and Milestones

Since its inception in 2001, the Consortium has pushed HyperTransport technology toward greater performance, features and architectural flexibility through new revisions of the HyperTransport link, the High Node Count specifications and a comprehensive portfolio of HT connector and cable standards. Below is a synthetic view of HyperTransport technology evolution.

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HyperTransport Technology Overview HyperTransport Technology White Papers HyperTransport Specifications Design Support Become a Member

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HT HT Connectors Specifications and Cables

Design Support

White Papers

Members Material

HT High Node Count

HyperTransport Link Specifications

Since its first HyperTransport 1.0 release in 2001, the HyperTransport standard has evolved to support higher speeds, increased functionality and scalability, while maintaining the same state-ofthe-art low latency capability. Thus, the HyperTransport standard has solidly maintained its lead as the industry's highest performance and most efficient interconnect. All HyperTransport Link specification releases are backwards-compatible with previous revisions to preserve the industry's long-term investments in the technology.

The chart below lists key features delivered by each release of the HyperTransport Link specification.

HyperTransport Link Specifications Features Summary

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HyperTransport 3.1 HyperTransport 3.0 HyperTransport 2.0 HyperTransport 1.x

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2012 HyperTransport Consortium

HT HT Connectors Specifications and Cables

Design Support

White Papers

Members Material

HTX Product Validation

HyperTransport Design Support

The HyperTransport Consortium offers a complete array of support tools and services intended to simplify the design effort and minimize the time-to-market of HyperTransport products. Central to the Consortiums design support strategy are:

Technical Support Database

HyperTransport product developers can access an extensive technical support documentation and software tool database available to members of the HyperTransport Consortium. The online database includes HyperTransport specifications, design and test guides, compatibility checklists, as well as simulation and compliance tools that facilitate and expedite HyperTransport product design. For details on the available documentation and software platforms please click on the PDF link below. HTC Technical Support Database To access, review and download the technical support material, simply click on the Members LogIn button above, sign-in using your personal log-in information and click on Documentation. If your organization is a member of the HyperTransport Consortium and you have not yet obtained log-in access to the HyperTransport Consortium member-only database, just click on the Members Log-In button above and fill up the request form. Your temporary password and ID will be emailed to you upon the Consortiums validation of your applications. If your company is not an HyperTransport Consortium member and would like to become one, please click the yellow Become a Member button above for details and guidelines on how to apply for membership.

HyperTransport Center of Excellence (HTCE)

HTCE is the premier source of HyperTransport testing and validation services to HyperTransport product developers. The center, sponsored by AMD and the HyperTransport Consortium, is lead by world-renowned team of technology experts and researchers of the University of Heidelberg, Germany and it is located on the campus of the University of Mannheim, also in Germany. For more details on HTCE and HTCEs services, please click on the HT Center of Excellence button above.

HTX Product Validation

The HyperTransport Center of Excellence (see above) offers test and validation services on HTX products and designs to the industry at large. For details please click on the HTX Product Validation button above.

Reference Designs and Development Tools

A host of HyperTransport reference design platforms and development tools are available through the HyperTransport Consortium and the HyperTransport Center of Excellence (see above) to enable rapid design and prototyping of HyperTransport-based and HTX-based products. For more details, please click on the Reference Design button above. HOME | TECHNOLOGY | PRODUCTS | NEWS & EVENTS | CONSORTIUM | MEMBER LOGIN | BECOME A MEMBER | CONTACT US | SEARCH 2012 HyperTransport Consortium

HyperTransport 3.1 Specification

The HyperTransport 3.1 specification, has been released on August 18, 2008. It delivers 23% of bandwidth improvement and proportionally lower latency capability compared to HyperTransport 3.0. HyperTransport 3.1 maintains the same advanced architectural, power management and protocol features of HyperTransport 3.0.

HyperTransport 3.0 Features Plus:

2.8 GHz, 3.0GHz and 3.2 GHz Clock Rates

o o o

51.2 GB/s Max Aggregate Bandwidth (32-bit) 25.6 GB/s (204.8 Gb/s) Max Bandwidth per Unidirectional HT Link (32-bit) 6.4 GT/s (3.2 GHz x 2 DDR) per Lane

State-of-the-Art Technology - Investment Preservation

With the clock rate and bandwidth capabilities introduced with the HyperTransport 3.1 Specification, the Consortium reinforces its mission of keeping HyperTransport specifications comfortably ahead of industry requirements, thus safeguarding long term investments in the technolog

yperTransport 3.0 Specification

HyperTransport 3.0 is the latest release of the HyperTransport specification introduced in April 2006. The new HT 3.0 standard nearly doubles the clock speed and bandwidth of HT 2.0 while delivering a full slate of powerful scalability and power management features.

HyperTransport 2.0 Features Plus:

1.8 GHz, 2.0 GHz, 2.2 GHz, 2.4 GHz and 2.6 GHz Clock Rates
o o o

41.6 GB/s Max Aggregate Bandwidth (32-bit) 20.8 GB/s (166.4 Gb/s) Max Bandwidth per Unidirectional HT Link (32-bit) 5.2 GT/s (2.6 GHz x 2 DDR) per Bit Each unidirectional HT link reconfigurable in real time and under software control from any given bit width i.e. 32-bit, 16-bit, 8-bit, 4-bit - to two independent unidirectional links having half the bit width of the original link Auto-Configuration Asymmetry Support

Link Splitting (Un-Ganging) Optional

o

o o

Unidirectional HT links within each HT port can have different bit width

o o

Powerful scalability feature - doubles the number of per-product HT ports More HT ports particularly useful in Symmetric Multi-Processing (SMP) topologies HT link clock rate and bit width constantly and dynamically adjusted for best power consumption and given workload. Real-time decision-making and adjustments handled by HT control logic via link traffic load monitoring transparently to operating system and end-user applications Rapid Pause-Change-Start Transmitter:

Enhanced Power Management

o

DC Operating Mode Enhancements

o

Enhanced Training Pattern Tolerates Multi-Bit Skew Added Scrambling Enables Rx Phase Alignment Retained DDR Clock Enabled Use of Rx Equalization Support for Multi-Bit Skew Through Clock-Based Rx Phase Alignment

Receiver:

AC Operating Mode Optional

o o o

Capacitive Coupling (vs. Direct Coupling of DC Mode) 8B/10B Clock Recovery Triples HTs Max Link Length to 1m/3ft at Max Clock Rate

Cables, Backplanes, Chassis-to-Chassis Applications

o o

Higher Latency than DC Mode Enabled when Needed Best of Both Worlds (DC and AC Mode) Coupling Capacitors Auto-Detect sets HT Link to AC mode Same HT device configurable in DC Mode for short runs and AC mode for long runs HT devices added or removed without disrupting product/system operation

DC /AC Auto-Configuration
o o

Hot Plugging
o

Defined Link Termination Methods Transaction Termination Behaviors Sync Flood Isolation Link Training Times

o o

Parameter Configuration Mechanisms "Always-up" capability for backplane and mission-critical applications

100% Backward Compatibility

Runs in HT 1.x and 2.0 Mode when New Features Not Enabled

Boot-Up Auto-Configuration

HT Link Set to Highest HT Specification Revision Supported by all HT Link Devices

State-of-the-Art Technology - Investments Preservation

These new HyperTransport 3.0 features and capabilities dramatically reinforce HyperTransport's role as the most flexible, most scalable, highest performance and lowest latency processor-toprocessor and processor-to-peripheral interconnect technology the market has to offer, vastly extending its overall application latitude and market opportunity. In addition, by preserving full backward compatibility with prior HyperTransport specifications, HyperTransport 2.0 continues to safeguard and maximize the industrys legacy investments in the technology.

HyperTransport 2.0 Specification

The HyperTransport 2.0 specification, released in February 2004, introduced a 75 percent clock rate and bandwidth improvement over HyperTransport 1.x, as well as additional features and capabilities.

HyperTransport 1.x Features Plus:

1.0 GHz, 1.2 GHz, 1.4 GHz, 2.4 GHz Clock Rates
o o o

22..4 GB/s Max Aggregate Bandwidth (32-bit) 11.2 GB/s (89.6 Gb/s) Max Bandwidth per Unidirectional HT Link (32-bit) 2.8 GT/s (1.4 GHz x 2 DDR) per Bit

PCI Express Mapping De-Emphasis

o

Ensures proper signal integrity despite the dramatic clock rate increase Runs in HT 1.x Mode when Higher Clock Rates Not Used Boot-Up Auto-Configuration

100% Backward Compatibility

o o

HT Link Set to Highest HT Specification Revision Supported by all HT Link Devices

In addition, by preserving full backward compatibility with prior HyperTransport specifications, HyperTransport 3.0 continues to safeguard and maximize the industrys legacy investments in the technology.

HyperTransport 1.x Specifications

HyperTransport 1.1 Specification (DirectPacket)

HyperTransport DirectPacket Release 1.10 defines four major features to the HyperTransport 1.x technology specification:

Native Packet Handling

o o o

User packets move efficiently between devices without DMA loops Seamless mix of load-store and packet bus functionality Load-store operation with no added overhead Direct communication between HT devices

Pier-to-Pier Routing
o

Example: framer to security processor

16 Additional Virtual Channels

o o o

Optimized for streaming Posted-Write only with dedicated flow control End-to-End flow control for highly channelized applications

Example: channelized framer interface

Robust Error Retry Protocol

o o

For high-reliability, mission-critical applications Future-proof - supporting faster electrical links

Such innovative DirectPacket capabilities make HyperTransport the most efficient means to stream packets with minimum overhead and the ideal technology for enhancing performance in high speed streaming data with SPI-4, XAUI, and other communications technologies. HyperTransport DirectPacket features bring communications-oriented, packet-handling capabilities to otherwise standard processor-centric computing systems. HyperTransport 1.1 Specification

HyperTransport 1.05 Specification

The HyperTransport 1.05 Specification adds four major features to the previous HyperTransport 1.03 release:

HyperTransport Link Switch Function

o

Enables connection of virtually unlimited numbers of HyperTransport devices Simplifies connection to PCI-X 2.0 subsystems Supports error indications and device configuration messages up to 4K bytes Supports PCI-X 2.0 128-byte burst messaging

Enhanced PCI-X 2.0 Inter-Working

o o o

Extended Transaction Concurrency

o o

Allows up to 128 outstanding requests Eliminates potential bottlenecks in networking applications Extended from 40-bit Supports larger address topologies required by large server and networking applications Backward compatible with earlier generation addressing schemes

Extended 64-bit Addressing

o o o

HyperTransport 1.05 Specification

HyperTransport 1.04 Specification

The HyperTransport 1.04 Specification introduces feature extensions, clarifications and errata fixes to the original HyperTransport 1.03 Release:

Revision ID Capability
o

For tagging functions as existing within an HT device Simplifies connection to PCI-X 2.0 subsystems How to prevent Documented in Appendix C

PCI-X Ordering and Command Mapping

o

Potential Deadlocks Prevention

o

HyperTransport 1.04 Specification

HyperTransport 1.03 Specification

HyperTransport 1.03 is the original HyperTransport I/O Link specification released by the HyperTransport Consortium in October 2001. HT 1.03 defines and describes the input/output link protocol and electrical interface for the HyperTransport interconnect technology. The document is divided into two main parts: Protocol and Electrical. The Protocol part includes information on HyperTransport technology signals, packets, commands, interrupts, configuration accesses, address map, error handling, clocking, and initialization. The Electrical part includes information on I/O power supply, AC and DC characteristics, transfer timing, and phase recovery timing.

Comprehensive HyperTransport Product Ecosystem

During its past seven years of performance leadership and technology solidity, HyperTrasport has continued to accumulate widespread industry adoption. At present, HyperTransport technology empowers an ever expanding variety of commercial platforms and products that cater to the entire design-to-solution technology food chain, with a true full circle value delivery.

As a processor-native interconnect, HyperTransport has been integrated in a large number of CPUs and processor families from multiple manufacturers. HT-powered processors serve a wide variety of performance-intensive applications, including x86 computing, graphics and 3D rendering, security processing, real-time data/packet analysis, media processing, application-specific acceleration and co-processing.

HyperTransport has been adopted by technology leaders for the widest range of product applications.

By clicking on the buttons above you can easily sort through and review the profile of HyperTransport-enabled products commercially available. While we strive to keep this product list updated at all time, due to fast market dynamics not all HyperTransport-based products may be included here. If you dont find HyperTransport-enabled products that you believe should be included in these product pages, please let us know by clicking on the "Contact Us" button above. We will gladly provide you with the information you need and any appropriate manufacturer contact.