An FPGA-Based Digital Modulation Signal
Generator with Fading Channel Emulation
Wei-Ming Chen, Chen-Yu Chen, Yu-Lun Chiu, and Jeng-Kuang Hwang*
Department of Communication Engineering, Yuan-Ze University
Chungli City, Taoyuan, Taiwan
*
E-mail: eejhwang@saturn.yzu.edu.tw
Abstract — In this paper, an FPGA-based digital
modulation signal generator with fading channel effect is
presented for basic experimental usage. Instead of using
off-the-shelf but costly instruments to test various
communication systems, this FPGA-based signal generator
is more cost-effective. We use Altera Stratix EP1S25 DSP
development board as the hardware platform, which can be
rapidly and flexibly re-configured and re-programmed by
modifying its Verilog-HDL code. Moreover, based on the
software defined radio concept, some built-in functions
have been included, such as three switchable basic digital
modulations (BPKS/QPSK/8PSK), poly-phase square-root
raised cosine pulse shaping, AWGN generator, complex
Rayleigh flat fading channel, and I/Q modulator based on a
reduced-memory DDFS. Some implementational and
measurement results are also included.
Key Words — FPGA-based system, poly-phase
interpolator filter, AWGN generator, fading channel
emulator, reduce-memory DDFS.
I. INTRODUCTION
Recently, highly configurable hardware platform is
often adopted for prototyping and realizing the digital
communication infrastructure rapidly. As the complexity
of VLSI chips dramatically improved in the last decade,
more and more functions in the communication receiver
can be shifted from analog to digital domain. While there
are many alternatives available for implementing the
various receiver functions, FPGA provides an attractive
platform for many of these tasks for reasons of
performance, power consumption and configurability.
In general, the generation of communication signals is
usually accomplished by either software-based or
hardware-based emulations. Comparing these two
different methods, hardware-based emulation is more
efficient and faster than software-based one [1]. For a
good choice of hardware experimental platform, the
aforementioned FPGA platform is highly flexible for
communication system design and costs much less than
those high-priced signal generation instruments.
Moreover, in realistic testing of wireless system
performance, the signal fading effect is inevitable.
However, very few channel emulators are off-the-shelf,
and they are usually very expensive. Especially, in the
fast-changing communication technologies, a modifiable
communicational transmitter is essential.
In this paper, we follow the top-down design flow to
efficiently design and implement a useful signal
generator for communication system prototyping and
testing. Based on the concept of software defined radio
(SDR), we develop an FPGA-based signal generation
platform which not only includes the fading channel
effect, but its built-in functions can also be easily and
rapidly modified by varying the firm-ware in Verilog-
HDL code. Thus it can serve as an affordable
general-purpose SDR transmitter platform for
experimental usage, and allows us to evaluate the
performance of a newly developed communication
systems efficiently and in a short time.
II. SYSTEM DESIGN FLOW
In considering a passband signal generator with fading
channel effect, some signal generator instruments are
often employed. A famous solution is the R&S vector
signal generator SMIQ [2]. Based on the design concepts
behind these signal generator instruments, we use the
system block diagram shown in Fig.1 to introduce the
steps of implementation.
To generate passband digital modulation waveform
with fading channel effect, there are three main portions
in generator system, which are digital modulation coders,
baseband fading simulator, and IQ modulator. Before
implementing these portions on FPGA, the whole system
parameters can be chosen and verified in Matlab first.
Then we begin to write the the Verilog-HDL code for the
Altera Stratix-EP1S25 DSP development board [3],
which is equipped with two output D/A channel at the
highest speed of 165 samples/sec. Although this board is
usually used as baseband processor, it can also generate
an IF signal with a center frequency under 10 MHz.
In our example system, there are three digital
modulation modes which can be switched to generate
corresponding baseband I/Q waveforms. In other words,
it maps the input bit sequence to different symbol
formats of BPSK, QPSK, 8PSK signal constellations, or
any other wanted modulation format. In the baseband
fading simulator, the Uniform and Gaussian random interpolate the upsampled-by-I and zero-inserted symbol
number generators (RNG), and Doppler filter are sequence. To reduce the required computational load, an
included to emulate the flat fading effect. After applying efficient poly-phase structure [4] is exploited to trade the
the channel effect to baseband I/Q signals, we employ a low-speed processing elements for costly, high-speed
reduced-memory Direct Digital Frequency Synthesizer elements. The poly-phase structure of SRRC filter is
(DDFS) to generate a pair of high-frequency sinusoidal derived in the following.
(sin/cos) waves, in order to modulate the baseband signal Fig.3 illustrates the equivalent block diagram of
to the specific carrier frequency, which are adjustable poly-phase interpolation filter. The over-sampling rate is
with numerically controlled oscillator (NCO). I, which means I-1 zeros are inserted between two
adjacent symbols. Let x(n) is the signal from symbol
Digital I ch. mapper output, then the zero-padded signal v(m) is
Modulation Baseband
Passband ⎧ x ( n) for m = nI
Coder fading cos (ωt ) ∑
signal
v ( m) = ⎨ (1)
(BPSK,QPS simulator ⎩0 otherwise
K, 8PSK...) Q ch.
Note that the index m is for the high-rate samples. The
sin (ωt ) FIR filter hI(m) with length N = P ⋅ I is the impulse
IQ modulator response of the SRRC filter. When v(m) passes through
(DDFS) the pulse shaping filter, the output is
y (m) = v(m) ∗ hI (m)
Fig.1 System block diagram. N −1
(2)
= ∑ v(m − l ) ⋅ hI (l )
To verify the results of FPGA implementation, the l =0
Verilog-HDL codes are programmed in Quartus II on the If we let l = iI +k, eq(2) can be rewritten as
Stratix DSP development board, and the simulation
I −1 P −1
waveforms will be back annotated to Matlab S/W and
compared with algorithmic simulation results. The D/A y (m) = ∑∑ v(m − (iI + k )) ⋅ hI (iI + k ) (3)
and digital outputs from the FPGA board are observed k = 0 i =0
and recorded by digital oscilloscope (Tektronix TDS
From (1), only one index of k leads to non-zero term.
3032B) and logic analyzer (Tektronix TLA 5203).
I −1 P −1

III. GENERATION OF THE UNFADED I/Q WAVEFORMS y (m) = ∑∑ x(n − i) hI (iI + k )

k =0 i = 0
(4)
A. The switchable digital modulation I −1

By using a 2-bits dip-switch, the three digital

= ∑ x(n) ∗pk (n)
k =0
modulation schemes of BPSK, QPSK and 8PSK can be
chosen to change the symbol mapping schemes. Fig. 2 For each new input sample x(n), I samples of y(m) are
shows the relationship between mapping schemes and output in turn by the I sub-filters. If the length of the
dip-switch pattern. original filter is N, then the length of each sub-filter is
00 P= N I . And the kth sub-filters are
pk (i ) = hI (iI + k ) (5)
BPSK
We take the 64-taps SRRC filter for an example. By
setting the I=8, the poly-phase interpolation filter is
10 constructed by 8 sub-filter and each filter has 64/8 = 8
Bits Symbols
coefficients. Table.1 shows the coefficients of each
QPSK sub-filter.
x(n)
p0 (m)
11
8PSK x(n)
Insert
v(m) y(m)
p1 (m)
SRRC hI(m) y(m)
I-1 zeros

Fig.2 The switching of modulation schemes.

#
pI −1 (m)
B. The Poly-phase interpolator filter
In order to suppress the spectrum side-lobe under Fig.3 Equivalent model of the poly-phase
the zero-ISI condition, square root raised cosine filter interpolation filter
(SRRC filter) is adopted as the pulse shaping filter. This
filter is also used as a low-pass interpolation filter to
 Table.1 The coefficients of each sub-filter which are uniformly distributed over [0,1].
2. Use look-up table to obtain:
Sub-filter
coefficient
SRRC filter coefficient f ( x1 ) = − ln( x1 ) (6)
p0 (m) h0 h8 h16 h24 h32 h40 h48 h56 g ( x2 ) = 2 cos(2π x2 ) (7)
p1 (m) h1 h9 h17 h25 h33 h41 h49 h57 3. Generate a Gaussian variables
p2 ( m) h2 h10 h18 h26 h34 h42 h50 h58 n = f ( x1 ) g ( x2 ) ; (8)
p3 (m) h3 h11 h19 h27 h35 h43 h51 h59 Thus we design the block diagram of WGNG as in Fig.
p4 ( m) h4 h12 h20 h28 h36 h44 h52 h60 5. In this structure, five linear feedback shift registers
p5 (m) h5 h13 h21 h29 h37 h45 h53 h61 (LFSRs) are used to generate the output bits of the
p6 (m) h6 h14 h22 h30 h38 h46 h54 h62 random number generators. Then x1 and x2 which are
uniform distributed over [0,1] are fed to two different
p7 ( m) h7 h15 h23 h31 h39 h47 h55 h63
look-up tables respectively. The two different tables
represent the function which will transfer x1 and x2 to
IV. EMULATION OF THE FLAT FADING EFFECT f(x1) and g(x2). In the end, the two random values will be
multiplied together to get the Gaussian random value in
As is shown in Fig. 4, there are two parts in typical the output terminal.
time-varying flat fading channel emulator, and we can
realize this structure step by step. First, we design a B. Doppler Filter
Rayleigh fading process emulator which consists of
The power spectral density below can represent the
Gaussian RNG and Doppler filter. Then we use two such
effect of Doppler.
independent fading emulator to generate the processes
fI(t) and fQ(t). Then we apply them to the original I/Q ⎧ 1
⎪ f < fm
waveforms i(t) and q(t) in terms of a complex S ( f ) = ⎨ 1 − ( f / f m )2 (9)
multiplication. In the following, the methods and ⎪0
⎩ otherwise
algorithms for realize White Gaussian Noise Generator
(WGNG) and Doppler filter will be stated respectively. Thus we can derive the required filter transfer function
H(f) as
i(t) q(t)
⎪⎧[1 − ( f / f m ) ]
2 −1/ 4
Fading Emulator f < fm
H( f ) = ⎨ (10)
⎪⎩0 otherwise
White Gaussian Doppler filter Finally, we can get the impulse response h(t) of the
Noise Generator (baseband) Doppler filter in time domain by taking the inverse DFT
fI(t)
Complex of H(f). The filter coefficients are passed from the PC
Multiplication
and then stored in a ROM area in the FPGA.
White Gaussian Doppler filter
Noise Generator (baseband)
fQ(t) LFSRs A

Random
x1 (Table1) f(x1)
ifad(t) qfad(t) LFSRs B ‧ Number LUT
‧ Generator
‧ Sqrt(-ln(U1))
A
Fig.4 Rayleigh fading channel emulator.
n=f g
LFSRs C
A. White Gaussian Noise Generator
In designing a WGNG, here are some important points Random
(Table2)
LFSRs D
we should keep in mind : ‧ Number LUT
‧ Generator
1. The statistical characteristics of the Gaussian ‧
B
x2 Sqrt(2)*cos(2pU2) g(x2)
random number should be white or nearly white.
LFSRs E
2. We should use enough number of bits to represent
the output signal with sufficiently high resolution.
3. The structure and the algorithms of the emulator Fig.5 white Gaussian noise generator (WGNG).
should be simple.
4. The system should be stable, especially when it is
operated in high speed. V. REDUCED-MEMORY DIRECT DIGITAL FREQUENCY
SYNTHESIZER
In this paper we use the Box-Muller method [5] to To modulate the baseband signal to passband, a high-
design our WGNG. The algorithm of the Box-Muller precision and variable-frequency direct digital frequency
method is shown below. synthesizer (DDFS) is designed and implemented. The
digital nature of the DDFS has the advantages of
1. Generate two independent random values x1 and x2,
implementational easiness, fast switching in frequency, (c) Use the phase address x to retrieve the value of
and flexibility. Thus, it is used extensively in digital (sinx-x) stored in the ROM.
communication systems. The traditional DDFS consists (d) By using the 1st-MSB, the polarity of the output
of a phase accumulator and a Look-Up-Table which voltage is set.
stores a sine or cosine waveform [4]. Assume that the Before output to D/A, an inverter is inserted to invert
input to phase accumulator is an N-bits control codeword the MSB bit, which gives the offset binary representation
WCTRL, and the resolution of the output sample is B bits, for the Analog Devices DAC904 D/A converter.
then for a conventional DDFS, the required ROM size is
2N×B bits. Besides, the output frequency is
Wcntl (11)
f out = fCLK
2N
where fCLK is the clock frequency. In our FPGA board,
we set fCLK=80MHz, N=14bits, and B=14bits, then the
frequency resolution is
fCLK (12)
Δf = = 4.8828 ×103 Hz
2N
With a voltage swing from -1V to +1 V, the amplitude
resolution is
2
ΔR = = 1.2207 × 10−4 (V) (13)
2B Fig. 6 The dynamic range of sin(x) - x.
14
The total used ROM size is 2 ×14=229,376 bits. 2 bits 11 bits
1
bits
To reduce the ROM size without losing frequency 0
resolution, we exploit the following two methods [6]:
#
1. By using the property of quarter-wave symmetry, it
only needs to store a quarter of one cycle of the sine 212 − 1
ROM address

Reduced ROM region

or cosine waveform instead. This method saves 75%
of ROM memory. To obtain a complete cycle, the # ：by Quarterwave Symmetry
：by reduced dynamic range
first two MSB bits of the phase accumulator output #
should be used as the two (+,-) control lines to ：Remain for method #1
unfold the symmetry of sinusoidal waveform in both # Remained ROM region
the time and amplitude. ：LUT storage region
2. Note that the sine function can be synthesized as the
214 − 1
summation of two functions, i.e.
sin x = (sin x − x) + x (14) Fig. 7The reduced ROM regions.
and the phase accumulator output is simply x. Then
1st MSB

instead of storing sinx, we choose to store (sinx –x) (b)

(c)

in ROM. However, the dynamic range of the data M-2

sin(2ٛWCTRLk)
2nd MSB

reduces from 2V (+1~-1) to 0.2083 V, as is shown in Frequency Control

WCTRL
N
R
R
SIN ROM
M-2
M-1 M

Fig.6. In this way, the required number of bits of the

M M-2
(d)

COS ROM
cos(2ٛWCTRLk)
stored sample codeword can be reduced to attain the (a)
Phase accumulator
M-2
M-1

same resolution.
M
M-2

Recalling the Eq.(13) for the relationship between B

and ΔR, the new codeword length becomes
⎛ 0.2083 ⎞ (15)
B ' = log 2 ⎜ ⎟ = 10.7367 ≈ 11 bits
⎝ ΔR ⎠
It is shown that almost 3 bits can be saved for each
codeword with the same ΔR. Therefore, the reduced
ROM size in our implementation is 214-2×11= 45,056 bits.
As illustrated in Fig.7, the new design cuts off about
80% memory usage, as compared to the original design.
Fig.8 is a circuit diagram of this reduced-memory DDFS
structure, which includes the following four portions:
(a) The phase accumulator which is controlled by a
control codeword WCTRL.
(b) Using the 2nd-MSB, the phase address x is folded
beyond π/2.
Fig. 8 The structure of Reduced-Memory DDFS.
VI. RESULT OF THE IMPLEMENTATION
To verify the implementation results on FPGA, the
D/A and digital-pin outputs of some system blocks are
observed by oscilloscope and logic analyzer. Fig.9 shows
the aforementioned FPGA-based platform for
modulation signal generator and associated testing
equipments. Fig. 10 shows the digital outputs of the
8-PSK observed by logic analyzer. The white Gaussian
noise is passed through the Doppler filter where the
maximum Doppler frequency fm is 100 Hz. Fig.11 shows
the PSD of the output signal, and Fig.12 shows the
envelope fading function of one fading emulator. And the
cosine/sine output waveforms of the DDFS are measured
by an oscilloscope, as is shown in Fig.13.

Fig. 13 The observations of oscilloscope of the DDFS.

(a) sine wave ; (b)cosine wave.
Fig. 9 The FPGA-based experimental platform.
VII. CONCLUSIONS
In this paper, we have presented the design and FPGA-
implementation of a practical communication signal
generator, whose modulation schemes is switchable, and
flat Rayleigh fading channel effect is included. As a
result, our system can be a cost-effective and flexible
substitute for those high-priced communicational
instruments. Besides, with the concept of software
Fig.10 The digital outputs of 8PSK observed by logic defined radio (SDR), our solution can keep up with those
analyzer. newly proposed communicational specifications by
simply re-programming the Verilog-HDL code. Hence, it
is a very efficient approach to transmitter-side
prototyping.

REFERENCES
[1] M. Courtoy, “Rapid System Prototyping for Real-time
Design Validation,” Proc. Ninth International Workshop
on Rapid System Prototyping, pp. 108-112, 1998.
[2] Rohde&Schwarz, “SMIQ03B Vector Signal Generator
Operating Manual Volume 1“,2001.
[3] Altera : Stratix EP1S25 DSP Development Board Data
Sheet, May 2003, ver.1.4.
[4] Jeffrey H. Reed, Software Radio: A Modern Approach to
Radio Engineering, Prentice Hall PTR, 2002.
Fig. 11 The PSD of the Rayleigh fading process [5] A. Gazel, E. Boutillon, J.L. Danger, G. Gulak, “Design
resulted from the Doppler filter. and performance analysis of a high speed AWGN
communication channel emulator”, IEEE PACRIM
5
conference, Victoria, B.C., Canada, Aug. 2001.
0 [6] Charles Chien: Digital Radio System on A Chip – A
System Approach, Klumer Academic Publishers, 2001.
-5

-10
Volt(dB)

-15

-20

-25

-30
0.32 0.34 0.36 0.38 0.4 0.42 0.44 0.46 0.48 0.5
time(sec)

Fig. 12 The envelope of the fading process.