DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING INDIAN INSTITUTE OF TECHNOLOGY, MADRAS 600 036 Class : B.

Tech Sem : IV Course: CS 2600 - COMPUTER ORGANIZATION Date: Feb. 22, 2012 Due: Mar. 5, 2012

Assignment-2 ---------------------------------------------------------------1. Work-out steps to execute the following instructions showing signals that can be active at the same time in a clock cycle Data transfer instructions: MOV (R0), R1 MOV R2, -(R3) Arithmetic-logic instructions: ADD R5, R4 CMP R6, R7 One operand instructions: CPL R3 INC R2 Control transfer instructions: JV Offset ;Offset relative to PC within the instruction word ;Conditional jump when overflow flag is set JMP Direct address ;Direct address specified in the following word CALL Direct address ;Direct address specified in the following word RET Show typical digital logic circuit to implement registers in the CPU with necessary control signals and connections to the bus Design a suitable hardwired control unit for the CPU showing logic circuit to implement all relevant control signals for the instructions and addressing modes given above Implement logic circuit to handle 'Memory Function Complete' (MFC) signal from memory controller that extends CPU clock cycles during Memory transactions 5. Determine the maximum clock frequency that may be used in your design of the CPU when using digital logic technology with the following parameters: Flip-flop: Setup time (minimum): 2 nS; Hold time (minimum): 0 nS; delay in output after clock edge (maximum): 1 nS Maximum propagation delay in logic gate: 1 nS Tri-state buffer: control-to-output delay (maximum): 2 nS; input-to-output delay (maximum): 1 nS; delay due to load on output (maximum): 0.05 nS per gate input

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ALU propagation delays: input-to-output (maximum): 4 nS; control-to-output (maximum): 1 nS Instruction decoder delay: input-to-output (maximum): 3 nS

Determine the number of clock cycles required to execute instructions given above for the following memory speed assumptions: i. Fast external memory that can complete any read or write within one CPU clock cycle (MFC is generated well within one clock period) ii. Memory and memory controller with the following parameters: Memory controller generates MFC 25 nS after MR or MW signal is active to ensure correct read and write cycles

Notes and Assumptions: a. CPU with single-bus 32-bit data-path b. Register-set: R0 through R7, PC, LINK, Y, Z, IR c. CPU Architecture RISC Addressing modes relevant only for data moves with respect to memory Arithmetic and Logic instructions are confined to register operands d. 32-bit Arithmetic Logic Unit (ALU) with two input legs A and B and one output leg R e. Condition code flags used and affected by ALU are: Negative (N), Zero (Z), Overflow (V) and Carry (C) f. Byte organized memory little-endian g. Synchronous digital logic circuit with a single periodic clock source driving all clock input h. Instruction decoder generates decoded output for each instruction i. Instruction decoder also provides decoded output for different addressing modes of source and destination