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SEER AKADEMI_SDM

Threshold of the MOSFET


At different lengths
M.Sharan Kumar Goud K.Naveen Kumar Chandan Tej Reddy

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Contents

1. Abstract 2. Introduction to MOSFET 2.1 Fundamentals of MOSFET 2.2 Threshold voltage 2.3 Operation modes of the MOSFET 3. Introduction to MINIMOS 3.1 understanding the script 3.2 How to generate the IV , BIN,OUT files 4. Analysis from the generated results 5. Results 6. Conclusion 7. References

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1. Abstract

The purpose of this document is to find out the parameters and study how its effects the MOSFET threshold voltage,transconductance using MINIMOS numerical simulation software tool ,calculate the threshold voltage for a given MOSFET with the following device parameter Tox =200 A, W= 1 micron , L= 1.2micron .Draw the Ids ,vds after getting the threshold values determine Rd at different L and plot Rds function of L and discuss about the results

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2. Introduction to MOSFET

MOSFET is an acronym for Metal Oxide Semiconductor Field Effect Transistor and it is the key component in high frequency, high efficiency switching applications across the electronics industry. It might be surprising, but FET technology was invented in 1930, some 20 years before the bipolar transistor. The first signal level FET transistors were built in the late 1950s while power MOSFETs have been available from the mid 70s. Today, millions of MOSFET transistors are integrated in modern electronic components, from microprocessors, through discrete power transistors. The focus of this topic is the gate drive requirements of the power MOSFET in various switch mode power conversion applications. 2.1 Fundamentals of MOSFET A MOSFET can be simply viewed as an electronic switch where the ON and OFF states are controlled by an electric field at the gate terminal. A basic MOSFET structure is shown in Figure 2.1 with an n-chnnel MOSFET (nMOSFET) for description. It is a four-terminal device with the terminals designated as gate, source, drain, and substrate or body. The Si substrate is p-type doped, and source and drain regions are heavily n- type doped. The gate electrode is usually made of metal or heavily doped polysilicon and is separated from the Si substrate by a thin insulating film, typically SiO2, i.e. the gate oxide. The gate oxide, SiO2, is usually formed by thermal oxidation of the Si substrate and acts as an energy barrier between the gate electrode and p-type Si substrate in order to confine charge carriers in the surface region of the Si substrate. When a sufficiently large positive voltage is applied on the gate terminal, the surface region of the Si substrate under the gate becomes inverted to n-type and hence called as n-channel. As a consequence, a current conducting path is formed through the n-channel between the two n+ source and drain regions. When there is no voltage applied on the gate electrode, no channel is formed and the MOSFET acts like two back-to-back p-n junction diodes with only low-level leakage currents present. A MOSFET therefore operates like a switch ideally suited for the drain. A p-channel MOSFET (pMOSFET) behaves similarly to an n-channel MOSFET but with an opposite polarity since the substrate, source and drain regions are all doped with opposite types as compared to the n-channel MOSFET in Figure below.

Fig N-channel MOSFET

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2.2 . Threshold voltage When a positive potential is applied to the gate, the energy band in the surface region of the substrate bends downwards as shown in Figure 2.2. The threshold voltage (VT) of the n-channel MOSFET is defined as the gate voltage at which the surface potential (S) or band bending reaches 2B and can be expressed as (for a uniformly doped substrate)

.1

where ms is the work function potential difference between the gate and Si substrate, Q is the equivalent fixed oxide charge per unit area at the oxide-silicon interface, and B is the potential difference between the intrinsic Fermi level, EFi, and the Fermi level in the substrate, EF. B is a function of substrate doping concentration, NA, given by,

.2 2.3 . Operation modes of the MOSFET The operation of a MOSFET can be separated into three different modes, depending on the voltages at the terminals. In the following discussion, a simplified algebraic model is used that is accurate only for old technology. Modern MOSFET characteristics require computer models that have rather more complex behavior. 1. Cutoff, subthreshold, or weak-inversion mode When VGS < Vth: 2. Triode mode or linear region (also known as the ohmic mode) When VGS > Vth and VDS < ( VGS Vth )

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3. Saturation or active mode When VGS > Vth and VDS > ( VGS Vth ) The switch is turned on, and a channel has been created, which allows current to flow between the drain and source. Since the drain voltage is higher than the gate voltage, the electrons spread out, and conduction is not through a narrow channel but through a broader, two- or three-dimensional current distribution extending away from the interface and deeper in the substrate. The onset of this region is also known as pinchoff to indicate the lack of channel region near the drain. The drain current is now weakly dependent upon drain voltage and controlled primarily by the gatesource voltage, and modeled approximately as: .3 The additional factor involving , the channel-length modulation parameter, models current dependence on drain voltage due to the Early effect, or channel length modulation. According to this equation, a key design parameter, the MOSFET transconductance is: , ..4 where the combination Vov = VGS Vth is called the overdrive voltage, and where VDSsat = VGS - Vth (which Sedra neglects) accounts for a small discontinuity in ID which would otherwise appear at the transition between the triode and saturation regions. Another key design parameter is the MOSFET output resistance rout given by: ..5

rout is the inverse of gDS where . VDS is the expression in saturation region. If is taken as zero, an infinite output resistance of the device results that leads to unrealistic circuit predictions, particularly in analog circuits. As the channel length becomes very short, these equations become quite inaccurate. New physical effects arise. For example, carrier transport in the active mode may become limited by velocity saturation. When velocity saturation dominates, the saturation drain current is more nearly linear than quadratic in VGS. At even shorter lengths, carriers transport with near zero scattering, known as quasi-ballistic transport. In addition, the output current is affected by drain-induced barrier lowering of the threshold voltage. The following graph shows how the MOSFET drain current vs. drain-to-source voltage for several values of VGS Vth; the boundary between linear (Ohmic) and saturation (active) modes is indicated by the upward curving parabola.

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Fig-Id Vs Vds curves at different Vgs values

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3. Introduction to MINIMOS
MINIMOS is a software tool for the numerical simulation of field-effect transistors such as silicon bulk and SOI MOSFETs. 3.1 Understanding the script DEVICE BIAS PROFILE CHANNEL=N GATE=NPOLY TOX=150.E-8 W=1.E-4 L=0.85E-4 UD=4. UG=1.5 NB=5.2E16 ELEM=AS DOSE=2.E15 TOX=500.E-8 AKEV=160. + IMPLANT OPTION OUTPUT END In the above file, the Bold-faced words are called as DIRECTIVES. Under each directive, there are different parameters, which are called as KEYS. Comment starts with a * (Asterisk) and that entire line will be treated as comment. The BIAS, DEVICE and PROFILE directive with appropriate keys are required in any MINIMOS input file. . The directives may appear in any order in the input file, except the END directive, which hat to be last statement in the input file. Explanation TEMP=1050. TIME=2700

ELEM=B DOSE=1.E12 AKEV=12 TEMP=940 TIME=1000 MODEL=2-D ALL=YES PIF=YES bin=yes

DEVICE: This directive is used specify the physical device parameters.

CHANNEL GATE

Channel type of the device Work function difference for the gate w.r.t. the intrinsic level in the substrate for MOSFET -

Tox W L

Thickness of the gate insulator Channel width Gate length

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BIAS: Specifies the simulation operating point UD UG Applied drain voltage

- Applied gate voltage

STEP: Specifies the step sequence of any applied terminal volatge DD DG ND - Drain voltage increment - Gate voltage increment - No.of drain voltage steps

PROFILE: Specifies the source-drain doping profiles, bulk doping and bulk trap distribution. NB - Bulk doping

ELEM - Implantation element DOSE AKEV TEMP TIME - Implantation dose - Implantation energy - Diffusion (Annealing) temperature - Diffusion time

TOX - Implantation isolation oxide thickness OPTION: Specifies general purpose keys to control the execution of MINIMOS. MODEL - Calculation mode OUTPUT: Specifies the physical quantities to be printed after the simulation. ALL - Prints all available quantities

END: Signals the end of the input file.

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3.2 How to generate the IV , BIN,OUT files Open the CMD prompt of your system and change the directory to c:\simulators\minimos\bin And after that type the command c:\simulators\minimos\bin\minimos filename.INP Then see the particular directory for the OUT ,BIN,IV files Screen shots as follows

Fig screen shot of minimos Then the values from the IV file are imported to Excel sheet and required graphs are were plotted

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4. Analysis from the generated results

4.1 At L=0.8 I-V character sticks linearly increases and after some extend at 0.9v the curve is constant slightly. Rd Drain resistance of MOSFET at vg = 1.6v at vd=0.6v the curve increases linearly and be constant at 0v at vg = 2.6v increases exponentially at vd=0.6v at vg = 7.6v increases exponentially at vd=0.6v with ripples on the exponential graph Gm- transconductance By varying the Vds at constant Vgs , the inverted bell shape like curve will be observed Vth Threshold voltage , by adding the step sizes DG and DD we plot the graph varying the Vgs keeping Vds constant. On comparing all three graphs we we can conclude that threshold voltage is 0.5-0.6 volts

4.2 At L=1.2 I-V character sticks linearly increases and after some extend at 0.8v the curve is constant slightly. Rd Drain resistance of MOSFET at vg = 1.6v at vd=0.6v the curve increases linearly and be constant at vg = 1.10v increase linearly at vd=0.6v Gm- transconductance By varying the Vds at constant Vgs , the inverted bell shape like curve will be observed Vth Threshold voltage , by adding the step sizes DG and DD we plot the graph varying the Vgs keeping Vds constant. On comparing all three graphs we we can conclude that threshold voltage is 0.6 volts

4.3 At L=2 I-V character sticks linearly increases and after some extend at 0.9v-1v the curve is constant slightly. Rd Drain resistance of MOSFET at vg = 0.1v at vd=0.1v the curve increases linearly and be constant at vg = 1.10v increases at vd=0.1v and after that it is unstable at vg= 4.10v the curve is constant at zero and at 4.10 v the curve decreases to negative side Gm- transconductance By varying the Vds at constant Vgs , the inverted bell shape like curve will be observed

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Vth Threshold voltage , by adding the step sizes DG and DD we plot the graph varying the Vgs keeping Vds constant. On comparing all three graphs we we can conclude that threshold voltage is 0.3 volts On comparing the graphs by varying the lengths of the gate , threshold voltages are observed

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5. Results At L=2.0u Graph for V-I

VI
7.00E-04 6.00E-04 5.00E-04 4.00E-04 3.00E-04 2.00E-04 VD at 2.60 VD at 3.10 VD at 6.0 VD at 7.60 VD at 8.60

1.00E-04
0.00E+00 0.00E+001.00E+002.00E+003.00E+004.00E+005.00E+006.00E+00

Graph for Gm
4.50E-05 4.00E-05 3.50E-05 3.00E-05 2.50E-05 2.00E-05 1.50E-05 1.00E-05 5.00E-06 0.00E+00 0.00E+00 2.00E+00 4.00E+00 6.00E+00 8.00E+00 1.00E+01 Gm at 0.1 GM at 4 GM at 6.0 GM at 8.0

Graph for Vth

THRES
4.00E-05 3.00E-05 2.00E-05 THRES 1.00E-05 0.00E+00 -1.00E-05 0.00E+00 1.00E-05 2.00E-05 3.00E-05 4.00E-05 -1.00E-05

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At L=1.2u Graph for v-i


2.00E-04 1.50E-04 1.00E-04 5.00E-05 0.00E+00 0.00E+00 1.00E+00 2.00E+00 3.00E+00 4.00E+00 5.00E+00 6.00E+00

VI at vg.6 VI at vg 1.10 VI at 1.60 VI at 2.10 VI at vg 2.60

Graph for Gm
4.50E-05 4.00E-05 3.50E-05 3.00E-05 2.50E-05 2.00E-05 1.50E-05 1.00E-05 5.00E-06 0.00E+00 0.00E+00 2.00E+00 4.00E+00 6.00E+00 8.00E+00 1.00E+01 Gm at vd1 Gm at vd2 GM at vd3 GM at vd4

Graph for Vth

thres at L=1.2
8.00E-05 7.00E-05 6.00E-05 5.00E-05 4.00E-05 3.00E-05 2.00E-05 1.00E-05 0.00E+00 -1.00E-05 0.00E+00 2.00E+00 4.00E+00 6.00E+00 8.00E+00 1.00E+01 1.20E+01

thres at L=1.2

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At L=0.8u Graph for v-i


1.20E-03 1.00E-03 8.00E-04 6.00E-04 4.00E-04 2.00E-04 0.00E+00 0.00E+00 1.00E+00 2.00E+00 3.00E+00 4.00E+00 5.00E+00 6.00E+00 VD at 3.6 VD at 2.10 V at 5.60 VD at 6.10 VD at 8.10

Graph for Gm
1.00E-04 9.00E-05 8.00E-05 7.00E-05 6.00E-05 5.00E-05 4.00E-05 3.00E-05 2.00E-05 1.00E-05 0.00E+00 0.00E+00 2.00E+00 4.00E+00 6.00E+00 8.00E+00 1.00E+01 1.20E+01

GM at 0.1 GM at 4 GM at 7

Graph for Vth

1.20E-04 1.00E-04 8.00E-05 6.00E-05 4.00E-05 2.00E-05 0.00E+00

THRES

THRES

0.00E+00 2.00E+00 4.00E+00 6.00E+00 8.00E+00 1.00E+01 1.20E+01

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6. Conclusion The mathematical calculations are done using minimos simulator and graphs are plotted at different values of the length of the gate . We observe how the threshold of the MOSFET device effected by the device parameters . There is a slight difference in the Vth

7. References 1. http://www.imtek.de/mikroelektronik/content/staff/device_sim.pdf 2. Minimos tutorial 3. Google sources

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