IS J AA

International Journal of Systems , Algorithms & Applications

Development of Design Environment for Embedded SoC Application

Archana V. Mahatme, 2R.S. Pande Department of Electronics Engineering ,Shri. Ramdeobaba Kamla Nehru Engineering College, Nagpur, India 2 Professor, Department of Electronics Engineering, Shri. Ramdeobaba Kamla Nehru Engineering College, Nagpur, India e-mail: mahatme.archana@gmail.com1, panders@rknec.edu2
1

Abstract - This paper deals with the basic design environment and its development for embedded SoC. In this environment, development of embedded systems may become easier. It is based on the Leon processor which is open source, soft core processor provided by Gaisler Research. The design environment is used for development of Leon processor based applications. The environment helps to debug the application and thoroughly verify its operation. Simulation result which verifies the operation of typical application in design environment is being presented. Keywords - Embedded System, SoC, Design Environment.

I. INTRODUCTION An embedded system is combination of processor along with some software and is specifically designed for a particular function. Over the last few years, embedded systems have experienced a tremendous growth in every domain like digital signal processing, communication, consumer electronics, medical equipment and many others. Day by day the complexity of applications goes on increasing with requirements like high performance, miniaturization and long battery life. Embedded systems are therefore configured as System on a Single Chip (SoC). SoC refers to integrating all components of a system may be analog, digital or mixed signal into single integrated circuit .If the embedded systems are to reach their full application domain, their total cost, both development and system must be reduced as much as possible[1]. The basic requirements for development of design environment for embedded system are development software like simulator, compiler, emulator and IP core. SoC designs are usually a mix of externally sourced Intellectual Property(IP) blocks, in-house developed standard functions and application specific blocks [2]. The IP core allows the reuse of predesigned hardware components. IP cores are soft core, firm core or hard core. Soft core processors are always preferable because of its higher level of abstraction, more flexibility and platform independency. Different commercial packages are being available for System on Chip design like Xilinx EDK or Altera Nios II IDE, which ease the workload of the embedded system designer by providing proprietary soft cores and the tools needed for implementing them in the manufacturer's FPGAs. These commercial solutions have

certain limitations. The most important is that the implemented softcores are dependent on the manufacturer's specific hardware. These softcores are also closed source, so modifications or enhancements to these softcores are impossible from a practical perspective. A designer that handles low budget projects, the cost of these software packages can be unaffordable[1]. Therefore, it is prefer to use open source cores which are freely available from open source communities, for example open source core Leon by Gaisler Research and Open RISC 1200 from open cores. In the propose work the Leon2 as an embedded processor is being preferred, which is a synthesizable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture [3]. The complete sources of this processor are distributed under the GNU LGPL license together with the needed tools to correctly configure the model. Thus, the advantages of using Leon as an embedded processor are it is open source, independent of any specific FPGA technology, allows reuse of code and highly configurable. The model has full implementation of AMBA AHB and APB on-chip buses. The Advanced Microcontroller Bus Architecture (AMBA) specification defines an onchip communications standard for designing high-performance embedded microcontrollers [4]. AMBA make it easy to extend functionality of processor by addition of custom peripherals to the system. The propose work make an attempt to develop an environment in which the design of an embedded application will become possible. The use of an open source IP core and free development software of the propose work will demonstrate substitute solution for the development of embedded systems. Block diagram of proposed work based on the Leon2 processor is shown figure 1.

Figure . Block diagram of proposed work based on Leon 2 processor

Volume 2, Issue ICTM 2011, February 2012, ISSN Online: 2277-2677 ICTM 2011|June 8-9,2011|Hyderabad|India

34

DEVELOPMENT OF DESIGN ENVIRONMENT FOR EMBEDDED SOC APPLICATION

IS J AA

International Journal of Systems , Algorithms & Applications

II. PLATFORM The platform over which the environment is being developed is CentOS-5.4, the linux platform. This linux platform makes it possible to develop and demonstrate an application using the following software. Simulator provided by Mentor GraphicsModelsim. LECCS a free C/C++ cross-compiler system based on gcc provided by Gaisler Research. TSIM-a generic SPARC architecture simulator capable of emulating ERC32- and Leon-based computer systems. GRMON - a general debug monitor for the Leon processor and for SOC designs based on the GRLIB IP. GDB debugger which allows the source level debugging of program. III. LEON2 PROCESSOR The Leon VHDL model [5] implements a fully synthesizable 32-bit processor with an instruction set according to the IEEE-1754 (SPARC V8) standard. The Leon is designed for embedded applications. Implementation is focused on portability and low complexity. Block diagram of Leon2 processor is as shown in figure2. This processor has following remarkable features : 5-stage instruction pipeline multiply/divide/mac operations on hardware separate instruction and data caches memory management unit, MMU flexible memory controller, able to work with SDRAM in 32-bit mode and with SRAM and ROM in configurable modes of 8, 16 or 32 bits on-chip RAM interface for a floating point unit and coprocessor debug support unit(DSU) two 24-bit timers, watchdog and power-down two serial port controllers(UART) 16-bit I/O port mapped on memory ethernet controller 10/100 MAC, PCI interface AMBA 2.0 Bus interrupt controller

parallel with the main processor in order to increase performance.

Figure . Block Diagram of Leon2 Processor

Leon2 uses the AMBA-2.0 AHB bus to connect the main processor with high-speed controller like cache, memory and other optional units like the onchip RAM or PCI or Ethernet interfaces. Another AMBA-2.0 APB bus is used to access most onchip peripherals. It is optimized for simple operation and low-power consumption. It is connected to the AHB and Leon2 via the AHB/APB Bridge, which is master of that bus. Leon2 external memory access is provided by a programmable memory controller with interfaces to PROM, SRAM, SDRAM and memory mapped I/O peripherals. The controller can decode a map of up to 2 Gbytes. The processor is extensively configurable and can be efficiently implemented on both FPGAs and ASIC technologies. The only technology-specific mega-cells needed are ram cells for caches and register file. IV. DESIGN ENVIRONMENT In order to design and develop a System-on-Chip application based on the Leon2 processor, an environment will be required in which it become possible to configure the processor according to the requirement. It will also compile, debug the application and simulate it to verify the operation. Finally it will run on an emulator for demonstration. A representation of this environment is shown in the figure 3. The design flow consists of configuration and simulation of Leon2 model as the first step. Next is the compilation and debugging. Finally there is a Leon2 simulator that is use to accelerate the design flow and to check the software on virtual system made by the simulator. This is typical software development flow with special features of Leon2 tools available for SoC implementation.

SPARC V8 processor defines three main units integer unit, floating-point unit and a custom coprocessor. Each unit has its own 32-bit internal registers. The later two units are optional. Leon2 implements the integer unit completely and the interfaces for the other two units in its core. High performance FPU for Leon2 is commercially available with Gaisler Research which is fully IEEE-754 compliant. Leon2 can also provide a generic interface for a custom user defined co-processor which will work in

Volume 2, Issue ICTM 2011, February 2012, ISSN Online: 2277-2677 ICTM 2011|June 8-9,2011|Hyderabad|India

35

DEVELOPMENT OF DESIGN ENVIRONMENT FOR EMBEDDED SOC APPLICATION

IS J AA

International Journal of Systems , Algorithms & Applications

Figure . SoC Design Environment for Leon2 Processor

B. Simulation Once the model in being configured, it is simulated by running a generic test bench provided with the Leon Model. The model comes with a generic test bench and test program, and includes support files for the Synopsys VSS and Modelsim simulators. It also features a built-in disassemble for debug purposes. This test bench allows creation of a model of Leon system with various memory sizes/types by setting appropriate generics. The supplied test programs in tsource directory are run by the test benches tests all on-chip peripherals and interfaces. The file tbench/tbleon.vhd contains a number of alternative configurations using generic testbench. Various configurations like tb_func8, tb_func16, tb_func32 will allow functional test of all on chip peripherals using 8, 16 or 32-bit external static ram. The precompiled images ram.dat and rom.dat are abounding, so that test suite can run without installing compiler [1]. Screen shot of the Leon simulated in modelsim using tb_func32 is shown in figure 5 and 6.

A. Configuration The Leon model is highly configurable [5], allowing the model to be used for a certain application or target technology. The first step in design process is the configuration of Leon2 processor according to the need of designer. It includes the selection of on chip peripherals, inclusion of any additional user-defined peripherals and assignment of values to the main parameters defining the behavior of processor [6]. A graphical configuration tool based on the linux kernal tkconfig scripts is used to configure the model as shown in figure 4. This tool works on both Windows (with Cygwin) and Unix/linux platform. For tkconfig to work, working installation of gcc and tcl/tk must be installed on the host.

Figure . Simulation of Leon2 using generic testbench

Figure . Configuration tool for Leon2 processor

Figure . Simulation waveform for Leon2 using generic test bench

Volume 2, Issue ICTM 2011, February 2012, ISSN Online: 2277-2677 ICTM 2011|June 8-9,2011|Hyderabad|India

36

DEVELOPMENT OF DESIGN ENVIRONMENT FOR EMBEDDED SOC APPLICATION

IS J AA

International Journal of Systems , Algorithms & Applications

C. Compilation As Leon2 is SPARC V8 compliant, compilers for SPARC V8 can be used with Leon. To simplify initial software development, Gaisler Research provides BCC cross-compiler for Leon2 and LEON3 processors. It is based on the GNU compiler tools and the Newlib standalone C-library. The cross-compiler system allows compilation of sequential (non-tasking) C and C++ applications. It supports both hard and soft floating-point operations as well as both V7 and V8 multiply and divide instructions [7]. Compilation and debugging of applications is being take place in the following steps 1) Compile and link program with gcc. 2) Debug program on a simulator or remote target. 3) Create boot-prom for a standalone application. The default link address is start of RAM, i.e. 0x40000000 for Leon. Other link addresses can be specified through the -Ttext option. D. Debugging GNU Project debugger GDB, allows to see what is going on inside another program while it executes. GDB offer wide facilities for tracing and altering the execution of computer programs. The user can monitor and modify the values of programs internal variables and even call functions independently of the application programs normal behavior. Every executable binary cannot be simply loaded into GDB for debugging because it does not contain debugging symbols. This symbol more or less tells GDB where to look in the source when it is running a program [8]. While compiling a program g switch is used to generate debugging information. GDB offers a remote mode frequently used when debugging embedded systems. Remote operation means when GDB runs on one machine and the program being debugged runs on another. Using the GDB debugger, it is possible to perform source-level symbolic debugging either on a simulator or using real target hardware. E. Tsim TSIM is a generic SPARC architecture simulator capable of emulating ERC-32 and Leon-based computer systems [9]. It is a high performance Leon simulator which seamlessly can be attached to GDB and emulate a Leon system. TSIM can operate in two modes, standalone and attached to GDB. In standalone mode, ERC32 or Leon applications can be loaded and simulated using a command line interface. A number of commands are available to examine data, insert breakpoints and for advance simulation. When attached to GDB, TSIM acts as a remote GDB target. Applications are loaded and debugged through GDB.

V. APPLICATION EXAMPLE Here an application illustrating the design flow of an arithmetic operation is presented. The program has been generating multiplication table of a number. The first step in development of an application is the configuration of Leon processor. Configuration GUI of Leon will be open by make xconfig. In VHDL debugging Accelerated UART tracing enabled as shown in figure 7. Changes are saved to device.vhd file using make dep command.

Figure . Configuration of Leon for an embedded application

The BCC compiler is used to create a memory dump readable from generic ram model. It is written into ram.dat. The ROM code is constant for all programs. Both files are read by the VHDL simulator prior to simulation start and loaded into the external memory in the test bench. This allows to write and compile C/C++ code and execute it through a VHDL simulation. The result of simulation is as shown in figure 8.

Figure . An Application Example

Volume 2, Issue ICTM 2011, February 2012, ISSN Online: 2277-2677 ICTM 2011|June 8-9,2011|Hyderabad|India 37

DEVELOPMENT OF DESIGN ENVIRONMENT FOR EMBEDDED SOC APPLICATION

IS J AA

International Journal of Systems , Algorithms & Applications

The application can also run on Tsim in standalone mode. The result is as shown below in figure 9.

Figure 1. GDB in remote mode Figure . Execution of application program on Tsim

Debugging is unavoidable step in development of any application. The GDB will allow debugging and execution of program. Following figure 10 shows the execution of program on GDB.

VI. CONCLUSION This paper described the basic requirements for the development of an embedded system. It justifies the use of open source, soft IP core of Leon2 processor by Gaisler Research. The design environment based on Leon2 is flexible due to large number of pre-defined and highly configurable devices included in Leon2 and due to availability of most of the free software supported by Gaisler Research. Thus in this work, the design environment based on Leon2 processor is being developed and an application is demonstrated. REFERENCES
[1]

[2]

[3] [4] [5]

Figure 1. Application program on gdb

[6]

Tsim can be attached to GDB and acts as a remote GDB target. Here GDB will run on one machine and the program being debugged runs on another. Following figure11 shows remote operation of GDB where application is running on Tsim.

[7] [8] [9]

H. Guzman Miranda, J. Tombs, M. A. Aguirre Echanove. Implementation of a low cost embedded system using the Leon2 processor. DCIS 2006. Z. stamenkovic, C.Wolfand J.Gaisler, LEON-2 : Genaral Purpose Processor for Wireless Engine, IHP Gmb, H.Frankfurt, Germany. SPARC International, Inc. The SPARC Architecture Manual: Version-8, Revision SAV080SI9308. ARM Limited, AMBA Specification, Rev 2.0. ARM IHI 0011A, May 1999. Gaisler Resarch, Leon2 Processor User's Manual, Version 1.0.30, XST Edition, July 2005. E.Ostua, J.Juan Chico, et,all. A SoC Design Methodology for Leon2 on FPGA, Instituto de Microelectronica de Sevilla Centro Nacional de Microelectronica, Edificio CICA - Av. Reina Mercedes, s/n 41012 Sevilla (Espana). Gaisler Reasarch, BCC - Bare - C Cross - Compiler Users Manual, Version 1.0.34, June 2010. Menaka Lashitha Bandara, A guide to GDB, Monash University (Clayton),Victoria, Australia. Gaisler Research, TSIM2 Simulator Users Manual, ERC32/ LEON2/LEON3, October 2010, Version 2.0.18.

Volume 2, Issue ICTM 2011, February 2012, ISSN Online: 2277-2677 ICTM 2011|June 8-9,2011|Hyderabad|India

38