Electronic System Level (ESL) Design

2008. 9

(joonhwan.yi@kw.ac.kr) joonhwan.yi@kw.ac.kr)

Copyrighted by Joonhwan Yi (joonhwan.yi@kw.ac.kr)


v Background v Electronic system level (ESL) design v ESL design tasks v v

Copyrighted by Joonhwan Yi (joonhwan.yi@kw.ac.kr)

Background

Computer Based System

v System-on-chips (SoCs) are computer based systems System-on(SoCs)
Processors and software control the system Hardware accelerators perform dedicated tasks On-chip communication and interface IP handles data traffic

v Many hardware and software components are co-working in a cocomplex manner

System behavior cannot be predicted and optimized easily
Processors / Accelerators
CPUs DSPs Interrupt controller, DMA controller, etc. HW accelerators
Memory

On-chip communication
- Bus fabric - Arbiter, bus matrix - Bus bridges

Software

Memory controller

Software

CPU CPU

DSP DSP GPS MPEG Bus bridge

SoC
Interfaces
- USIM, SDIO, USB, PCMCIA, UART, etc. - CDMA/Wibro modem
USIM SDIO USB

Software
- OS, device driver - Middleware - Application software

PCMCIA

Modem

Increasing Design Complexity

v Data transfer rate for communication standards
2G (GSM/GPRS/EDGE/CDMA2000 1x) 3G (WCDMA/CDMA2000 1x EV-DO Beyond 3G (HSPA/WiBro/LTE) 4G 100 Kbps ~ 3 Mbps 10 ~ 200 Mbps 100 Mbps ~ 1 Gbps 10,000 x

v Mobile convergence
Voice + broadcasting + entertainment + camera + security + etc.

v More functionality, more data movement, more computation

The performance of each IP as well as SoC architecture matters Architecture design based on scientific analysis is necessary

Problems in SoC Architecture Design

v Slow simulation speed !!!
More than 10M gates for modern mobile modem SoCs or multimedia processors At register transfer level (RTL), for SoC size, the simulation speed is about 3~30 cycles per second For example, consider a CDMA modem SoC.
Takes about 4 hours to simulate 20 ms of real time scenario For architecture design, at least few seconds of real time scenario should be simulated many times To simulate a real time scenario of 3 seconds, it takes more than 60 years

At FPGA, its fast but has many limitations

Limited design space, long time for design changes, bad visibility for internal signals, etc.

v Late availability of executable designs

Higher level of abstraction addresses these problems nicely!
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Design Abstractions

Higher level of abstraction

Time 2000s 1990s 1980s 1970s

Level of abstractions Electronic system level RTL Gate level Transistor level

Design size 10M+ 100K ~ 1M 1K ~ 10K ~ 100

Languages C/C++/SystemC Verilog, VHDL Schematic SPICE netlist, layout

Copyrighted by Joonhwan Yi (joonhwan.yi@kw.ac.kr)

Electronic System Level (ESL) Design

Electronic System Level (ESL)

v An abstraction level of electronic circuit designs
Higher than register transfer level (RTL) Lower than algorithm level
Design abstraction Function accuracy Cycle accuracy RTL
Register (flip-flop) level

ESL
Block level Bus-functional level Both (with or without cycle accuracy) are possible Signal Transaction Function calls C/C++/SystemC

Algorithm level
Behavior level

Naturally cycle accurate

No timing

Communication method Description languages

Signal (bit-level)

Function calls

HDL (Verilog, VHDL)

C/C++/SystemC

abstraction layer
1: bus-functional transaction level model w/ cycle-accuracy () 2: bus-functional transaction level model w/o cycle-accuracy (SW )
Copyrighted by Joonhwan Yi (joonhwan.yi@kw.ac.kr) 9

Popular Levels in ESL

v Programmers view (PV) register accurate but no timing v Architectural view (AV) register accurate & cycle approximate v Verification view (VV) register and cycle accurate

Processors / Accelerators
CPUs DSPs Interrupt controller, DMA controller, etc. HW accelerators

Memory

On-chip communication
- Bus fabric - Arbiter, bus matrix - Bus bridges

Software

Memory controller

Software

CPU CPU

DSP DSP GPS MPEG Bus bridge

SoC
Interfaces & host models
- USIM, SDIO, USB, PCMCIA, UART, etc. - Corresponding host models - CDMA/Wibro modem & basestation models
USIM SDIO USB

Software
- OS, device driver - Middleware - Application software

PCMCIA

Modem

Host

Host

Host

Host

Basestation

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10

ESL Design
v Efficient hardware-software co-design in early design stage
/ hardware-software co-simulation

Availability Simulation Simulation Hardware-software co-design

ESL design (Virtual platform)

Early ( ) (RTL 3000 )

RTL
Late ( ~ )

FGPA
Very late ( ~ )

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11

ESL Design
Requirements HW IPs SW IPs

IP
(algorithm / SW)

IPs

+
ESL 1

HW-SW partitioning

Late HW-SW co-verification

Yes

Architecture exploration

ESL 2

Architecture

Initial architecture

Architecture design

Architecture design

ESL 3
Implementation

HW-SW coverification

Implementation

Early HW-SW co-verification

Verification

Verification

HW on silicon + SW (integration + verification)

Problem?

Time to silicon advantage

No
Success

Time to market advantage

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ESL Design Tasks

ESL Design Tasks

v Architecture exploration v Hardware-software co-design Hardwarecov Hardware-software partitioning Hardwarev Hardware-software co-verification Hardwarecov Performance analysis v RTL generation v Power analysis

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Architecture Exploration
Performance

Legend Initial architecture

Exploration space at different abstraction levels

Infeasible region
(with same design effort) gate-level RTL ESL Specification

Poor quality region

Optimum architecture curve

Intersection of the curve within a circle represents the set of optimum architecture solutions searchable at the abstraction level

Cost
15

Copyrighted by Joonhwan Yi (joonhwan.yi@kw.ac.kr)

HardwareHardware-Software Co-Design Cov

Sequential development: hardware software

v ESL design design

Parallel development: hardware software

Old flow

Architecture

Hardware

Software

New flow Architecture ESL design Hardware ESL design Software

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HardwareHardware-Software Partitioning
v Definition
A process that makes decisions whether a required functionality of a system is more advantageously implemented in hardware or in software Fundamental phase of hardware-software co-design

v ESL design technique plays an crucial role

Fast iterative performance analysis is essential
Start with all HW (or SW) implementation

ESL design

Is the performance requirement met?

No

Change HW-SW partitions Reschedule jobs

Yes

ESL design

Is it optimum? Yes

No

Optimum system architecture

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HardwareHardware-Software Co-Verification Cov sequential development

Hardware-software co-verification Big surprise (/ ) long iteration

v ESL design parallel development design

Hardware-software co-verification co-verification big surprise iteration Old flow Architecture Hardware Long iterations New flow Architecture ESL design
Short iterations
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Software

Hardware ESL design Software

Performance Analysis
ESL design tool data
Function call trace Cache hit rate Function execution time Variable value

Information (Data )
Function call overhead Cache size optimization Software execution time Software bug

SW

HW

Bus and signal waveform Bus utilization Register value waveform

HW-SW co-verification Bus & system architecture Hardware initialization

System

HW & SW data

System performance HW-SW partitioning system

Copyrighted by Joonhwan Yi (joonhwan.yi@kw.ac.kr)

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RTL Generation
v Behavioral synthesis
Automatic ESL to RTL mapping

Architecture design

ESL design
Architecture exploration

Initial architecture document

ESL design
Behavioral synthesis (RTL generation)

Initial software

Hardware design Start from scratch

Software design Start from scratch

Hardware design

Software design

Broken links Copyrighted by Joonhwan Yi (joonhwan.yi@kw.ac.kr) (manual conversion)

Short time for RTL generation Short time for HW-SW co-verification
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Power Analysis
v Why ESL power analysis?
Realistic scenario for power analysis Short analysis time for power analysis Base for system (HW & SW) power optimization

v : Samsung-Sequence ESL power analysis flow Samsung Scenario @ESL & analysis @RTL
Realistic scenario

ESL RTL Analysis speed

PowerTheater-ESL ORINOCO Mapae () PowerTheater PrimePower PowerTheater PrimePower PowerMill HSPICE

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Unrealistic scenario

Gate-level Transistor-level

Analysis

Copyrighted by Joonhwan Yi (joonhwan.yi@kw.ac.kr)


v ESL design very fast hardware simulation model design
FPGA chip RTL 3000 RTL available

v Hardware-software co-design Hardwareco ESL design hardware software (early system verification) (optimum system design)

v Early stage system (HW+SW) performance analysis analysis

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