Ic Spec Lds285

LDS285
Data Sheet
720 Source (240 x RGB) + 320 Gate 16M-Color One-Chip TFT Driver
Feb. 27, 2007
PRELIMINARY
LDS285
240 (RGB) x 320 16M-Color TFT Driver
Version 2.00
CONTENTS
1 2 3 4 5 DESCRIPTION FEATURES BLOCK DIAGRAM PIN DESCRIPTION FUNCTIONAL DESCRIPTION
5.1
5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 5.1.8
2 2 4 5 10
MPU INTERFACE ......................................................................................................................................10

Interface Type Selection .................................................................................................................................. 10 General Protocol .............................................................................................................................................. 11 8080-Series Parallel Interface (P68 = "L")....................................................................................................... 12 6800-Series Parallel Interface (P68 = "H") ...................................................................................................... 15 Serial Interface................................................................................................................................................. 18 Interface Pause................................................................................................................................................ 22 Data Transfer Recovery................................................................................................................................... 23 Display Module Data Transfer Modes ............................................................................................................. 25 Display Data Formats ...................................................................................................................................... 27 RGB Interface .................................................................................................................................................. 41 Address Counter .............................................................................................................................................. 49 Memory Map .................................................................................................................................................... 51 Normal Display On or Partial Mode On ........................................................................................................... 52 Tearing Effect Output Line............................................................................................................................... 53
5.2
DISPLAY DATA RAM (DDRAM)................................................................................................................26

5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6
5.3 5.4 5.5 5.6 5.7 5.8
INSTRUCTION DECODER & REGISTER ................................................................................................57 SYSTEM CLOCK GENERATOR ...............................................................................................................57 OSCILLATOR.............................................................................................................................................57 SOURCE DRIVER .....................................................................................................................................57 GATE DRIVER ...........................................................................................................................................58 RGB INTERFACE TIMING DIAGRAM ......................................................................................................59
5.8.1 5.8.2 Relationship between Input Signal and Output Signal (RGB I/F Mode 3) ...................................................... 59 Input / Output Timing Chart (G0->G320, S1->S720)....................................................................................... 60 LCD Power Generation Scheme ..................................................................................................................... 61 Various Boosting Steps ................................................................................................................................... 62 Gray Voltage Generator................................................................................................................................... 63 Temperature Compensation ............................................................................................................................ 70
5.9
LCD POWER GENERATION CIRCUIT.....................................................................................................61

5.9.1 5.9.2 5.9.3 5.9.4
5.10 POWER ON/OFF SEQUENCE..................................................................................................................71
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5.10.1 Case 1 RESB line is held High or Unstable by Host at Power On............................................................... 71 5.10.2 Case 2 RESB line is held Low by host at Power On.................................................................................... 72
5.11 UNCONTROLLED POWER OFF ..............................................................................................................72 5.12 POWER FLOW CHART FOR DIFFERENT POWER MODES .................................................................73 5.13 INPUT / OUTPUT PIN STATE ...................................................................................................................74
5.13.1 Output or Bi-directional (I/O) Pins.................................................................................................................... 74 5.13.2 Input Pins ......................................................................................................................................................... 74
5.14 SLEEP OUT COMMAND AND SELF-DIAGNOSTIC FUNCTIONS OF THE DISPLAY MODULE ........75
5.14.1 Register loading Detection............................................................................................................................... 75 5.14.2 Functionality Detection .................................................................................................................................... 76 5.14.3 Chip Attachment Detection (optional).............................................................................................................. 77 5.14.4 Display Glass Break Detection (optional)........................................................................................................ 78
ADAPTIVE BCAKLIGHT CONTROL AND LED DRIVER CONTROL

6.1
6.1.1 6.1.2
79
LABC ( LIGHT ADAPTIVE BACKLIGHT CONTROL) ...............................................................................79

System Block Diagam with ALS (Ambient Light Sensor) and LDS285........................................................... 79 LABC Function Flow ........................................................................................................................................ 80 CABC Function Flow........................................................................................................................................ 83
6.2 6.3 6.4
CABC ( CONTENT ADAPTIVE BACKLIGHT CONTROL)........................................................................82

6.2.1
CABC AND LABC .....................................................................................................................................83 LED DRIVER CONTROL ...........................................................................................................................84

6.4.1 6.4.2 LED Driver control with PWM pulse ................................................................................................................ 84 LED Driver control with 1-wire digital interface( only for LDS8861 ) ............................................................... 86
INSTRUCTION DESCRIPTION
7.1
7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.1.6 7.1.7 7.1.8 7.1.9
88
INSTRUCTION CODE ...............................................................................................................................88

Instruction Code Table..................................................................................................................................... 88 NO (00h) .......................................................................................................................................................... 92 SWRESET: Software Reset (01h)................................................................................................................... 93 RDDID: Read Display ID (04h) ........................................................................................................................ 94 RDDST: Read Display Status (09h) ................................................................................................................ 95 RDDPM: Read Display Power Mode (0Ah)..................................................................................................... 97 RDDMADCTR: Read Display MADCTR (0Bh)................................................................................................ 98 RDDCOLMOD: Read Display Pixel Format (0Ch) .......................................................................................... 99 RDDIM: Read Display Image Mode (0Dh) .................................................................................................... 100
7.1.10 RDDSM: Read Display Signal Mode (0Eh) ................................................................................................... 101 7.1.11 RDDSDR: Read Display Self-Diagnostic Result (0Fh) ................................................................................. 102 7.1.12 SLPIN: Sleep In (10h) .................................................................................................................................... 103 7.1.13 SLPOUT: Sleep Out (11h) ............................................................................................................................. 105 7.1.14 PTLON: Partial Display Mode On (12h) ........................................................................................................ 107 7.1.15 NORON: Normal Display Mode On (13h)...................................................................................................... 108 LEADIS Technology CONFIDENTIAL
LDS285
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7.1.16 INVOFF: Display Inversion Off (20h)............................................................................................................. 109 7.1.17 INVON: Display Inversion On (21h)............................................................................................................... 110 7.1.18 GAMSET: Gamma Set (26h) ......................................................................................................................... 111 7.1.19 DISPOFF: Display Off (28h) .......................................................................................................................... 112 7.1.20 DISPON: Display On (29h) ............................................................................................................................ 113 7.1.21 CASET: Column Address Set (2Ah).............................................................................................................. 114 7.1.22 RASET: Row Address Set (2Bh) ................................................................................................................... 116 7.1.23 RAMWR: Memory Write (2Ch) ...................................................................................................................... 118 7.1.24 RAMRD: Memory Read (2Eh) ....................................................................................................................... 119 7.1.25 PTLAR: Partial Area (30h) ............................................................................................................................. 120 7.1.26 TEOFF: Tearing Effect Line OFF (34h) ......................................................................................................... 122 7.1.27 TEON: Tearing Effect Line ON (35h)............................................................................................................. 123 7.1.28 MADCTR: Memory Data Access Control (36h)............................................................................................. 124 7.1.29 IDMOFF: Idle Mode Off (38h) ........................................................................................................................ 126 7.1.30 IDMON: Idle Mode On (39h).......................................................................................................................... 127 7.1.31 COLMOD: Interface Pixel Format (3Ah)........................................................................................................ 129 7.1.32 WRDISBV : Write Display Brightness (51h) .................................................................................................. 130 7.1.33 RDDISBV : Read Display Brightness (52h)................................................................................................... 131 7.1.34 WRCTRLD: Write CTRL Display (53h).......................................................................................................... 132 7.1.35 RDCTRLD : Read CTRL Value Display (54h)............................................................................................... 133 7.1.36 WRCABC: Write Content Adaptive Brightness (55h) .................................................................................... 134 7.1.37 RDCABC : Read Content Adaptive Brightness (56h) ................................................................................... 135 7.1.38 RDID1: Read ID1 Value (DAh) ...................................................................................................................... 136 7.1.39 RDID2: Read ID2 Value (DBh) ...................................................................................................................... 137 7.1.40 RDID3: Read ID3 Value (DCh) ...................................................................................................................... 138 7.1.41 IFMODE: Set Display Interface Mode (B0h) ................................................................................................. 139 7.1.42 DISCLK: Display Clock Set (B1h).................................................................................................................. 141 7.1.43 INVCTR: Inversion Control (B2h) .................................................................................................................. 143 7.1.44 REGCTR: Regulator Control (C0h) ............................................................................................................... 145 7.1.45 VCOMCTR: VCOML / VCOMH Voltage Control (C1h) ................................................................................. 146 7.1.46 GAMCTR1: Set Gamma Correction Characteristics (C8h) ........................................................................... 147 7.1.47 GAMCTR2: Set Gamma Correction Characteristics (C9h) ........................................................................... 148 7.1.48 GAMCTR3: Set Gamma Correction Characteristics (CAh)........................................................................... 149 7.1.49 GAMCTR4: Set Gamma Correction Characteristics (CBh)........................................................................... 150 7.1.50 EPPGMDB: Write ID2, VCOM Offset Value.................................................................................................. 151 7.1.51 EPERASE: EPROM Erase (D1h) .................................................................................................................. 154 7.1.52 EPPROG: EPROM Program (D2h) ............................................................................................................... 155 7.1.53 EPRDVRF: EPROM Read Verify (D3h) ........................................................................................................ 156 7.1.54 RDVCOF: VCOM offset registers bits Read Back (D9h) .............................................................................. 157 7.1.55 LEDCTRL: Write the configuration for LED driver......................................................................................... 158
7.2
RESET TABLE (DEFAULT VALUE) (TBD) .............................................................................................160
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7.3
INSTRUCTION SETUP FLOW ................................................................................................................161

7.3.1 7.3.2 7.3.3 7.3.4 Initializing with the Built-in Power Supply Circuits (TBD) .............................................................................. 161 Power OFF Sequence (TBD)......................................................................................................................... 162 EEPROM Access Sequence for Initialization (Data Clear) ........................................................................... 163 EEPROM Access Sequence for program (Data write) (TBD)....................................................................... 164
SPECIFICATIONS
8.1 8.2 8.3 8.4 8.5 8.6
165
ABSOLUTE MAXIMUM RATINGS ..........................................................................................................165 ESD PROTECTION LEVEL .....................................................................................................................165 LATCH-UP PROTECTION LEVEL ..........................................................................................................165 LIGHT SENSITIVITY................................................................................................................................165 MAXIMUM SERIES RESISTANCE .........................................................................................................166 DC CHARACTERISTICS .........................................................................................................................167
8.6.1 8.6.2 Basic Characteristics ..................................................................................................................................... 167 Current Consumption..................................................................................................................................... 169 Parallel Interface Characteristics (8080-series MPU) ................................................................................... 170 Parallel Interface Characteristics (6800-series MPU) ................................................................................... 172 Serial Interface Characteristics (3-Pin Serial) ............................................................................................... 174 Serial Interface Characteristics (4-Pin Serial) ............................................................................................... 175 RGB Interface Characteristics ....................................................................................................................... 177 Reset Input Timing......................................................................................................................................... 178 Measurement Conditions............................................................................................................................... 179
8.7
AC CHARACTERISTICS(TBD)................................................................................................................170
8.7.1 8.7.2 8.7.3 8.7.4 8.7.5 8.7.6 8.7.7
REFERENCE APPLICATIONS
9.1
9.1.1 9.1.2 9.1.3 9.1.4 9.1.5 9.1.6 9.1.7 9.1.8 9.1.9
183
MICROPROCESSOR INTERFACE.........................................................................................................183
Interfacing with 3-Pin Serial Mode (P68 = "L", BS2=L, BS1 = "L", BS0 = "L") ........................................... 183 Interfacing with 4-Pin Serial Mode (P68 = "H", BS2=L, BS1 = "L", BS0 = "L")........................................... 183 Interfacing with 8080-series MPU 8-Bit Bus (P68 = "L", BS2=L, BS1 = "L", BS0 = "H")............................ 184 Interfacing with 6800-series MPU 8-Bit Bus (P68 = "H", BS2=L, BS1 = "L", BS0 = "H") ........................... 184 Interfacing with 8080-series MPU 9-Bit Bus (P68 = "L", BS2=H, BS1 = "L", BS0 = "L")............................ 185 Interfacing with 6800-series MPU 9-Bit Bus (P68 = "H", BS2=H, BS1 = "L", BS0 = "L") ........................... 185 Interfacing with 8080-series MPU 16-Bit Bus (P68 = "L", BS2=L, BS1 = "H", BS0 = "H") ......................... 186 Interfacing with 6800-series MPU 16-Bit Bus (P68 = "H", BS2=L, BS1 = "H", BS0 = "H") ........................ 186 Interfacing with 8080-series MPU 18-Bit Bus (P68 = "L", BS2=H, BS1 = "H", BS0 = "L") ......................... 187
9.1.10 Interfacing with 6800-series MPU 18-Bit Bus (P68 = "H", BS2=H, BS1 = "H", BS0 = "L") ........................ 187
9.2
CONNECTIONS WITH LCD PANEL .......................................................................................................188

9.2.1 9.2.2 One Layer Connection for Gate output.......................................................................................................... 188 Two Layer Connection for Gate output.......................................................................................................... 189
9.3
EXAMPLE CONNECTION WITH PANEL (CASE11) ..............................................................................190
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9.4 9.5
CONNECTION EXAMPLE WITH EXTERNAL COMPONENTS .............................................................191

9.4.1 Application Circuit Example ........................................................................................................................... 192
EXTERNAL COMPONENTS CONNECTION..........................................................................................193
10 CHIP INFORMATION
194
10.1 CHIP OVERVIEW ....................................................................................................................................194 10.2 BUMP INFORMATION.............................................................................................................................196

10.2.1 Source / Gate / VCOM / Gate control / Output side dummy Pad Format ..................................................... 196 10.2.2 Input / Input side dummy Pad Format ........................................................................................................... 197
10.3 PAD COORDINATES...............................................................................................................................198
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LDS285
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Document No: LTT285A-000
Prepared by: Sam_oh
REVISION HISTORY
Date Oct. 17, 2006 Feb. 1, 2007 Mar. 1, 2007 Contents - Preliminary Version 0.00. Totally revised Command , EEPROM and DBC description Version Ver. 0.00 (Preliminary) Ver. 1.00 (Preliminary) Ver. 2.00 (Preliminary)
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LDS285
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DESCRIPTION
LDS285 is a single chip low power CMOS LCD controller/driver for color TFT-LCD displays of 320 gates and 240xRGB columns. It has a 1.84M-bit (240 x 24bit x 320) display RAM and a full set of control functions. LDS285 offers 10 kinds microprocessor interfaces: 8080-system (8-bit, 9-bit, 16-bit, 18-bit), 6800-system (8-bit, 9-bit, 16-bit, 18-bit) and serial (3-pin or 4-pin). It also supplies 24-bit or 8-bit RGB interface for driving Video signal directly from controller.
FEATURES
Single chip TFT-LCD controller/driver Outputs: - 720 source outputs (240 x RGB) - 320 gate outputs - Common electrode output Display mode (Color modes): - Full colors (Idle mode off): 16M-colors,262K-colors - Reduced color (Idle mode on): 8-colors (3-bit binary mode) Interface mode (Color modes on the display host interface): - 24 bit/pixel: (RGB) = (888) using the 1.84M-bit frame memory directly - 18 bit/pixel: (RGB) = (666) using the 1.84M-bit frame memory with 256k-colors Display Data RAM (DDRAM): 240 x 320 x 24-bit = 1.84M bit MPU Interfaces: - 3-pin or 4-pin serial interface - 8-bit, 9-bit, 16-bit, 18-bit interface with 8080-series MPU - 8-bit, 9-bit, 16-bit, 18-bit interface with 6800-series MPU - 24-bit or 8-bit RGB interface with graphic controller
Display features - Partial display mode - Software programmable color depth mode - N-line inversion for low cross talk On chip: - DC/DC converter - Adjusted VCOM generation by MTP - Oscillator for display clock generation. - One set of 4 gamma curves with micro-adjustment points - Temperature compensation for display quality Driving algorithm: - Line inversion, frame inversion
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I/O supply voltage range. 1.65 to 3.3V Optional logic supply voltage range VDD1 to VSS1 (when PSEL=Low): 1.65 to 1.95V VDD1 to VSS1 (when PSEL=High): 1.95 to VDD2 Analog supply voltage range VDD2 to VSS2: 2.3 to 3.3V Output voltage levels: - Source output voltage range VS to VSS2: 3.0 to 6.0 V - Common electrode output voltage range Vcom amplitude (max) = 5.5V - VcomH output voltage range VcomH to VSS2 2.0 to 5.0V - VcomL output voltage range VcomL to VSS2 -2.0 to 1.0V - Positive Gate output voltage range: +12.0 to +16.0 V when VR=4 - Negative Gate output voltage range: -8.0 to 12.0 V when VR=4 Low power consumption, suitable for battery operated systems CMOS compatible inputs Optimized layout for COG assembly Temperature range: -30 ~ 70C (to +85C no damage) Support DBC(Dynamic Backlight Control) function and ALS(Ambient light sensing )Function Support normal black / normal white LCD Support wide view angle display
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BLOCK DIAGRAM
TFT-LCD Panel (16M-Color)
S1 - - - - - - - - - - S720 BIAS
Gamma Generator
G1
G320
720 Source Buffer D/A Converter Level Shifter Data Latch
320 Gate Buffer Level Shifter Gate Counter FPC VCOM VCOMH VCOM VCOML C6P C6M VCL C5P C5M C4P C4M C3P C3M VGH VGL C2P C2M CAP C1P C1M AVDD VREG_DC Connect Capacitors CAP
VS VR
VS VR VREF
Booster3 Generator
Row Display Data DDRAM Scan Address 240 x 320 x 24 = 1,843,200 bits Address Counter Counter VD0 VSYNC HSYNC DCK ENABLE VSYNCO RGB I/F Column Address Counter DDRAM Data Generator Instruction Control MPU I/F & Data Latch
(3-/4-pin serial, 8/9/16/18 bit parallel & 24-bit RGB)
VR
Booster2
MTP System Clock Generator
Oscillator
Booster1
VREG_DC
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D23 to D0(SDA)
P68 BS2, BS1, BS0 RESB CSB RDB WRB(D!C) DC(SCL)
ME_CMP SMX, SMY SRGB, SINV, EXTC LED_CNT
MPU Interface
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VDC1 VDD2 VDD2_DC VSS2, VSS2_DC VDD1,VDD1_R VDD1_IO VSS1, VSS1_R TGS, FRM , PSEL TEST1, TEST4 TEST2, TEST3 TE OSC
PADB0 to PADB4 PADA0 to PADA4
LDS285
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PIN DESCRIPTION
Pin Description
Table 4.1.1
Name
Type
Description Source driver output pins. Gate driver output pins. I/O power voltage level selection pin. When PSEL=VSS2: I/O signal voltage should be less than 1.95V and in this case, VDD1_IO and VDD1 should be connected together and external power for I/O system should be supplied to those pins ( VDD1_IO and VDD1) When PSEL=VDD2: I/O signal voltage should be larger than 1.95V and in this case, VDD1_IO and VDD1 should not be connected together and external power for I/O system should be supplied to VDD1_IO and VDD1 should have stabilization capacitor (about 2.2uF) to VSS. Power supply for I/O circuit system. (Refer PSEL pin description) Power supply for logic system. (Refer PSEL pin description) Power supply for analog system and boosting input voltage. 2.3V~3.3V supported. All VDD2 and VDD2_DC pins must be externally connected. System ground for logic and analog circuits. All VSS1,VSS1_R and VSS2,VSS2_DC pins MUST be externally connected to system ground. Dummy VDD1_IO power output pin. It can be used to fix some input pins to H level and must be left open if not used. Dummy VSS1 power output pin. It can be used to fix some input pins to L level and must be left open if not used. MACRO EEPROM write - erase power. When you write on internal EEPROM you must provide power through this pin and it must be left open when you do not write on EEPROM.
Driver output pins S1 to S720 O G1 to G320 O Power supply pins
PSEL
VDD1_IO VDD1, VDD1_R VDD2, VDD2_DC VSS1, VSS1_R, VSS2 VSS2_DC D_VDD1O D_VSS1 ME_CMP
P P P
PO PO P
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Pin Description (continued)
Name Type Description LCD supply voltage generation (DC-DC converter and Regulator) C1P to Capacitor connection pins for booster circuits. I/O C6P, C1M to C6M Output of booster circuit (2*VDD2 or 3*VREG_DC). AVDD O Connect capacitor to VSS (GND) 1st booster reference voltage Using VS<4.2V , VDC1 and VDD2_DC should be connected together VDC1 I Using VS>4.2V , VDC1 and VREG_DC should be connected together Output of the VREG_DC regulator Connect capacitor between VREG_DC and system ground (GND). VREG_DC O Using VS>4.2V , VDC1 and VREG_DC should be connected together Output of the VR regulator. VR O Connect capacitor between VR and system ground (GND). Output of the VS regulator. All VS pads in left side and right side must be connected together by external metal layer for lower resistance. VS O Connect stabilizing capacitor between VS and system ground (GND). Positive reference voltage for gate driver circuits (3*VR or 4*VR). VGH O Please refer to the 5.9.2 Various Boosting Steps for details Negative reference voltage for gate driver circuits (-2*VR or -3*VR). VGL O Please refer to the 5.9.2 Various Boosting Steps for details VCL Negative voltage output of booster circuits for VCOM (-1*VDD2) O VCOMH Positive voltage output of VCOM. O VCOML Negative voltage output of VCOM. O Common output signal. VCOM O The swing voltage level is VCOML to VCOMH.
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Name Type Host interface pins P68,BS2,BS1, I BS0 RESB I
Description Interface mode setting (Please refer to the section 5.1). In the serial interface mode, RGB interface mode can be used by ENABLE pin. This signal will reset the device and must be applied to properly initialize the chip. Signal is active low. Chip select input pin (Low enable). This pin can be permanently fixed Low in parallel interface mode only. If CSB is connected to ground in Parallel interface mode, there will be no abnormal visible effect to the display module. Also there will be no restriction on using the Parallel Read/Write protocols, Power On/Off Sequences or other functions. Furthermore there will be no influence to the Power Consumption of the display module. Display data / Command selection pin in parallel interface. In serial I/F, this is used SCL. If not used, please connect to ground or VDD1_IO this pin. Write enable in 8080-series parallel interface. Read write selection in 6800-series parallel interface. In serial I/F, this is used D/!C for 4-line serial. If not used, please connect to ground or VDD1_IO this pin. Read enable in 8080-series parallel interface. Read/write enable in 6800-series parallel interface. If not used, please connect to ground or VDD1_IO this pin. Tearing effect output. If not used, please open this pin. 18-Bit bi-directional display data bus for parallel interface with MPU. 16-Bit bi-directional display data bus for parallel interface with MPU. 9-Bit bi-directional display data bus for 9-bit parallel interface. 8-Bit bi-directional display data bus for 8-bit parallel interface. 8-Bit command bus for 18-bit, 16-bit, 9-bit and 8-bit parallel interface. In 8-bit parallel, D7 to D0 are used and the others (D23 to D8) should be connected to VSS1. In 9-bit parallel, D8 to D0 are used and the others (D23 to D9) should be connected to VSS1. In 16-bit parallel, D23 to D16 are not used and should be connected to VSS1. In 18-bit parallel, D23 to D18 are not used and should be connected to VSS1. In serial interface, D23 to D1 are not used and should be let open or connected to VSS1. In only RGB interface, D23 to D18 are used.
CSB (!SCE)
D/!C(SCL)
WRB (RW) (D/!C)
RDB (E) TE
I O
D23to D8, D7 to D0
I/O
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Name Mode Select SRGB SINV SMX SMY EXTC
Type I I I I I
Description Module RGB order select pin. (Refer section 8.2) Source output data polarity select pin. (SINV=H: Data reverse) (Refer section 8.2) Module Source output direction select pin. (Refer section 8.2) Module Gate output direction select pin. (Refer section 8.2) Enable pin for extended command set and test command set. To use extended command set and test command set (such as EEPROM WRITE), please connect this pin to VDD1_IO. During normal operation, please open this pin. (Internal Rpull-down=15K) Enable pin for extended command set. To use extended command and normal command sets only, please connect this to VSS1 and make EXTC connected to VSS1 or open. ( The test commands can not be used and are treated as NOPs). To use normal command set only, please connect this to VDD1 and open EXTC. Back-light control output. If not used, please open this pin
TGS
LED_Control LED_CNT O
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Name Type Description Clock input and RGB interface Oscillator input for test purpose. OSC I If not used, please connect this pin to VSS1 Vertical sync input for RGB interface. VSYNC I It used as a start pulse input for the gate driver circuits. If not used, please connect this pin to VSS1. Horizontal sync input for RGB interface. HSYNC I It used as a start pulse input to receive the valid data for the source driver circuits. If not used, please connect this pin to VSS1. Pixel data clock input for RGB interface. When the RGB interface is used, the dot clock is input. The RGB data of VD17 to DCK I VD0 pins are read at the rising edge or falling edge of this signal. If not used, please connect this pin to VSS1. RGB interface enable pin. ENABLE I This pin is used for the RGB data enable signal when RGB interface is used. If not used, please connect this pin to VSS1. LSB of RGB interface data bus. Since D23~D1 are shared between RGB interface and parallel interface, only VD0 is VD0 I used. If not used, please connect these pins to VSS1. RGB interface vertical sync output for RGB interface. VSYNCO O If not used, please open this pin. Test pins Pins for display glass break detection. PADA0 Refer to the section 5.14.4 for details. I PADB0 If not used, please open these pins. PADA1 to Pins for chip attachment detection. PADA4 Refer to the section 5.14.3 for details. I PADB1 to If not used, please open these pins. PADB4 Test input pin. Free Running Mode test. You can use this pin when you do reliability test for your panel. FRM I If not used, please open this pin (Internal Rpull-down=15K). TEST1 O Test pin, not accessible to user must be left open. TEST2 I Test pin, not accessible to user must be left open. TEST3 I Test pin, not accessible to user must be left open. TEST4 O Test pin, not accessible to user must be left open. Dummy pins. Dummy These pins can be used for ITO routing. NOTE: DUMMY These pins should be open (float).
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5
5.1
FUNCTIONAL DESCRIPTION
MPU INTERFACE
LDS285 can interface with MPU at high speed. However, if the interface cycle time is faster than the limit, MPU needs to have dummy wait(s) to meet the cycle time limit.
5.1.1
Interface Type Selection
The selection of a given interfaces are done by setting P68, BS2, BS1 and BS0 pins as shown in Table 5.1.1 and
Table 5.1.2.
Table 5.1.1 Interface Type Selection
P68 BS1 BS1 BS0 Interface Read back select 0 0 0 0 3-Pin Serial Interface Via the read instruction (8-bit, 24-bit and 32-bit read parameter) 0 0 0 1 8080 MPU 8-bit Parallel RDB strobe (8-bit read data and 8-bit read parameter) 0 0 1 1 8080 MPU 16-bit Parallel RDB strobe (16-bit read data and 16-bit read parameter) 0 1 0 0 8080 MPU 9-bit Parallel RDB strobe (9-bit read data and 8-bit read parameter) 0 1 1 0 8080 MPU 18-bit Parallel RDB strobe (18-bit read data and 16-bit read parameter) 1 0 0 0 4-Pin Serial Interface Via the read instruction (8-bit, 24-bit and 32-bit read parameter) 1 0 0 1 6800 MPU 8-bit Parallel E strobe (8-bit read data and 8-bit read parameter) 1 0 1 1 6800 MPU 16-bit Parallel E strobe (16-bit read data and 16-bit read parameter) 1 1 0 0 6800 MPU 9-bit Parallel E strobe (9-bit read data and 8-bit read parameter) 1 1 1 0 6800 MPU 18-bit Parallel E strobe (18-bit read data and 16-bit read parameter)
Table 5.1.2
Pin Connection according to the Interface Type
P68 BS2 BS1 BS0 Interface RDB 0 0 0 0 3-Pin Serial Interface *1) 0 0 0 1 8080 MPU 8-bit Parallel RDB 0 0 1 1 8080 MPU 16-bit Parallel RDB 0 1 0 0 8080 MPU 9-bit Parallel RDB 0 1 1 0 8080 MPU 18-bit Parallel RDB 1 0 0 0 4-Pin Serial Interface *1) 1 0 0 1 6800 MPU 8-bit Parallel E 1 0 1 1 6800 MPU 16-bit Parallel E 1 1 0 0 6800 MPU 9-bit Parallel E 1 1 1 0 6800 MPU 18-bit Parallel E NOTE: 1) Unused pins can be open, connected to VSS1
WRB DC D23-D0 *1) SCL *1) D23-D1: Unused, D0: SDA WRB DC *1) D23-D8: Unused, D7-D0: 8-bit Data WRB DC *1) D23-D16: Unused, D15-D0: 16-bit Data WRB DC *1) D23-D9: Unused, D8-D0: 9-bit Data WRB DC *1) D23-D18: Unused, D17-D0: 18-bit Data DC SCL *1) D23-D1: Unused, D0: SDA RW DC *1) D23-D8: Unused, D7-D0: 8-bit Data RW DC *1) D23-D16: Unused, D15-D0: 16-bit Data RW DC *1) D23-D9: Unused, D8-D0: 9-bit Data RW DC *1) D23-D18: Unused, D17-D0: 18-bit Data
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5.1.2
General Protocol
For programming of the LCD driver, the general supported protocol is shown in Fig. 5.1.1
TB
TB
TB
TB
TB
TB
S: Start data tranamission P: Stop data tranamission TB: tranamission byte
Fig. 5.1.1
Programming protocol
If data write or parameter write is interrupted by any other command, data write command or parameter write command should be done again to write the remained data or parameter.
Command1 code (with 3 parameter) CMD1 PARA11 PARA12 PARA13
Command1 code is interrupped by command2

CMD1
PARA11
CMD2
CMD1
PARA11
PARA12
PARA13
Command1 with 1st parameter (PARA11) should be executed again to write remained parameter (PARA12 and PARA13)
Fig. 5.1.2
Write interrupt sequence
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5.1.3
8080-Series Parallel Interface (P68 = "L")
The 8080-series bi-directional interface can be used for communication between the micro controller and the LCD driver chip. The selection of this interface is done when P68 pin is L state (VSS1). Interface bus width can be selected with BS2, BS1 and BS0. The interface functions of the parallel interface (8080-series) are given in Table 5.1.3.
Table 5.1.3 Parallel Interface Function (8080-series, P68=L)
BS2
BS1
BS0
Interface
DC 1 0 1 1 1 0 1 1 1
8080-series RDB WRB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Function Write 8-bit display data or 8-bit parameter (D7 to D0) Write 8-bit command (D7 to D0) Read 8-bit display data (D7 to D0) *1) Read 8-bit parameter or status (D7 to D0) Write 16-bit display data (D15 to D0) or 8-bit parameter (D7 to D0) Write 8-bit command (D7 to D0) Read 16-bit display data (D15 to D0) *1) Read 8-bit parameter or status (D7 to D0) Write 9-bit display data(D8 to D0) or 8-bit parameter (D7 to D0) Write 8-bit command (D7 to D0) Read 9-bit display data (D8 to D0) *1) Read 8-bit parameter or status (D7 to D0) Write 18-bit display data (D17 to D0) or 8-bit parameter (D7 to D0) Write 8-bit command (D7 to D0) Read 18-bit display data (D17 to D0) *1) Read 8-bit parameter or status (D7 to D0)
8-bit interface
16-bit interface
9-bit interface
0 1 1
18-bit interface
1 0 1 1
NOTE: = rising edge *1) Applied for command code: DAh, DBh, DCh, 0Ah, 0Bh, 0Ch, 0Dh, 0Eh, 0Fh, 04h and 09h
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The parallel interface timing diagram is given in Fig. 5.1.3 and Fig. 5.1.4.
1-byte command 2-byte command n-byte command (number of parameter = n-1)
CMD
CMD
PA 1
CMD
PA 1
PA n-2
PA n-1
CSB DC RDB WRB D[K:0] Host D[K:0] (MPU to LCD) Driver D[K:0] (LCD to MPU)
PA 1
CMD
CMD
PA 1
CMD
PA n-2
PA n-1
CMD
CMD
PA 1 Hi-Z
CMD
PA 1
PA n-2
PA n-1
CMD: Write command code PA: Write parameter or RAM data [K:0] : K means the used data bus. Refer to table 5.1.3
Signals on D[K:0], DC, RDB and WRB pins during CSB=H are ignored.
Fig. 5.1.3
8080-Series parallel bus protocol, write to register or display DDRAM
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Read parameter
Read display RAM data
CMD
DM
PA
CMD
DM
Data
Data
CSB DC RDB WRB D[K:0] Host D[K:0] (MPU to LCD) Driver D[K:0] (LCD to MPU)
Hi-Z
CMD
DM
PA
CMD
DM
PA
PA
CMD Hi-Z
Hi-Z
CMD Hi-Z
Hi-Z Hi-Z
DM
PA
DM
PA
PA
Fig. 5.1.4
8080-Series parallel bus protocol, read from register
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5.1.4
6800-Series Parallel Interface (P68 = "H")
The 6800-series bi-directional interface can be used for communication between the micro controller and the LCD driver chip. The selection of this interface is done when P68 pin is H state (VDD1_IO). Interface bus width can be selected with BS2, BS1 and BS0. The interface functions of the parallel interface (6800-series) are given in Table 5.1.4.
Table 5.1.4 Parallel Interface Function (6800-series, P68=H)
BS2
BS1
BS0
Interface
DC 1 0 1 1
6800-series RW E 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1
Function Write 8-bit display data or 8-bit parameter (D7 to D0) Write 8-bit command (D7 to D0) Read 8-bit display data (D7 to D0) *1) Read 8-bit parameter or status (D7 to D0) Write 16-bit display data (D15 to D0) or 8-bit parameter (D7 to D0) Write 8-bit command (D7 to D0) Read 16-bit display data (D15 to D0) *1) Read 8-bit parameter or status (D7 to D0) Write 9-bit display(D8 to D0) data or 8-bit parameter (D7 to D0) Write 8-bit command (D7 to D0) Read 9-bit display data (D8 to D0) *1) Read 8-bit parameter or status (D7 to D0) Write 18-bit display data (D17 to D0) or 8-bit parameter (D7 to D0) Write 8-bit command (D7 to D0) Read 18-bit display data (D17 to D0)
8-bit interface
16-bit interface
1 0 1 1 1
9-bit interface
0 1 1 1
18-bit interface
0 1
*1) Read 8-bit parameter or status (D7 to D0) 1 1 NOTE: = falling edge *1) Applied for command code: DAh, DBh, DCh, 0Ah, 0Bh, 0Ch, 0Dh, 0Eh, 0Fh, 04h and 09h
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The parallel interface timing diagram is given in Fig. 5.1.5 and Fig. 5.1.6.
1-byte command 2-byte command n-byte command (number of parameter = n-1)
CMD
CMD
PA 1
CMD
PA 1
PA n-2
PA n-1
CSB DC RW E D[K:0] Host D[K:0] (MPU to LCD) Driver D[K:0] (LCD to MPU)
PA 1
CMD
CMD
PA 1
CMD
PA n-2
PA n-1
CMD
CMD
PA 1 Hi-Z
CMD
PA 1
PA n-2
PA n-1
Signals on D[K:0], DC, RW and E pins during CSB=H are ignored.
Fig. 5.1.5
6800-Series parallel bus protocol, write to register or display DDRAM
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Read parameter
Read display RAM data
CMD
DM
PA
CMD
DM
Data
Data
CSB DC RW E D[K:0] Host D[K:0] (MPU to LCD) Driver D[K:0] (LCD to MPU)
Hi-Z
CMD
DM
PA
CMD
DM
PA
PA
CMD Hi-Z
Hi-Z
CMD Hi-Z
Hi-Z Hi-Z
DM
PA
DM
PA
PA
Fig. 5.1.6
6800-Series parallel bus protocol, read from register
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5.1.5
Serial Interface
Communication with the microprocessor can also be done via a clock-synchronized serial peripheral interface. The selection of this interface is done when all of BS2, BS1 and BS0 are L state (VSS1). The serial interface is a 3-pin or 4-pin bi-directional interface for communication between the micro controller and the LCD driver chip. The 3-pin serial use: SCEB (chip enable), SCL (serial clock) and SDA (serial data input/output) and 4-pin serial use: SCEB (chip enable), DC (data / command select), SCL (serial clock) and SDA (serial data input/output). Serial clock (SCL) is controlled for interface only by MPU, so it can be stopped when the communication is not necessary. 5.1.5.1 Write Mode
The write mode of the interface means the micro controller writes commands and data to the LDS285. 3-Pin serial data packet contains a control bit DC and a transmission byte and in 4-pin serial case, data packet contains just transmission byte and control bit DC is transferred by the DC pin. If DC is L, the transmission byte is interpreted as a command byte. If DC is H, the transmission byte is stored in the display data RAM (Memory write command), or command register as a parameter. Any instruction can be sent in any order to the LDS285. The MSB is transmitted first. The serial interface circuits are initialized when the SCEB is H state. In this initialize state, SCL clock pulse or SDA data inputs have no effect. A falling edge of SCEB enables the serial interface and indicates the start of data transmission.
3-Line Serial Data Stream Format

Transmission byte (TB) may be a Command or a Data
MSB
LSB
DC D7 D6 D5 D4 D3 D2 D1 D0
DC
TB
DC
TB
DC
TB
4-Line Serial Data Stream Format

Transmission byte (TB) may be a Command or a Data
MSB
LSB
D7 D6 D5 D4 D3 D2 D1 D0 TB TB TB
Fig. 5.1.7
Serial data stream, write mode
When SCEB is H state, SCL clock is ignored. During the high time of SCEB the serial interface is initialized. At the falling SCEB edge, SCL can be high or low (see Fig 5.1.8). SDA is sampled at the rising edge of SCL. DC indicates, whether the byte is command code (DC=0) or parameter/DDRAM data (DC=1). It is sampled when first rising SCL edge (3-line serial interface) or 8th rising SCLK edge (4-line serial interface). If SCEB stays low after the last bit of command/data byte, the serial interface expects the DC bit (3-line serial interface) or D7 (4-line serial interface) of the next byte at the next rising edge of SCL.
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1) 3-Pin Serial Interface Protocol

S TB TB P
SCEB Host
(MPU to Driver)
SCL SDA
D7
D6
D5
D4
D3
D2
D1
D0
D/!C
D7
D6
D5
D4
D3
D2
D1
D0
Command
Command / parameter
SCEB can be H between parameter / command and parameter / command, but SCL and SDA during SCEB = H is invalid
2) 4-Pin Serial Interface Protocol

S TB TB P
SCEB Host
(MPU to Driver)
SCL SDA DC
Command
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D/!C
Command / parameter
SCEB can be H between parameter / command and parameter / command, but SCL and SDA during SCEB = H is invalid
Fig. 5.1.8
Serial bus protocol, write to register with control bit in transmission
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5.1.5.2
Read Mode
The read mode of the interface means that the micro controller reads register value from the LDS285. To do so the micro controller first has to send a command (Read ID or Read Register command) and then the following byte is transmitted in the opposite direction. After that, SCEB is required to go high before a new command is send (see Fig. 5.1.9 and Fig. 5.1.10). The LDS285 samples the SDA (input data) at the rising edges, but shifts SDA (output data) at the falling SCL edges. Thus the micro controller is supported to read data at the rising SCL edges. After the read status command has been sent, the SDA line must be set to tri-state no later than at the falling SCL edge of the last bit (see Fig. 5.1.9 and Fig. 5.1.10).
3-Pin Serial Protocol (for RDID1/RDID2/RDID3/0Ah/0Bh/0Ch/0Dh/0Eh/0Fh command: 8-bit read)

S TB TB P S
SCEB
Host
SCL SDA (SDI)

DC D7 D6 D5 D4 D3 D2 D1 D0
High-Z
DC
Driver
SDA (SDO)
High-Z
D7 D6 D5 D4 D3 D2 D1 D0
3-Pin Serial Protocol (for RDDID command: 24-bit read)

S TB TB P S
SCEB
Host
SCL SDA (SDI)

DC D7 D6 D5 D4 D3 D2 D1 D0
High-Z
DC
Driver
SDA (SDO)
High-Z
D23
D22 D21
D20 D19
D3
D2
D1 D0
Dummy Clock Cycle
3-Pin Serial Protocol (for RDDST command: 32-bit read)

S TB TB P S
SCEB
Host
SCL SDA (SDI)

DC D7 D6 D5 D4 D3 D2 D1 D0
High-Z
DC
Driver
SDA (SDO)
High-Z
D31 D30 D29
D28 D27
D3
D2
D1 D0
Dummy Clock Cycle
Fig. 5.1.9
Serial bus protocol, read mode (3-Pin serial interface case)
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4-Pin Serial Protocol (for RDID1/RDID2/RDID3/0Ah/0Bh/0Ch/0Dh/0Eh/0Fh command: 8-bit read)

S TB TB P S
SCEB SCL
Host
DC SDA (SDI)
D7 D6 D5 D4 D3 D2 D1
D0
High-Z
D7
Driver
SDA (SDO)
High-Z
D7
D6
D5
D4
D3
D2
D1 D0
4-Pin Serial Protocol (for RDDID command: 24-bit read)

S TB TB P S
SCEB SCL
Host
DC SDA (SDI)
D7 D6 D5 D4 D3 D2 D1
D0
High-Z
D7
Driver
SDA (SDO)
High-Z
D23
D22 D21
D20 D19
D3
D2
D1 D0
Dummy Clock Cycle
4-Pin Serial Protocol (for RDDST command: 32-bit read)

S TB TB P S
SCEB SCL
Host
DC SDA (SDI)
D7 D6 D5 D4 D3 D2 D1
D0
High-Z
D7
Driver
High-Z
SDA (SDO)
D31
D30 D29
D28 D27
D3
D2
D1 D0
Dummy Clock Cycle
Fig. 5.1.10
Serial bus protocol, read mode (4-Pin serial interface case)
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5.1.6
Interface Pause
It will be possible when transferring a Command, DDRAM Data or Multiple Parameter Data to invoke a pause in the data transmission. If the Chip Select Line (CSB) is released after a whole byte of a DDRAM Data or Multiple Parameter Data has been completed, then LDS285 will wait and continue the DDRAM Data or Parameter Data Transmission from the point where it was paused. If the Chip Select Line is released after a whole byte of a command has been completed, then the Display Module will receive either the commands parameters (if appropriate) or a new command when the Chip Select Line is next enabled as shown below. This applies to the following 4 conditions: 1) Command-Pause-Command 2) Command-Pause-Parameter 3) Parameter-Pause-Command 4) Parameter-Pause-Parameter
5.1.6.1 Parallel Interface Pause
CSB DC RDB WRB D[7:0]

D7 to D0
Pause
D7 to D0
Command / Parameter
Pause
Command / Parameter
Fig. 5.1.11
Parallel bus protocol, write mode paused by CSB
5.1.6.2
Serial Interface Pause
TB
TB
SCEB Host
(MPU to Driver)
Pause
SCL SDA
DC D7 D6 D5 D4 D3 D2 D1 D0 DC D7 D6 D5 D4 D3 D2 D1 D0
Command / Parameter / Data

SCL and SDA during CSB = H is invalid
Fig. 5.1.12
Serial bus protocol, write mode paused by SCEB (3-Pin serial case)
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5.1.7
Data Transfer Recovery
If there is a break in data transmission by RESB pulse, while transferring a Command or DDRAM Data or Multiple Parameter command Data, before Bit D0 of the byte has been completed, then LDS285 will reject the previous bits and have reset the interface such that it will be ready to receive command data again when the chip select line (SCEB) is next activated after RESB have been High state. See the following example (See Fig.
5.1.13)
If there is a break in data transmission by SCEB pulse, while transferring a Command or DDRAM Data or Multiple Parameter command Data, before Bit D0 of the byte has been completed, then LDS285 will reject the previous bits and have reset the interface such that it will be ready to receive the same byte re-transmitted when the chip select line (SCEB) is next activated. See the following example (See Fig. 5.1.14)
TB
TB
SCEB RESB Host

(MPU to Driver)
Wait for more than 10s
SCL SDA
DC D7 D6 D5 D4 D3 D2 DC D7 D6 D5 D4 D3 D2 D1 D0
Command
SCL and SDA during RESB = L is invalid and next byte becomes command
Fig. 5.1.13
Serial bus protocol, write mode interrupted by RESB
TB
TB
SCEB SCL Host

(MPU to Driver)
SDA
DC
D7
D6
D5
D4
DC
D7
D6
D5
D4
D3
D2
D1
D0
Break
Fig. 5.1.14
Serial bus protocol, write mode interrupted by SCEB
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If 1, 2 or more parameter command is being sent and a break occurs while sending any parameter before the last one and if the host then sends a new command rather than re-transmitting the parameter that was interrupted, then the parameters that were successfully sent are stored and the parameter where the break occurred is rejected. The interface is ready to receive next byte as shown in Fig. 5.1.15.
Break
PARA11 is sucessfully sended but PARA12 is breaked and need to be transfered again
CMD1
PARA11
PARA12
CMD2
CMD1
PARA11
PARA12
PARA13
Fig. 5.1.15
Write interrupt recovery (serial interface)
If a 2 or more parameter command is being sent and a break occurs by the other command before the last one is sent, then the parameters that were successfully sent are stored and the other parameter of that command remains previous value.
Break
PARA11 is sucessfully sent but the other parameters are not sent and break happeds by the other command.
CMD1
PARA11
CMD2
CMD1
PARA11
PARA12
PARA13
Fig. 5.1.16
Write interrupt recovery (both serial and parallel interface)
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5.1.8
Display Module Data Transfer Modes
The Module has two kinds color modes for transferring data to the display RAM. These are 18-bit color per pixel and 24-bit color per pixel. The data format is described for each interface. Data can be downloaded to the DDRAM by 2 methods.
5.1.8.1 Method 1
The Image data is sent to the DDRAM in successive Frame writes, each time the DDRAM is filled, the DDRAM pointer is reset to the start point and the next Frame is written.
Start Start DDRAM Write Image Data Frame 1 Image Data Frame 2 Image Data Frame 3 Stop Any Command
5.1.8.2
Method 2
Image Data is sent and at the end of each DDRAM download, a command is sent to stop DDRAM Write. Then Start Memory Write command is sent, and a new Frame is downloaded.
Start Start DDRAM Write Image Data Frame 1 Any Command Start DDRAM Write Image Data Frame 2 Any Command
Stop Any Command
Note: 1) These apply to all Data Transfer Color modes on both Serial and Parallel interfaces. 2) The DDRAM can contain both odd and even number of pixels for both Methods. Only complete pixel data will be stored in the DDRAM.
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5.2 DISPLAY DATA RAM (DDRAM)

The LDS285 has an integrated 240x320x24-bit graphic type static RAM. This 1.84M-bit memory allows to store on-chip a 240xRGBx320 image with an 24-bpp resolution (16M-color). There will be no abnormal visible effect on the display when there is a simultaneous Panel Read and Interface Read or write to the same location of the DDRAM.
Display Data RAM Organization

LCD Glass
(240 x 320 x RGB)
MPU I/F
Data Gen. ( Data sum-up and Expand) Row Address Counter Column Address Counter
Latch
Display Data RAM

(240 x 320 x 24-bit)
Line Address Counter Scan Address Counter
Host Interface
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5.2.1
5.2.1.1
Display Data Formats

Serial Interface Mode (3-Pin serial I/F)
Different display data formats are available for two colors depth supported by the LDS285 listed below. 262k colors, RGB 6-6-6-bits input (see Table 5.2.1) 16M colors, RGB 8-8-8-bits input (see Table 5.2.2)
Table 5.2.1 SCL
Write data for RGB 6-6-6-bits input
SDA
R15 R14
R13 R12 R11 R10
G15 G14
G13 G12 G11 G10
B15 B14
B13 B12 B11 B10
18-bit
LSB Expansion DB[5] DB[4] DB[3] DB[2] DB[1] DB[0]
DB[5]
DB[4]
DB[3]
DB[2]
DB[1]
DB[0]
DB[5]
DB[4]
24-bit
Frame memory
R1 G1 B1
R2 G2 B2
R3 G3 B3
NOTE: 1 pixel data with the 18-bit color depth information. The most significant bits are: Rx5, Gx5 and Bx5. The least significant bits are: Rx0, Gx0 and Bx0.
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Table 5.2.2 SCL
SDA
R17 R16 R15 R14 R13 R12 R11 R10
G17 G16 G15 G14 G13 G12 G11 G10
B17 B16 B15 B14 B13 B12 B11 B10
24-bit
Frame memory
R1 G1 B1
R2 G2 B2
R3 G3 B3
NOTE: 1 pixel data with the 24-bit color depth information. The most significant bits are: Rx7, Gx7 and Bx7. The least significant bits are: Rx0, Gx0 and Bx0.
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5.2.1.2
8-Bit Parallel Interface Mode
Different display data formats are available for two colors depth supported by the LDS285 listed below. 262k colors, RGB 6-6-6-bits input (see Table 5.2.3) 16M colors, RGB 8-8-8-bits input (see Table 5.2.4) Read (see Table 5.2.5)
Table 5.2.3 Write data for RGB 6-6-6-bits input

X : Dont care
262k Color data DC MEMWR 0 1st write 2nd write 3rd write 4th write 5th write 6th write 1 1 1 1 1 1
D7 R15 G15 B15 R25 G25 B25
D6 D5 D4 D3 D2 D1 Memory Write Command Code R14 G14 B14 R24 G24 B24 R13 G13 B13 R23 G23 B23
18-bit
D0 x x x x x x
Memory Write 1st pixel data (R1/G1/B1) 2nd pixel data (R2/G2/B2)
R12 G12 B12 R22 G22 B22
R11 G11 B11 R21 G21 B21

18-bit
R10 G10 B10 R20 G20 B20
x x x x x x
DB[5]
DB[4]
DB[3]
DB[2]
DB[1]
DB[0]
DB[5]
DB[4]
24-bit
24-bit
Frame memory
R1 G1 B1
R2 G2 B2
R3 G3 B3
NOTE: 3 times transfer is used to transmit 1 pixel data with the 18-bit color depth information. The most significant bits are: Rx5, Gx5 and Bx5. The least significant bits are: Rx0, Gx0 and Bx0.
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Table 5.2.4

X : Dont care
262k Color data DC MEMWR 0 1st write 2nd write 3rd write 4th write 5th write 6th write 1 1 1 1 1 1
D7 R17 G17 B17 R27 G27 B27
D6 D5 D4 D3 D2 D1 Memory Write Command Code R16 G16 B16 R26 G26 B26 R15 G15 B15 R25 G25 B25 R14 G14 B14 R24 G24 B24 R13 G13 B13 R23 G23 B23 R12 G12 B12 R22 G22 B22 R11 G11 B11 R21 G21 B21
D0 R10 G10 B10 R20 G20 B20
Memory Write st 1 pixel data (R1/G1/B1) nd 2 pixel data (R2/G2/B2)
24-bit
24-bit
Frame memory
R1 G1 B1
R2 G2 B2
R3 G3 B3
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Table 5.2.5
Read
Frame memory
R1 G1 B1
R2 G2 B2
R3 G3 B3
24-bit
X : Dont care
16M Color data MEMRD dummy 1st Read 2nd Read 3rd Read
DC 0 1 1 1 1
D7 x R17 G17 B17
D6 D5 D4 D3 D2 D1 Memory Read Command Code x x x x x x R16 G16 B16 R15 G15 B15 R14 G14 B14 R13 G13 B13 R12 G12 B12 R11 G11 B11
D0 x R10 G10 B10
Memory Read 1st pixel data (R1/G1/B1)
NOTE: 3 times transfer is used to transmit 1 pixel data with the 24-bit color depth information. The read data can be different to the written data because of the LSB Expansion.
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5.2.1.3
Table 5.2.6

X : Dont care
262k Color data MEMWR 1st write 2nd write 3rd write 4th write
DC 0 1 1 1 1
D8 x
D7
D6
D5
D4
D3
D2
D1
D0
Memory Write st -1 pixel data (R1/G1/B1) -2nd pixel data (R2/G2/B2)
Memory Write Command Code R11 B14 R21 B24 R10 G15 G14 G13 B13 B12 B11 B10 R20 G25 G24 G23 B23 B22 B21 B20
R15 R14 R13 R12 G12 G11 G10 B15 R25 R24 R23 R22 G22 G21 G20 B25
18-bit
18-bit
DB[5]
DB[4]
DB[3]
24-bit
DB[2]
DB[1]
24-bit
DB[0]
DB[5]
DB[4]
Frame memory
R1 G1 B1
R2 G2 B2
R3 G3 B3
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LDS285
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Table 5.2.7

X : Dont care
262k Color data MEMWR 1 write 2nd write 3rd write 4th write 5th write 6th write
st
DC 0 1 1 1 1 1 1
D8
D7
D6
D5
D4
D3
D2
D1
D0
Memory Write -
Memory Write Command Code x x x x x x R17 G17 B17 R27 G27 B27 R16 G16 B16 R26 G26 B26 R15 G15 B15 R25 G25 B25 R14 G14 B14 R24 G24 B24 R13 G13 B13 R23 G23 B23 R12 G12 B12 R22 G22 B22 R11 G11 B11 R21 G21 B21 R10 G10 B10 R20 G20 B20
st 1 pixel data (R1/G1/B1) nd 2 pixel data (R2/G2/B2)
24-bit
24-bit
Frame memory
R1 G1 B1
R2 G2 B2
R3 G3 B3
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Table 5.2.8
Read
Frame memory
R1 G1 B1
R2 G2 B2
R3 G3 B3
24-bit
X : Dont care
16M Color data DC MEMRD 0 dummy 1 1 Read 2nd Read 3rd Read
st
D8 x x R17 G17 B17
D7 x R16 G16 B16
D6 D5 D4 D3 D2 D1 Memory Read Command Code x x x x x x R15 G15 B15 R14 G14 B14 R13 G13 B13 R12 G12 B12 R11 G11 B11 R10 G10 B10
D0 x x x x
Memory Read 1st pixel data (R1/G1/B1)
1 1 1
NOTE: 3 times transfer is used to transmit 1 pixel data with the 24-bit color depth information. The read data can be different to the written data because of the LSB Expansion.
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LDS285
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5.2.1.4
Table 5.2.9
Write data for RGB 6-6-6-bits input in 16-bit parallel Interface

X : Dont care
262k Color D6 D5 D4 D3 D2 D1 D0 DC D15 D14 D13 D12 D11 D10 D9 D8 D7 data x Memory Write Command Code MEMWR 0 st 1 write 1 R15 R14 R13 R12 R11 R10 x x G15 G14 G13 G12 G11 G10 x x 2 write 3 write
rd nd
Memory Write 1 pixel (R1/G1/B1) 2nd pixel (R2/G2/B2)

st
1 1
B15 B14 B13 B12 B11 B10
x x
R25 R24 R23 R22 R21 R20 x B25 B24 B23 B22 B21 B20 x
x x
G25 G24 G23 G22 G21 G20 x

18-bit 18-bit
DB[5]
DB[4]
DB[3]
DB[2]
24-bit
DB[1]
DB[0]
DB[5]
DB[4]
24-bit
Frame memory
R1 G1 B1
R2 G2 B2
R3 G3 B3
NOTE: 3 times transfer is used to transmit 2 pixels data or 2 times transfer are used to transmit 1 pixel data with the 18-bit color depth information.. The most significant bits are: Rx5, Gx5 and Bx5. The least significant bits are: Rx0, Gx0 and Bx0.
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LDS285
Version 2.00
Table 5.2.10

X : Dont care
16M Color DC D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 data x Memory Write Command Code MEMWR 0 st 1 write 1 R17 R16 R15 R14 R13 R12 R11 R10 G17 G16 G15 G14 G13 G12 G11 G10 2 write 3rd write
nd
Memory Write -
1 1
B15 B14 B13 B12 B11 B10 R27 R26 R25 R24 R23 R22 R21 R20 1st pixel (R1/G1/B1) B17 B16 G27 G26 G25 G24 G23 G22 G21 G20 B27 B26 B25 B24 B23 B22 B21 B20 2nd pixel (R2/G2/B2)
24 bit
24 bit
Frame memory
R1 G1 B1
R2 G2 B2
R3 G3 B3
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Table 5.2.11
Read
Frame memory
R1 G1 B1
R2 G2 B2
R3 G3 B3
24 bit 24 bit
X : Dont care
16M Color DC D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 data x Memory Read Command Code MEMRD 0 x x x x x x x x x x x x x x x x dummy 1 1st Read 1 R17 R16 R15 R14 R13 R12 R11 R10 G17 G16 G15 G14 G13 G12 G11 G10 2 Read 3 Read
rd nd
Memory Read st
1 1
B17 B16 B15 B14 B13 B12 B11 B10 R27 R26 R25 R24 R23 R22 R21 R20 1 pixel (R1/G1/B1) G27 G26 G25 G24 G23 G22 G21 G20 B27 B26 B25 B24 B23 B22 B21 B20 2nd pixel (R2/G2/B2)
NOTE: 3 times transfer is used to transmit 2 pixels data or 2 times transfer are used to transmit 1 pixel data with the 24-bit color depth information.. The read data can be different to the written data because of the LSB Expansion.
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LDS285
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5.2.1.5
Different display data formats are available for four colors depth supported by the LDS285 listed below. 262k colors, RGB 6-6-6-bits input (see Table 5.2.12) 16M colors, RGB 6-6-6-bits input (see Table 5.2.13) Read (see Table 5.2.14)
Table 5.2.12

X : Dont care
262k Color Memory Write DC D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 data x Memory Write Command Code MEMWR 0 st R15 R14 R13 R12 R11 R10 G15 G14 G13 G12 G11 G10 B15 B14 B13 B12 B11 B10 -1st pixel (R1/G1/B1) 1 write 1 2nd write 1 R25 R24 R23 R22 R21 R20 G25 G24 G23 G22 G21 G20 B25 B24 B23 B22 B21 B20 2nd pixel (R2/G2/B2)
18-bit 18-bit
DB[5]
DB[4]
DB[3]
DB[2]
DB[1]
DB[0]
DB[5]
DB[4]
24-bit
24-bit
Frame memory
R1 G1 B1
R2 G2 B2
R3 G3 B3
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LDS285
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Table 5.2.13

X : Dont care
16M Color DC D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 data x Memory Write Command Code MEMWR 0 st 1 write 1 x x R17 R16 R15 R14 R13 R12 R11 R10 G17 G16 G15 G14 G13 G12 G11 G10 2 write 3rd write
nd
Memory Write -
1 1
x x
B15 B14 B13 B12 B11 B10 R27 R26 R25 R24 R23 R22 R21 R20 1st pixel (R1/G1/B1) x B17 B16 x G27 G26 G25 G24 G23 G22 G21 G20 B27 B26 B25 B24 B23 B22 B21 B20 2nd pixel (R2/G2/B2)
24 bit
24 bit
Frame memory
R1 G1 B1
R2 G2 B2
R3 G3 B3
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LDS285
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Table 5.2.14
Read
Frame memory
R1 G1 B1
R2 G2 B2
R3 G3 B3
24 bit
24 bit
X : Dont care
16M Color DC D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 data x Memory Read Command Code MEMRD 0 x x x x x x x x x x x x x x x x x x dummy 1 1st Read 1 R17 R16 R15 R14 R13 R12 R11 R10 x G17 G16 G15 G14 G13 G12 G11 G10 x 2 Read 3 Read
rd nd
Memory Read st
1 1
B17 B16 B15 B14 B13 B12 B11 B10 x R27 R26 R25 R24 R23 R22 R21 R20 x 1 pixel (R1/G1/B1) G27 G26 G25 G24 G23 G22 G21 G20 x B27 B26 B25 B24 B23 B22 B21 B20 x 2nd pixel (R2/G2/B2)
NOTE: 3 times transfer is used to transmit 2 pixels data or 2 times transfer are used to transmit 1 pixel data with the 24-bit color depth information.. The Read data can be different to the written data because of the LSB Expansion.
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LDS285
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5.2.2
RGB Interface
For direct interface with both graphic controller and MPU, LDS285 offers RGB interface mode to receive video data. In RGB interface mode, video data bus becomes (D23 to D1, VD0) and grahic controller can write 24-bit RGB data to predefined row and column address area (by CASET and RASET command) of the DDRAM. Command and parameter to control LDS285 can be accessed by MPU via serial interface mode.
5.2.2.1
RGB Interface Bus Width Set
All 2-kinds of bus width can be available during RGB interface mode. (selected by the 2nd parameter of IFMODE command: DW).
DW D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 0 1 R7 x x x R6 x x x R5 x x x R4 x x x R3 x x x R2 x x x R1 x x x R0 x x x G7 x x x G6 x x x G5 x x x G4 x x x G3 x x x G2 x x x
D9 G1 x x x
D8 G0 x x x
D7 B7 R7 G7 B7
D6 B6 R6 G6 B6
D5 B5 R5 G5 B5
D4 B4 R4 G4 B4
D3 B3 R3 G3 B3
D2 B2 R2 G2 B2
D1 B1 R1 G1 B1
D0 B0 R0 G0 B0
Bus Width 24-bit data 8-bit data
NOTE: Unused RGB data bus must be connected to VSS1.
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- 24-Bit RGB Interface Mode
Different display data formats are available for four colors depth supported by the LDS285 listed below. 262k colors, RGB 6-6-6-bits input when (see Table 5.2.15) 16M colors, RGB 8-8-8-bits input when (see Table 5.2.16)
Table 5.2.15
Write data for RGB 6-6-6-bits input in 24-bit rgb Interface

D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
65k Color data 1 write 2

nd st
Memory Write 1st pixel (R1/G1/B1)

nd
x x
x R15 R14 R13 R12 R11R110 x x R25 R24 R23 R22 R21 R20 x
x G15 G14 G13 G12 G11 G10 x x G25 G24 G23 G22 G21 G20 x
x B15 B14 B13 B12 B11 B10
write
x B25 B24 B23 B22 B21 B20 2
pixel (R2/G2/B2)
18-bit
18-bit
DB[5]
DB[4]
24-bit
DB[3]
DB[2]
DB[1]
DB[0]
DB[5]
DB[4]
24-bit
Frame memory
R1 G1 B1
R2 G2 B2
R3 G3 B3
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LDS285
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Table 5.2.16


nd st
Memory Write 1st pixel (R1/G1/B1)
R17 R16 R15 R14 R13 R12 R11 R110G17 G16 G15 G14 G13 G12 G11 G10 B17 B16 B15 B14 B13 B12 B11 B10
nd write R27 R26 R25 R24 R23 R22 R21 R20G27 G26 G25 G24 G23 G22 G21 G20 B27 B26 B25 B24 B23 B22 B21 B20 2 pixel (R2/G2/B2)
24-bit
24-bit
Frame memory
R1 G1 B1
R2 G2 B2
R3 G3 B3
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LDS285
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- 8-Bit RGB Interface Mode
Different display data formats are available for four colors depth supported by the LDS285 listed below. 262k colors, RGB 6-6-6-bits input when (see Table 5.2.17) 16M colors, RGB 8-8-8-bits input when (see Table 5.2.18)
Table 5.2.17 Write data for RGB 6-6-6-bits input in 24-bit rgb Interface

nd rd th th th st
Memory Write
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x R15 R14 R13 R12 R11 R10 x G15 G14 G13 G12 G11 G10 x G15 G14 G13 G12 G11 G10 1st x R25 R24 R23 R22 R21 R20 x G25 G24 G23 G22 G21 G20 x B25 B24 B23 B22 B21 B20 2nd
write
3 write 4 write 5 write 6 write
pixel (R1/G1/B1)
pixel (R1/G1/B1)
18-bit
18-bit
DB[5]
DB[4]
DB[3]
DB[2]
DB[1]
DB[0]
DB[5]
DB[4]
24-bit
24-bit
Frame memory
R1 G1 B1
R2 G2 B2
R3 G3 B3
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Table 5.2.18


nd rd th th th st
Memory Write
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x R17 R16 R15 R14 R13 R12 R11 R10 x G17 G16 G15 G14 G13 G12 G11 G10 x G17 G16 G15 G14 G13 G12 G11 G10 1st x R27 R26 R25 R24 R23 R22 R21 R20 x G27 G26 G25 G24 G23 G22 G21 G20 x B27 B26 B25 B24 B23 B22 B21 B20 2nd
write
3 write 4 write 5 write 6 write
pixel (R1/G1/B1)
pixel (R1/G1/B1)
24-bit
24-bit
Frame memory
R1 G1 B1
R2 G2 B2
R3 G3 B3
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LDS285
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5.2.2.2
RGB Interface Mode Set
All 3-kinds of RGB interface mode can be available to fit the various controller type.(selected by 1st parameter of IFMODE command : IF1,IF0)
RGB I/F Mode RGB Mode1 RGB Mode2 RGB Mode3 DCK Used Used Used ENABLE Used Used Used Video Data Bus D23 to D1, VD0 Used Used Used VSYNC Not used Used Used VSYNCO Used Not used Not used HSYNC Not used Not used Used Reference clock for display Internal Oscillator Internal Oscillator DCK
NOTE: Unused RGB data bus must be connected to VSS1.
RGB Interface Mode1
Data write to the DDRAM is done by DCK and Video Data Bus (D23 to D1, VD0) when ENABLE is H state. To make the internal displaying clock, internal oscillator is used. So, to write the video data without flickering, controller needs to transfer the data with synchronous to the VSYNCO output signal.
RGB Interface Mode2
Data write to the DDRAM is done by DCK and Video Data Bus (D23 to D1, VD0) when ENABLE is H state. To make the internal displaying clock, internal oscillator is used. But frame display starts with synchronous to VSYNC input. So, to write the video data without flickers, the graphic controller must always transfer VSYNC signal to LDS285.
RGB Interface Mode3
Data write to the DDRAM is done by DCK and Video Data Bus (D23 to D1, VD0) when ENABLE is H state. To make the internal displaying clock, external clocks (DCK, VSYNC and HSYNC) are used. So, the graphic controller must always transfer DCK, VSYNC and HSYNC signal to LDS285.
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LDS285
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Video data write area
Still data write area
Video data write area
TE HSYNC (int) DCK ENABLE D17-D1,VD0 Serial interface

Data Dont Care Data Dont Care
Dont Care
Data
Dont Care
Address set command RGB transfer 1 mode
RAM write command Address set command MPU data transfer mode
Address set command RGB transfer 1 mode
Fig. 5.2.1
An example to overwrite still picture data during moving picture display (RGB Interface Mode1)
1 frame
Wait 319 320 FP FP FP BP BP BP 1 2 3
Line No. VSYNCI
BP BP BP
1 frame of an external signal
Start synchronization at the falling edge of the VSYNCI signal
Internal Clock Line No. VSYNCI
BP
BP
Fig. 5.2.2
An example of RGB Interface Mode2
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LDS285
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VSYNC HSYNC ENABLE

Back porch
Front porch
HSYNC DCK ENABLE VD17-VD0 Latched Data RAM WEN

Fig. 5.2.3 Video signal data writing method in RGB Interface Mode 3
Invalid RGB 0 RGB 1 RGB2 RGB N Invalid
RGB 0 RGB 1 RGB 2
RGB N
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LDS285
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5.2.3
Address Counter
The address counter sets the addresses of the display data RAM for writing and reading. Data is written pixel-wise into the DDRAM matrix of LDS285. The data for one pixel or two pixels is collected (RGB 8-8-8-bit), according to the data formats. As soon as this pixel-data information is complete the Write access is activated on the DDRAM. The locations of DDRAM are addressed by the address pointers. When MV = 0 ( MV is one of register value controlled by instruction MADCTL), the address ranges are X=0 to X=239 (0EFhex) and Y=0 to Y=319 (13Fh). When MV = 1, the address ranges are X=0 to X=319(13Fh) and Y=0 to Y=239 (0EFh). Addresses outside these ranges are not allowed. Before writing to the DDRAM, a window where data will be written must be defined. The window is programmable via the command registers XS, YS designating the start address and XE, YE designating the end address. For example the whole display contents will be written, the window is defined by the following values: XS=0 (0h) YS=0 (0h) and XE=239 (0EFh), YE=319 (13Fh). In vertical addressing mode (MV=1), the Y-address increments after each byte, after the last Y-address (Y=YE), Y wraps around to YS and X increments to address the next column. In horizontal addressing mode (MV=0), the X-address increments after each byte, after the last X-address (X=XE), X wraps around to XS and Y increments to address the next row. After the every last address (X=XE and Y=YE) the address pointers wrap around to address (X=XS and Y=YS). For flexibility in handling a wide variety of display architectures, the commands CASET, RASET and MADCTL (see section 6 INSTRUCTION DESCRIPTION), define flags MX and MY, which allows mirroring of the X-address and Y-address. All combinations of flags are allowed. Fig. 5.2.4 shows the available combinations of writing to the display RAM. When MX, MY and MV will be changed, the data must be rewritten to the display RAM. For each image condition, the controls for the column and row counters apply as below:
Condition When RAMWR/RAMRD command is accepted
Column Counter Return to Start Column (XS) Complete Pixel Read / Write action Increment by 1 The Column counter value is larger than End Column (XE) Return to Start Column (XS) The Column counter value is larger than End Column (XE) and Return to Start the Row counter value is larger than End Row (YE) Column (XS)
Row Counter Return to Start Row (YS) No change Increment by 1 Return to Start Row (YS) ( where MY= 0 )
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LDS285
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Fig. 5.2.4
Frame Data Write Direction According to the MADCTR parameters (MV, MX and MY)
Display Data Direction Normal
MADCTR Parameter MV MX MY 0 0 0
Image in the Host (MPU)

B
Image in the Driver (DDRAM)

H/W position (0,0) X-Y address (0,0) X: CASET, Y: RASET B
E H/W position (0,0) E
Y-Mirror
X-Y address (0,0) X: CASET, Y: RASET H/W position (0,0)
B B X-Y address (0,0) X: CASET, Y: RASET
X-Mirror
X-Mirror Y-Mirror
B H/W position (0,0) X-Y address (0,0) X: RASET, Y: CASET B
X-Y address (0,0) X: CASET, Y: RASET
X-Y Exchange
X-Y Exchange Y-Mirror
X-Y address (0,0) X: RASET, Y: CASET H/W position (0,0)
B B X-Y address (0,0) X: RASET, Y: CASET
X-Y Exchange X-Mirror
X-Y Exchange X-Mirror Y-Mirror
X-Y address (0,0) X: RASET, Y: CASET
NOTE: MV=D5 parameter of MADCTL command, MX=D6 parameter of MADCTL command, MY=D7 parameter of MADCTL command
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LDS285
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5.2.4
Memory Map
Pixel1 Pixel2 --Pixel239 Pixel240
Source Out
S1
RGB=0
S2
RGB=1
S3
S4
RGB=0
S5
RGB=1
S6
--RGB Order
S715 S716 S717 S718 S719 S720

RGB=0 RGB=1 RGB=0 RGB=1
RA MY=0 MY=1 0 319 R05-0 1 318 2 317 3 316 4 315 5 314 6 313 7 312 8 311 9 310 10 309 11 308 : : : : : : : : : : : : : : : : : : 312 7 313 6 314 5 315 4 316 3 317 2 318 1 319 0 MX=0 CA MX=1
SA ML=0 ML=1 0 319 1 318 2 317 3 316 4 315 5 314 6 313 7 312 8 311 9 310 10 309 11 308 : : : : : : : : : : : : 312 7 313 6 314 5 315 4 316 3 317 2 318 1 319 0
G05-0
B05-0
R15-0
G15-0
B15-0
---
R2385-0 G2385-0 B2385-0 R2395-0 G2395-0 B2395-0
: : : : : :
Display Pattern Data

: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
-----------------
-------------------------
: : : : : :
RN5-0
GN5-0
BN5-0
0 239
1 238
-----
238 1
239 0
NOTE: RA = Row Address, CA = Column Address, SA = Scan Address, MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTR command MY = Mirror Y-axis (Row address direction parameter), D7 parameter of MADCTR command ML = Scan direction parameter, D4 parameter of MADCTR command RGB= Red, Green and Blue pixel position change, D3 parameter of MADCTR command
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LDS285
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5.2.5
Normal Display On or Partial Mode On
In this mode, the content of the frame memory within an area where column pointer is 00h to 0EFh and page pointer is 00h to 13Fh is displayed. To display a dot on leftmost top corner, store the dot data at (column pointer, row pointer) = (0, 0). Example1) Normal Display On
S237 S238 S239
00h 01h 02h 03h 04h .. 000h 00 01 02 03 04 001h 10 11 12 13 14 002h 20 21 22 003h 30 31 32 004h 40 41 42 005h 50 51
..
.. EChEDhEEhEFh
0W 0X 0Y 0Z 1W 1X 1Y 1Z 2X 2Y 2Z 3X 3Y 3Z 4Y 4Z 5Y 5Z
1st 2nd 3
rd
G1 G2 G3 G4 G5 G6 : : G315 G316 G317 G318 G319 G320
00 01 02 03 04 10 11 12 13 14 20 21 22 30 31 32 40 41 42 50 51
4th 5th 6
th
S240
Scan Order
: : S1 S2 S3 S4 S5 :
320 lines
: : 13Ah U0 U1
240 x 320 x 24 bit Frame memory
: :
240 x 320 LCD panel
Displaying area = 320 lines
UY UZ 315th VX VY VZ 316th WXWYWZ 317th XX XY XZ 318th YW YX YY YZ 319th ZW ZX ZY ZZ 320th
U0 U1 V0 V1 V2 W0 W1 W2 X0 X1 X2 Y0 Y1 Y2 Y3 Y4 Z0 Z1 Z2 Z3 Z4
UY UZ VX VY VZ WX WY WZ XX XY XZ YW YX YY YZ ZW ZX ZY ZZ
13Bh V0 V1 V2 13Ch W0 W1 W2 13Dh X0 X1 X2 13Eh Y0 Y1 Y2 Y3 Y4 13Fh Z0 Z1 Z2 Z3 Z4
Example2) Partial Display On: PSL [15:0] = 004h, PEL [15:0] = 13Ch, MADCTR (ML)=0
S237
S238
S239
00h 01h 02h 03h 04h .. 000h 00 01 02 03 04 001h 10 11 12 13 14 002h 20 21 22 003h 30 31 32 004h 40 41 42 005h 50 51
..
.. EChEDhEEhEFh
1 2
st
G1 G2 G3 G4 G5 G6 : : G315 G316 G317 G318 G319 G320
00 01 02 03 04 10 11 12 13 14 20 21 22 30 31 32 40 41 42 50 51
S240
Scan Order
: : S1 S2 S3 S4 S5 :
nd
3rd 4
th
Nondisplaying area = 4 lines
5th 6th : :
320 lines
: : 13Ah U0 U1
240 x 320 x 24 bit Frame memory
240 x 320 LCD panel
UY UZ 315th VX VY VZ 316th WXWYWZ 317th XX XY XZ 318th YW YX YY YZ 319th ZW ZX ZY ZZ 320th
U0 U1 V0 V1 V2 W0 W1 W2 X0 X1 X2 Y0 Y1 Y2 Y3 Y4 Z0 Z1 Z2 Z3 Z4
UY UZ VX VY VZ WX WY WZ XX XY XZ YW YX YY YZ ZW ZX ZY ZZ
Displaying area = 313 lines
13Bh V0 V1 V2 13Ch W0 W1 W2 13Dh X0 X1 X2 13Eh Y0 Y1 Y2 Y3 Y4 13Fh Z0 Z1 Z2 Z3 Z4
Nondisplaying area = 3 lines
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LDS285
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5.2.6
Tearing Effect Output Line
The Tearing Effect output line supplies a Panel synchronization signal to the MPU. This signal can be enabled or disabled by the Tearing Effect Line Off & On commands. The mode of the Tearing Effect signal is defined by the parameter of the Tearing Effect Line On command. The signal can be used by the MPU to synchronize DDRAM Writing when displaying video images.
5.2.6.1 Tearing Effect Line Modes
Mode 1, the Tearing Effect Output signal consists of V-Blanking Information only:
t vd l
t vdh
Vertical T im e Scale
tvdh= The LCD display is not updated from the DDRAM tvdl = The LCD display is updated from the DDRAM (except Invisible Line see below)
Mode 2, the Tearing Effect Output signal consists of V-Blanking and H-Blanking Information, there are one V-sync and 320 H-sync pulses per field.
thdl
thdh
V -S ync
st nd th th
V-S ync
In visible Line
1 Line
Line
319
Line
320 Line
thdh= The LCD display is not updated from the Frame Memory thd l= The LCD display is updated from the Frame Memory (except Invisible Line see above)
Bottom Line
T op Line 2
nd
Line
T E (M ode2) T E (M ode1)
t vdh
Note: During Sleep In Mode, the Tearing Output Pin is active Low
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5.2.6.2
Tearing Effect Line Timing
The Tearing Effect signal is described below:
t vdl
t vdh
Vertical T im ing
H orizontal T im ing
t hdl t hdh
Table 5.2.19
AC characteristics of Tearing Effect Signal
Idle Mode Off (Frame Rate = 59Hz)

Symbol tvdl tvdh thdl thdh Parameter Vertical Timing Low Duration Vertical Timing High Duration Horizontal Timing Low Duration Horizontal Timing High Duration min TBD 1000 TBD TBD max 500 unit ms description
NOTE: The timings in Table 5.2.12 apply when MADCTL ML=0 and ML=1 The signals rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns.
tr
tf
0.8*V DD 1
0.8*V DD 1
0.2*V D D1
0.2*V D D1
The Tearing Effect Output Line is fed back to the MPU and should be used as shown below to avoid Tearing Effect:
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5.2.6.3 Example 1: MPU Write is faster than Panel Read.
M CU to M em ory
1
st
32 0
th
tim e
TE Output Signal
tim e
M em ory to LC D
1
st
32 0
th
tim e d
Im age on LCD
Data write to Frame Memory is now synchronized to the Panel Scan. It should be written during the vertical sync pulse of the Tearing Effect Output Line. This ensures that data is always written ahead of the panel scan and each Panel Frame refresh has a complete new image:
Data to be sent
B
a b c d
Im age on LCD
A A B B B
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5.2.6.4 Example 2: MPU Write is slower than Panel Read.
M CU to M em ory
1
st
320
th
tim e
TE Output Signal
tim e
M em ory to LC D
1
st
32 0
th
tim e
d e f
Im age on LCD
The MPU to Frame Memory write begins just after Panel Read has commenced i.e. after one horizontal sync pulse of the Tearing Effect Output Line. This allows time for the MPU to download the image behind the Panel Read pointer and to finish downloading during the subsequent Frame before the Read Pointer catches the MPU to Frame memory write position.
Data to be sent
B
a b c d e f
Im age on LCD
AA A A AB B
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5.3
INSTRUCTION DECODER & REGISTER
The instruction decoder identifies command words arriving at the interface and routes the following data type bytes to their destination. The command set can be found in 6 INSTRUCTION DESCRIPTION section.
5.4
SYSTEM CLOCK GENERATOR
The timing generator produces the various signals to drive the internal circuitry. Internal chip operation is not affected by operations on the data bus.
5.5
OSCILLATOR
LDS285 has on-chip oscillator which does not require external components. This oscillator output signal is used for system clock generation for internal display operation
5.6
SOURCE DRIVER
The source driver block includes 240x3 source outputs (S1 to S720), which should be connected directly to the TFT-LCD. The source output signals are generated in the data processing block after the data is read out of the RAM and latched, which represent the simultaneous selected rows. When less then 720 sources are required the unused source outputs should be left open-circuit.
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5.7
GATE DRIVER
The gate driver block includes 320 gate outputs (G1 to G320) which should be connected directly to the TFT-LCD.
S1~720
10
11
12
13
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11 VGH G12 VGL
G13
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5.8
5.8.1
RGB INTERFACE TIMING DIAGRAM

Relationship between Input Signal and Output Signal (RGB I/F Mode 3)
HSYNC
10 1 2 3 4 5 6 7 8 9
DCK MCK (Internal)
1 H ( period is selectable by setting register value ) HSYNC
MCK No (Internal).
17
18
19
20
21
22
23
24
25
26
S1~S720
Gn
Gn+1
Gate output ON time Gate output OFF time
Gate output disable time
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5.8.2
Input / Output Timing Chart (G0->G320, S1->S720)
Horizontal valid data start time=10DCK, Vertical valid data start time=3HSYNC, 1 Line scan, Line inversion.
VSYNC BACK PORCH (can be selected by register setting: VBP[5:0]) VSYNC

322 323 324 325 326 1 2 3 4 5 6 7 8 322 323 324 325 326 1 2 3 4 5 6 7
HSYNC
0 (Dummy) 1 2 3 4 5 6 7 8
DATA G0 G1 G319 G320 VCOM
HSYNC BACK PORCH (can be selected by ENABLE pad input)

259 260 1 2 3 4 5 6 7 8 9 10 11 249 250 251 252 253 254 255 256 257 258 259 260 1 2 3 4 5 6 7 8 9 10 11 12 249 250 251 252 253 254 255 256 257 258 259 260 1 2 3 4 5 6 7 8 9 10 11 12 238 239 240 250 251 252 253 254 255 256 257 258 259 260 1 240 Invalid Data
DCK
HSYNC
238 239 240 1 2 3 1 2 3 1 2 3 2
DATA
1st Line DATA
2nd Line DATA
ENABLE
Gate output disable time G0 (Dummy) G1
S1~S720
HSYNC
152 249
10
11
DCK DATA
Invalid Data
12
239
Data for S1 to S3
Data for S4 to S6
Data for S718 to S720
315 316 317 318 319 320
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5.9
5.9.1
LCD POWER GENERATION CIRCUIT

LCD Power Generation Scheme
1. The boost voltage generated in LDS285 is shown as below. (Case=VS<4.2V)
VGH=16V(x4VR)
AVDD=5.6V(x2VDD2) VR=4.0V VDD2=2.8V VSS2=0V VCOML=-2.0 ~ 1.0V VCL=-2.8V(x-1VDD2) VS=4.0V VCOMH=2.5 ~ 5.5V
VGL=-12V(x-3VR)
Fig. 5.9.1
LCD power generation scheme1
2. The boost voltage generated in LDS285 is shown as below. (Case=VS>4.2V)
VGH=16V(x4VR)
AVDD=6.0V(x3VREG_DC) VR=4.0V
VDD2=2.8V
VS=4.0V
VCOMH=2.5 ~ 5.5V
VREG_DC=2V VSS2=0V VCOML=-2.0 ~ 1.0V VCL=-2.8V(x-1VDD2)
VGL=-12V(x-3VR)
Fig. 5.9.2
LCD power generation scheme2(wide viewing angle)
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5.9.2
Various Boosting Steps
The boost steps of each boosting voltage are selected according to how the external capacitors are connected. Different booster applications are shown as below.
AVD D = 2VD D2 (D ual mode) C 1P C 1M C 2P C 2M AVD D
AVD D = 2VD D2 (Single mode) C 1P C 1M C 2P C 2M A VDD
AVD D = 3VR E G _DC (X3 mode) C 1P C 1M VR EG _DC C 2P C 2M VD C1 AVD D
VCL = -1VD D2 C 6P C 6M VCL
VG H = 4V R V G L = -3VR
VG H = 3V R V G L = -3VR
C3P C 3M C 4P C 4M C 5P C 5M
VGH
C 3P C 3M
VG H
VGL
C 4P C 4M C 5P C 5M
VGL
VG H = 4VR VG L = -2V R
VG H = 3V R VG L = -2VR
C 3P C 3M C 4P C 4M C 5P C 5M
VG H
C 3P C 3M
VG H
VGL
C 4P C 4M C 5P C 5M
VGL
Fig. 5.9.3
Various boosting Step
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5.9.3
Gray Voltage Generator
LDS285 supports 4 gamma curves. They can be selected by GAMSET command(26h).
5.9.3.1
Gamma Correction Curve Circuit
RSTRING1_DEC COM G4<1:0>
BUF_GAMMA
RSTRING 2 GM V
G4<1:0> G4<1:0>
V<1:3> VR1000 0 Rx0,Ry0 GS0<2:0> R999 R998 R997 GM32 R996 R<b0:b63> GS2<2:0> DEC_64to1 dec002 GM3 2 GM80 DEC_64to1 dec003 GM8 0 R<d0:d63> GS4<2:0> DEC_64to1 DEC_2to1<93:0> V80 V<81:174> DEC_2to1<46:0> V32 V<33:79> R<a0:a63> GS1<2:0> DEC_64to1 DEC_16to1 dec000 GM0 GM 4 dec001 GM4 0 V 4 DEC_8to1<26:0> V<5:31> DEC_8to1<2:0>
R<c0:c63> GS3<2:0>
dec004
GM17 5
GM175
V175 V<176:222 DEC_2to1<46:0 > >
R<e0:e63> GS5<2:0> R4 R3 R2 R1 R<f0:f63> GS6<2:0> Rx1,Ry1 GS7<2:0> VR0 DEC_16to1 DEC_64to1 DEC_64to1
dec005
GM22 3
GM223
V223 V<224:250> DEC_8to1<26:0>
dec006
GM25 1 GM251 V25 V<252:254> 1 GM25 5 5 GM255 V25 DEC_8to1<2:0 >
dec007
Fig. 5.9.4
Gamma Correction Curve cirsuit
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5.9.3.2
Data (Hex)
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47
Relationship between DDRAM Data and Output Voltages. (TBD)

Output Voltage when VS= V VCOM = Low
Gamma V0+ V1+ V2+ V3+ V4+ V5+ V6+ V7+ V8+ V9+ V10+ V11+ V12+ V13+ V14+ V15+ V16+ V17+ V18+ V19+ V20+ V21+ V22+ V23+ V24+ V25+ V26+ V27+ V28+ V29+ V30+ V31+ V32+ V33+ V34+ V35+ V36+ V37+ V38+ V39+ V40+ V41+ V42+ V43+ V44+ V45+ V46+ V47+ V48+ V49+ V50+ V51+ V52+ V53+ V54+ V55+ V56+ V57+ V58+ V59+ V60+ V61+ V62+ V63+ V64+ V65+ V66+ V67+ V68+ V69+ V70+ V71+ 1.0 1.8 2.2 2.5 Gamma V0V1V2V3V4V5V6V7V8V9V10V11V12V13V14V15V16V17V18V19V20V21V22V23V24V25V26V27V28V29V30V31V32V33V34V35V36V37V38V39V40V41V42V43V44V45V46V47V48V49V50V51V52V53V54V55V56V57V58V59V60V61V62V63V64V65V66V67V68V69V70V711.0
VCOM = High
1.8 2.2 2.5
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48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95
V72+ V73+ V74+ V75+ V76+ V77+ V78+ V79+ V80+ V81+ V82+ V83+ V84+ V85+ V86+ V87+ V88+ V89+ V90+ V91+ V92+ V93+ V94+ V95+ V96+ V97+ V98+ V100+ V101+ V102+ V103+ V104+ V105+ V106+ V107+ V108+ V109+ V110+ V111+ V112+ V113+ V114+ V115+ V116+ V117+ V118+ V119+ V120+ V121+ V122+ V123+ V124+ V125+ V126+ V127+ V127+ V128+ V129+ V130+ V131+ V132+ V133+ V134+ V135+ V136+ V137+ V138+ V139+ V140+ V141+ V142+ V143+ V144+ V145+ V146+ V147+ V148+ V149+
V72V73V74V75V76V77V78V79V80V81V82V83V84V85V86V87V88V89V90V91V92V93V94V95V96V97V98V100V101V102V103V104V105V106V107V108V109V110V111V112V113V114V115V116V117V118V119V120V121V122V123V124V125V126V127V127V128V129V130V131V132V133V134V135V136V137V138V139V140V141V142V143V144V145V146V147V148V149-
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96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3
V150+ V151+ V152+ V153+ V154+ V155+ V156+ V157+ V158+ V159+ V160+ V161+ V162+ V163+ V164+ V165+ V166+ V167+ V168+ V169+ V170+ V171+ V172+ V173+ V174+ V175+ V176+ V177+ V178+ V179+ V180+ V181+ V182+ V183+ V184+ V185+ V186+ V187+ V188+ V189+ V190+ V191+ V192+ V193+ V194+ V195+ V196+ V197+ V198+ V199+ V200+ V201+ V202+ V203+ V204+ V205+ V206+ V207+ V208+ V209+ V210+ V211+ V212+ V213+ V214+ V215+ V216+ V217+ V218+ V219+ V220+ V221+ V222+ V223+ V224+ V225+ V226+ V227+
2.097 2.056 2.015 1.975 1.934 1.893 1.853 1.817 1.782 1.746 1.711 1.676 1.640 1.605 1.575 1.545 1.515 1.485 1.455 1.425 1.395 1.363 1.330 1.298 1.265 1.233 1.200 1.166 1.131 1.097 1.062 1.028 0.985 0.943 0.900 0.851 0.803 0.750 0.683 0.608 0.518 0.368 3.540 3.398 3.383 3.353 3.293 3.203 3.128 3.053 2.963 2.873 2.783 2.717 2.651 2.585 2.519 2.453 2.400 2.348 2.295 2.243 2.190 2.138 2.097 2.056 2.015 1.975 1.934 1.893 1.853 1.817 1.782 1.746 1.711 1.676 1.640 1.605
V150V151V152V153V154V155V156V157V158V159V160V161V162V163V164V165V166V167V168V169V170V171V172V173V174V175V176V177V178V179V180V181V182V183V184V185V186V187V188V189V190V191V192V193V194V195V196V197V198V199V200V201V202V203V204V205V206V207V208V209V210V211V212V213V214V215V216V217V218V219V220V221V222V223V224V225V226V227-
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E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF
V228+ V229+ V230+ V231+ V232+ V233+ V234+ V235+ V236+ V237+ V238+ V239+ V240+ V241+ V242+ V243+ V244+ V245+ V246+ V247+ V248+ V249+ V250+ V251+ V252+ V253+ V254+ V255+
V228V229V230V231V232V233V234V235V236V237V238V239V240V241V242V243V244V245V246V247V248V249V250V251V252V253V254V255-
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Gamma Curve
1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 12 24 36 48 60 72 84 96 108 120 135 147 159 171 183 195 207 219 231 243 255
GC0
GC2 GC1
GC3
Gamma1.0 Gamma1.8 Gamma2.2 Gamma2.5
Fig. 5.9.5
Gamma Curve according to the GC0 to GC3 bit (TBD)
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VS V0+(V255-)
V255+(V0-) VSS 00h 40h 80h C0h FFh
Fig. 5.9.6
Relationship between DDRAM data and output level
Source output
VC O M
Positive
N egative
Fig. 5.9.7
Relationship between source output and VCOM
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5.9.4
Temperature Compensation
The LDS285 has a built-in temperature compensation circuits. By the temperature compensation circuits, user can obtain a higher quality in the various temperature ranges.
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5.10 POWER ON/OFF SEQUENCE

VDD1 and VDD2 can be applied in any order. VDD2 and VDD1 can be powered down in any order. During power off, if LCD is in the Sleep Out mode, VDD2 and VDD1 must be powered down minimum 120msec after RESB has been released. During power off, if LCD is in the Sleep In mode, VDD1 or VDD2 can be powered down minimum 0msec after RESB has been released. !SCE can be applied at any timing or can be permanently grounded. RESB has priority over !SCE. There will be no damage to the display module if the power sequences are not met. There will be no abnormal visible effects on the display panel during the Power On/Off Sequences. There will be no abnormal visible effects on the display between ending the Power On Sequence and receiving Sleep Out command and between receiving Sleep In command and starting the Power Off Sequence. If RESB line is not held stable by host during Power On Sequence as defined in Sections 5.10.21, and 5.10.2, then it will be necessary to apply a Hardware Reset (RESB) after Host Power On Sequence is complete to ensure correct operation. Otherwise function is not guaranteed. The power on/off sequence is illustrated below:
5.10.1 Case 1 RESB line is held High or Unstable by Host at Power On

If RESB line is held High or unstable by the host during Power On, then a Hardware Reset must be applied after both VDD2 and VDD1 have been applied otherwise correct functionality is not guaranteed. There is no timing restriction upon this hardware reset.
TrPW = +/- no limit
tfPW
+/- no limit
VDD1 VDD2
Time when the latter signal rises up to 90% of its Typical Value. e.g. When VDD2 comes later, This time is defined at the cross point of 90% of 2.5V/2.75V, not 90% of 2.3V. Time when the former signal falls down to 90% of its Typical Value. e.g. When VDD2 falls earlier, This time is defined at the cross point of 90% of 2.5V/2.75V, not 90% of 2.3V.
tfPW!CS = +/- no limit trPW!CS = +/- no limit
!CS
H or L
trPW!RES = + no limit
!RES
(Power down in Sleep Out mode)
30%
tfPW!RES1 = min.120ms trPW!RES = + no limit
!RES
(Power down in Sleep In mode)
30%
tfPW!RES2 = min.0ns
tfPW !RES1 is applied to !RES falling in the Sleep Out Mode. tfPW !RES2 is applied to !RES falling in the Sleep In Mode.
Note: Unless otherwise specified, timings herein show cross point at 50% of signal/power level.
Fig. 5.10.1 RESB line is held high or unstable by Host at Power on
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5.10.2 Case 2 RESB line is held Low by host at Power On

If RESB line is held Low (and stable) by the host during Power On, then the RESB must be held low for minimum 10sec after both VDD2 and VDD1 have been applied.
TrPW = +/- no limit
tfPW = +/- no limit
VDD1 VDD2
Time when the latter signal rises up to 90% of its Typical Value. e.g. When VDD2 comes later, This time is defined at the cross point of 90% of 2.5V/2.75V, not 90% of 2.3V. Time when the former signal falls down to 90% of its Typical Value. e.g. When VDD2 falls earlier, This time is defined at the cross point of 90% of 2.5V/2.75V, not 90% of 2.3V.
tfPW!CS = +/- no limit trPW!CS = +/- no limit
!CS
H or L
trPW!RES = min.10s
!RES
(Power down in Sleep Out mode)
tfPW!RES1 = min.120ms trPW!RES = min.10s
!RES
(Power down in Sleep In mode)
tfPW!RES2 = min.0ns
tfPW!RES1 is applied to !RES falling in the Sleep Out Mode. tfPW!RES2 is applied to !RES falling in the Sleep In Mode.
Note: Unless otherwise specified, timings herein show cross point at 50% of signal/power level.
Fig. 5.10.2 RESB line is held low by Host at Power on
5.11 UNCONTROLLED POWER OFF

The uncontrolled power off means a situation when e.g. there is removed a battery without the controlled power off sequence. There will not be any damages for the display module or the display module will not cause any damages for the host or lines of the interface. At an uncontrolled power off the display will go blank and there will not be any visible effects within 1 second on the display (blank display) and remains blank until Power On Sequence powers it up.
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5.12 POWER FLOW CHART FOR DIFFERENT POWER MODES

Normal display mode on = NORON Partial mode on = PTLON Idle mode off = IDMOFF
Idle mode on = IDMON Sleep out = SLPOUT Sleep in = SLPIN
Power on sequence
HW reset SW reset
NORON PTLON Sleep out Normal display mode on Idle mode off
SLPIN SLPOUT Sleep in Normal display mode on Idle mode off
NORON PTLON
IDMON
IDMOFF
IDMON
IDMOFF
SLPIN Sleep out Normal display mode on Idle mode on SLPOUT Sleep in Normal display mode on Idle mode on
SLPIN Sleep out Partial mode on Idle mode off SLPOUT Sleep in Partial mode on Idle mode off
IDMON
IDMOFF
IDMON
IDMOFF
PTLON NORON
Sleep out Partial mode on Idle mode on
SLPIN SLPOUT
Sleep in Partial mode on Idle mode on
PTLON NORON
Sleep out
Sleep in
Note 1: There is not any abnormal visual effect when there is changing from one power mode to another power mode. 2: There is not any limitation, which is not specified by this spec, when there is changing from one power mode to another power mode
Fig. 5.12.1 Power flow char for different Power Modest
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5.13 INPUT / OUTPUT PIN STATE

5.13.1 Output or Bi-directional (I/O) Pins
Output or After Power On After Hardware Reset After Software Reset Bi-directional pins TE Low Low Low D23 to D0 (Output driver) High-Z (Inactive) High-Z (Inactive) High-Z (Inactive) TEST1, TEST4 X X X Note: There will be no output from D23-D0 during Power On/Off sequence, Hardware Reset and Software Reset.
5.13.2 Input Pins

Input pins RESB CSB DC WRB RDB D23 to D0 VSYNC, HSYNC , DCK, ENABLE, VD0 SRGB, SINV, SMX,SMY, P68, BS2, BS1,BS0, TGS,EXTC,FRM,PSEL, OSC,TEST2, TEST3 During Power On Process See Section 5.10 Input invalid Input invalid Input invalid Input invalid Input invalid Input invalid After Power On Input valid Input valid Input valid Input valid Input valid Input valid Input valid After Hardware After Software During Power Reset Reset Off Process Input valid Input valid Input valid Input valid Input valid Input valid Input valid Input valid Input valid Input valid Input valid Input valid Input valid Input valid See Section 5.10 Input invalid Input invalid Input invalid Input invalid Input invalid Input invalid
Input invalid
Input valid
Input valid
Input valid
Input invalid
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5.14 SLEEP OUT COMMAND AND SELF-DIAGNOSTIC FUNCTIONS OF THE DISPLAY MODULE
5.14.1 Register loading Detection
Sleep Out-command (See section 6.1.13 Sleep Out (11h)) is a trigger for an internal function of the display module, which indicates, if the display module loading function of factory default values from EEPROM (or similar device) to registers of the display controller is working properly. There are compared factory values of the EEPROM and register values of the display controller by the display controller. If those both values (EEPROM and register values) are same, there is inverted (=increased by 1) a bit, which is defined in command 6.1.11 Read Display Self-Diagnostic Result (0Fh) (=RDDSDR) (The used bit of this command is D7). If those both values are not same, this bit (D7) is not inverted (= increased by 1). The flow chart for this internal function is following:
Power on sequence HW reset SW reset
Sleep In (10h)
Sleep Out Mode
Sleep In Mode
RDDSDRs D7=0
Sleep Out (11h)
Loads and compares EEPROM and register values
No
Are EEPROM and register values same?
Yes D7 inverted
Note: There is not compared and loaded register values, which can be changed by user (00h to AFh and DAh to DDh), by the display module.
Fig. 5.14.1 Regist er loading Detection Flow chart
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5.14.2 Functionality Detection

Sleep Out-command (See section 6.1.13 Sleep Out (11h)) is a trigger for an internal function of the display module, which indicates, if the display module is still running and meets functionality requirements. The internal function (= the display controller) is comparing, if the display module is still meeting functionality requirements (e.g. booster voltage levels, timings, etc.). If functionality requirement is met, there is inverted (= increased by 1) a bit, which defined in command 6.1.11 Read Display Self- Diagnostic Result (0Fh) (= RDDSDR) (The used bit of this command is D6). If functionality requirement is not same, this bit (D6) is not inverted (= increased by 1). The flow chart for this internal function is following:
Sleep In (10h)
Sleep Out Mode
Sleep In Mode
RDDSDRs D6=0
Sleep Out (11h)
Checks timings, voltage levels and other functionalities
No
Is functionality requirement met ?
Yes D6 inverted
Note: It is needed 120msec after Sleep Out -command, when there is changing from Sleep In mode to Sleep Out -mode, before it is possible to check if functionality requirements are met and a value of RDDSDRs D6 is valid. Otherwise, there is 5msec delay for D6s value, when Sleep Out command is sent in Sleep Out -mode.
Fig. 5.14.2 Functionality Detection Flow chart
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5.14.3 Chip Attachment Detection (optional)

Sleep Out-command (See section 6.1.13 Sleep Out (11h)) is a trigger for an internal function of the display module, which indicates, if a chip or chips (e.g. driver, etc.) of the display module is/are attached to the circuit route of a flex foil or display glass ITO. There is inverted (= increased by 1) a bit, which is defined in command 6.1.11 Read Display Self- Diagnostic Result (0Fh) (= RDDSDR) (The used bit of this command is D5), if the chip or chips is/are attached to the circuit route of the flex or display glass. If this chip is or those chips are not attached to the circuit route of the flex or display glass, this bit (D5) is not inverted (= increased by 1). The following figure is for reference purposes; how this chip attachment can be implemented e.g. there are connected together 2 bumps via route of ITO or the flex foil on 4 corners of the driver (chip).
Bump
Routing between bumps
Through view of driver to bumps
Routing between bumps
Substrate or flex foil
The flow chart for this internal function is following:

Sleep In (10h)
Sleep Out Mode
Sleep In Mode
RDDSDRs D5=0
Sleep Out (11h)
Checks, if chip is attached to route
No
Is chip attached to routes?

Yes D5 inverted
Fig. 5.14.3 Chip attachment Detection Flow chart
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5.14.4 Display Glass Break Detection (optional)

Sleep Out-command (See section 6.1.12 Sleep Out (11h)) is a trigger for an internal function of the display module, which indicates, if the display glass of the display module is broken or not. There is inverted (= increased by 1) a bit, which is defined in command 6.1.11 Read Display Self-Diagnostic Result (0Fh) (= RDDSDR) (The used bit of this command is D4), if the display glass is not broken. If this display glass is broken, this bit (D4) is not inverted (= increased by 1). The following figure is a reference, how this glass break detection can be implemented e.g. there is connected together 2 bumps via route of ITO. This route of ITO is the nearest route of the edge of the display glass.
Active area of the display glass

Bump
Through view of driver to bumps
Substrate of display glass
The flow chart for this internal function is following:

Sleep In (10h)
Sleep Out Mode
Sleep In Mode
RDDSDRs D4=0
Sleep Out (11h)
Checks, if display glass is broken
Yes
Is the display glass broken?

No D4 inverted
Fig. 5.14.4 Display Glass Break Detection Flow chart
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6
6.1
ADAPTIVE BCAKLIGHT CONTROL AND LED DRIVER CONTROL

LABC ( LIGHT ADAPTIVE BACKLIGHT CONTROL)
System Block Diagam with ALS (Ambient Light Sensor) and LDS285
6.1.1
Ambient Light
Ambient Light Sensor
The general block diagram of the ambient light and brightness control is illustrated in Fig 6.1.1. The information of the ambient light is sent to LDS285 and the Brightness Control in LDS285 deals with them if the user enables it. The user can read ambient light information from LDS285 and control the brightness of LEDs in TFT Panel by writing the command to LDS285 manually. (See section 7.1.32 Write Display Brightness (51h)).
LEADIS Technology
from Outside
LEDs
MPU
Brightness Conroller
MeSSI or LoSSI
LDI Driver TFT Panel LDS285
Fig. 6.1.1
System Block Diagram with ALS
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6.1.2
6.1.2.1
LABC Function Flow

LABC contol from sleep out to sleep in
Previous status before the sequence - Sleep in Mode - BCTRL = 0, BL = 0 in Write CTRL Display(53h) Command Sequence Command : Sleep out ( 11h) - Not working Brightness control - Display backlight off Command : Write Display Brightness (51h) Parameter : DBV[7:0] : 216 (DBh: 85 % brightness ) - Not working Brightness control - Display backlight off Command : Write CTRL Display (53h) Parameter : BCTRL = 1 : Brightness Control Block on BL = 1 : Backlight Control on
- Display waits for V-sync - Display starts brightness control from 0 % to 85 % after V-sync Command : Write Display Brightness (51h) Parameter : DBV[7:0] : 255 (DBh: 100 % brightness ) - Display waits for V-sync - Display starts brightness control from 85 % to 100 % after V-sync Command : Write CTRL Display (53h) Parameter : BCTRL = 0 : Brightness Control Block off BL = 0 : Backlight Control off
- Display waits for V-sync - Display backlight off Command : Sleep in ( 10h)
Following Fig 6.1.2 shows the brightness changes in the case of the above example..
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0%
100%
85 %
100 %
100%
0%
Display brightness
85%
50%
0%
1.Sleep out 3.Write CTRL Display 5.Write CTRL Display 6. Sleep in 2. Write Display brightness : 85% 4. Write Display brightness : 100%
Command Sequence
Fig. 6.1.2
LABC ( Light Adaptive Brightness control ) example
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6.2
CABC ( CONTENT ADAPTIVE BACKLIGHT CONTROL)
A Content Adaptive Brightness Control function can be used to reduce the power consumption of the luminance source. Content adaptation means that content grey level scale can be increased while simultaneously lowering brightness of the backlight to achieve the same perceived brightness. The adjusted grey level scale and thus the power consumption reduction depend on the content of the image. The function and its different modes can be controlled. See 7.1.36 Write Content Adaptive Brightness Control (55h) for more information. Definition modes : Off mode : Content Adaptive Brightness Control functionality is totally off. UI(User Interface) image mode : Optimized for UI image. It is kept image quality as much as possible. Target power consumption reduction ratio: 10% or less SI(Still picture mode) : Optimized for still picture. Some image quality degradation would be acceptable. Target power consumption reduction ratio: more than 30 % MI(Moving image mode) : Optimized for moving image. It is focused on the biggest power reduction with image quality degradation. Target power consumption reduction ratio : more than 30 %
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6.2.1
CABC Function Flow
Content Adaptive Brightness Control operates like below. Display brightness is changed, according to the image contents. The following graph in Fig 6.2.1 mentions the case of displaying three different images. - Image A : -20 % brightness reduction - Image B : -30 % brightness reduction - Image C : -10 % brightness reduction
Image A
Brightness reduction ratio : -20 %
Image B
Image C
6.3
CABC and LABC can be ON simultaneously. Then the final Display Brightness is calculated with the following formula. Display brightness = Brighness based on LABC * Brightness based on CABC
Table 6.3.1 Display Brightness ration when LABC and CABC are all ON
Display brightness
100% 80% 70% 50%
90%
0%
Fig. 6.2.1
CABC (Content Adaptive Brightness control) example )
CABC AND LABC
LABC Brightness ratio Case1 Case2 Case3 85% 60% 85%
CABC Brightness ratio 80% 70% 90%
Display Brightness ratio 68% 42% 76.5%
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6.4
LED DRIVER CONTROL
LDS285 can change the brightness of LEDs in panel by controlling LED drivers if LABC or CABC is enabled (Refer to Section 6.1 LABC and 6.2 CABC). LDS285 can support the two interfaces for two types of LED drivers, LED driver with pwm pulse contorl and LED driver with 1-wire digital interface (only for LDS8661), through the output LED_CNT.
6.4.1
LED Driver control with PWM pulse
LDS285 can calculate the backlight brightness level and send it to LED driver which is controlled by PWM pulse through the output LED_CNT. Fig 6.4.1 is the basic timing diagram which is used in LDS285 to contol LED driver.
Dislay_ON tperiod LED_CNT ton toff

When LABC=1 or CABC =1
LED_CNT
When LABC=0 and CABC =0
Fig. 6.4.1
PWM pulse timing on LED_CNT output
The period tperiod of PWM pulse can be changed by the 3rd parameter PER[3:0] of the command LEDCTRL(EFh). (see the section 7.1.55 LEDCTRL) The LED-on time ton and the LED-off time toff are decided by the backlight brightness level which is calculated with LABC or/and CABC in LDS285. If LABC is off and CABC is off, then LED_CNT is the same to Display-On signal. Fig 6.4.2 shows the change of PWM pulse according to PER[3:0].
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PER[3:0] 0 1 2 3 4 5 6 7 8 else
tperiod 1024us 1280ns 1536ns 1792ns 2048ns 3076ns 4096ns 8192ns 512ns 256ns tperiod
LED_CNT
VDD2 VSS2
Where High level is VDD2 and Low level is VSS2
Fig. 6.4.2
PWM pulse timing according to PER[3:0]
Fig 6.4.3 shows the two examples of PWM pulse with LABC, CABC and PER[3:0]
Case1 : LABC brightness ratio = 80%, CABC = Off and PER[3:0] = 0

1024ns
LED_CNT
819ns ( 1024 * 0.8 ) 205ns ( 1024 * 0.2 )
Case2 : LABC brightness ratio = 90%, CABC brightness ration = 80 % and PER[3:0] = 4
2048ns
LED_CNT
1474ns ( 2048 * 0.9 * 0.8 ) 574ns ( 2048 * 0.28 )
Fig. 6.4.3
PWM pulse examples with LABC, CABC and PER[3:0]
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6.4.2
LED Driver control with 1-wire digital interface( only for LDS8861 )
LDS285 can support only the LED driver LDS8861 with 1-wire digital interface. Here we specify the interface between LDS285 and LDS8861 briefly. The LED_CNT output in LDS285 should be connected to EN/SET pin in LDS8816.
C1VIN
C1+
C2-
C2+
LDS285
2.5V to 5.5V
VIN
LDS8861 (LED Driver)

LEDA1 LEDA2 LEDB1 LEDB2 LEDC1 LEDC2
LED_CNT
One wire programming
EN/SET
Fig. 6.4.4
Interconnection between LDS285 and LDS8861
LDS285 control LDS8861 through the one wire programming. The EN/SET logic input in LDS8861 operates as a chip enable and singla wire addressable interface for control and current setting of all LEDs. LDS285 can write data to LDS8861 by programming the 2nd parameter of the command LEDCTRL(EFh). (see the section 7.1.55 LEDCTRL). The 2nd parameter of the command LEDCTRL(EFh) consists of ADDR[2:0] and DB[3:0]. The user can change the status of LDS8861 by changing the 2nd parameter of the command LEDCTRL(EFh). Fig.6.4.5 shows the timing specification of EN/SET in LDS8861 and LDS285 drives the LED_CNT output meeting the timing specification of EN/SET in LDS8861. If you need more detailed specification, please refer to the Specification of LDS8861 ( 6-Channel Fractional Charge Pump LED Driver in 3x3 TQFN).
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symbol TSETUP TLO THI TOFF TDATADELAY TRESETDELAY
Name EN/SET setup from shutdown EN/SET program low time EN/SET program high time EN/SET low time to shutdown EN/SET Delay to DATA EN/SET Delay High to ADDRESS
Conditions
Min 10 0.2 0.2 1.5 500 2
Typ
Max
Units us
100 100
us us ms
1000
us ms
TSETUP Shutdown TLO
THIGH
TDATADELA
TRESETDELAY
TOFF Shutdown
EN/SET
ADDRESS
Fig. 6.4.5
WAIT
DATA
EN/SET timing specification in LDS8861
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7
7.1
INSTRUCTION DESCRIPTION
INSTRUCTION CODE
Instruction Code Table
Instruction Code
7.1.1
Table 7.1.1
Instruction
NOP SWRESET
Refer
7.1.2 7.1.3
DC WRB RDB D17-8

0 0 0 1 1 1 1 0 1 1 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -
D7
0 0 0 ID17 1 ID37 0 ST31 ST23 ST15 ST7 0 D7 0 D7 0 D7 0 D7 0 D7 0 D7 0 0 0 0 0 0 0 GC7 0 0 0 XS15 XS7 XE15 XE7
D6
0 0 0 ID16 ID26 ID36 0 ST30 ST22 ST14 ST6 0 D6 0 D6 0 D6 0 D6 0 D6 0 D6 0 0 0 0 0 0 0 GC6 0 0 0 XS14 XS6 XE14 XE6
D5
D4
D3
D2
D1
D0 (Hex)
0 1 0 ID10 ID20 ID30 1 ST24 ST16 ST8 ST0 0 D0 1 D0 0 D0 1 D0 0 D0 1 D0 0 1 0 1 0 1 0 GC0 0 1 0 XS8 XS0 XE8 XE0 (00h) (01h) (04h) (09h) (0Ah) (0Bh) (0Ch) (0Dh) (0Eh) (0Fh) (10h) (11h) (12h) (13h) (20h) (21h) (26h) (28h) (29h) (2Ah) -
-: Dont care Function

No Operation Software reset Read Display ID Dummy read ID1 read ID2 read ID3 read Read Display Status Dummy read Read Display Power Mode Dummy read Read Display MADCTR Dummy read Read Display Pixel Format Dummy read Read Display Image Mode Dummy read Read Display Signal Mode Dummy read Read Display Self-diagnostic result Dummy read Sleep in & booster off Sleep out & booster on Partial mode on Partial off (Normal) Display inversion off (normal) Display inversion on Gamma curve select Display off Display on Column address set X address start: 0 XS EFh :MV=0 X address start: 0 XS 13Fh :MV=1 X address end: XS XE EFh :MV=0 X address end: XS XE 13Fh :MV=1
RDDID
7.1.4
RDDST
7.1.5
RDDPM
7.1.6
RDDMADCTR
7.1.7
RDDCOLMOD
7.1.8
RDDIM
7.1.9
RDDSM
7.1.10
RDDSDR SLPIN SLPOUT PTLON NORON INVOFF INVON GAMSET DISPOFF DISPON
7.1.11 7.1.12 7.1.13 7.1.14 7.1.15 7.1.16 7.1.17 7.1.18 7.1.19 7.1.20
CASET
7.1.21
0 0 0 0 1 0 ID12 ID11 ID22 ID21 ID32 ID31 0 0 ST26 ST25 ST18 ST17 ST10 ST9 ST2 ST1 0 1 D2 D1 0 1 D2 D1 1 0 D2 D1 1 0 D2 D1 1 1 D2 D1 1 1 D2 D1 0 0 0 0 0 1 0 1 0 0 0 0 1 1 GC2 GC1 0 0 0 0 0 1 XS10 XS9 XS2 XS1 XE10 XE9 XE2 XE1
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Table 7.1.2
Instruction Code (Continued)
-:Dont care
Instruction
RASET
Refer DC WRB RDB D17-8 D7

7.1.22 0 1 1 1 1 0 1 0 1 1 0 1 1 1 1 0 0 1 0 1 0 0 0 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D17-8 D17-8 -
D6
D5
D4
D3
D2
D1
D0 (Hex) Function
Row address set Y address start: 0 YS 13Fh :MV=0 Y address start: 0 YS EFh :MV=1 Y address end: YS YE 13Fh :MV=0 Y address end: YS YE EFh :MV=1 Memory write Write data Memory read Dummy read Read data Partial start/end address set Partial start address (0,1,2 , ,319) Partial end address (0,1,2 , , 319) Tearing effect line off Tearing effect mode set & on M=0: Mode1, M=1: Mode2 Memory data access control Idle mode off Idle mode on Interface pixel format Interface format Write Display Brightness Write Data Read Display Brightness value Dummy Read Read parameter Write Control Display Write Data Read Control Display Dummy Read Read parameter Wrtie Content Adaptive Brightness Write Data Read Content Adaptive Brightness Dummy Read Read parameter Read ID1 Dummy read Read parameter Read ID2 Dummy read Read parameter Read ID3 Dummy read Read parameter
RAMWR RAMRD
7.1.23 7.1.24
PTLAR
7.1.25
TEOFF TEON MADCTR IDMOFF IDMON COLMOD
7.1.26 7.1.27 7.1.28 7.1.29 7.1.30 7.1.31 7.1.32 7.1.33
WRDISBV RDDISBV
WRCTRLD RDCTRLD
7.1.34 7.1.35
WRCABC RDCABC
7.1.36 7.1.37
RDID1
7.1.38
RDID2
7.1.39
RDID3
7.1.40
0 0 1 0 YS15 YS14 YS13 YS12 YS7 YS6 YS5 YS4 YE15 YE14 YE13 YE12 YE7 YE6 YE5 YE4 0 0 1 0 D7 D6 D5 D4 0 0 1 0 D7 D6 D5 D4 0 0 1 1 PSL15 PSL14 PSL13 PSL12 PSL7 PSL6 PSL5 PSL4 PEL15 PEL14 PEL13 PEL12 PEL7 PEL6 PEL5 PEL4 0 0 1 1 0 0 1 1 0 0 1 1 MY MX MV ML 0 0 1 1 0 0 1 1 0 0 1 1 RP2 RP1 RP0 0 1 0 1 DBV7 DBV6 DBV5 DBV4 0 1 0 1 DBV7 DBV6 DBV5 DBV4 0 1 0 1 - BCTRL 0 1 0 1 - BCTRL 0 1 0 1 0 1 0 1 1 1 0 1 ID17 ID16 ID15 ID14 1 1 0 1 1 ID26 ID25 ID24 1 1 0 1 ID37 ID36 ID35 ID34
1 0 1 1 (2Bh) YS11 YS10 YS9 YS8 YS3 YS2 YS1 YS0 YE11 YE10 YE9 YE8 YE3 YE2 YE1 YE0 1 1 0 0 (2Ch) D3 D2 D1 D0 1 1 1 0 (2Eh) D3 D2 D1 D0 0 0 0 0 (30h) PSL11 PSL10 PSL9 PSL8 PSL3 PSL2 PSL1 PSL0 PEL11 PEL10 PEL9 PEL8 PEL3 PEL2 PEL1 PEL0 0 1 0 0 (34h) 0 1 0 1 (35h) M 0 1 1 0 (36h) RGB 1 0 0 0 (38h) 1 0 0 1 (39h) 1 0 1 0 (3Ah) P2 P1 P0 0 0 0 1 (51h) DBV3 DBV2 DBV1 DBV0 0 0 1 0 (52h) DBV3 DBV2 DBV1 DBV0 0 0 1 1 (53h) BL 0 1 0 0 (54h) BL 0 1 0 1 (55h) C1 C0 0 1 1 0 (56h) C1 C0 1 0 1 0 (DAh) ID13 ID12 ID11 ID10 1 0 1 1 (DBh) ID23 ID22 ID21 ID20 1 1 0 0 (DCh) ID33 ID32 ID31 ID30
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Table 7.1.3
Instruction Code (Extended code set)
Instruction Refer DC WRB RDB D17-8 D7

IFMODE 7.1.41 0 1 1 0 1 1 1 1 1 1 0 1 1 REGCTR VCOMCTR 7.1.44 7.1.45 0 1 0 1 1 GAMCTR1 7.1.46 0 1 1 1 1 GAMCTR2 7.1.47 0 1 1 1 1 GAMCTR3 7.1.48 0 1 1 1 1 GAMCTR4 7.1.49 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -
D6
D5
D4
D3
0
D2
0
D1
0 IF1 HSP 0 HA 1 BPA1 FPA1 HB 1 BPB1 FPB1 1
D0
-: Dont Care (Hex) Function
DISCLK
7.1.42
1 0 1 1 DW 1 0 1 1 HA7 HA 6 HA 5 HA 4 BPA5 BPA4 FPA5 FPA4 HB7 HB 6 HB 5 HB 4 BPB5 BPB4 FPB5 FPB4 1 0 0
1 1 -
DP 0 HA 3 BPA3 FPA3 HB 3 BPB3 FPB3 0 0 0
EP 0 HA 2 BPA2 FPA2 HB 2 BPB2 FPB2 0
INVCTR
7.1.43
0 0 0
1 VR2 1 1
1 0 0
0 VR1 0
1 0 0
0 VR0 0
(B0h) Set display interface mode 0 IF0 Data transfer mode set VSP RGB I/F data width & Clock polarity set (B1h) Display clock set 1 Number of clocks during 1H (full-color) HA 0 Number of vertical back porches (full-color) BPA0 FPA0 Number of vertical front porches (full-color) Number of clocks during 1H (8-color) HB 0 Number of vertical back porches (8-color) BPB0 FPB0 Number of vertical front porches (8-color) (B2h) Display inversion control 0 Line inversion (full color) Line inversion (8-color) VR/VS regulator output voltage control -2.5V ~ +0.5V (50mV step) +2.5V ~ +5.5V (50mV step) Gamma adjustment . Gamma adjustment . Gamma adjustment . Gamma adjustment . Gamma adjustment . Gamma adjustment . Gamma adjustment . Gamma adjustment . Gamma adjustment . Gamma adjustment . Gamma adjustment . Gamma adjustment . Gamma adjustment . Gamma adjustment . Gamma adjustment . Gamma adjustment .
NLA2 NLA1 NLA0 NLB2 NLB1 NLB0

0 VS2 0 0 VS1 0 0 VS0 1
(C0h) Regulator control (C1h) VCOML/VCOMH voltage control
VCLC5 VCLC4 VCLC3 VCLC2 VCLC1 VCLC0 VCHC5 VCHC4 VCHC3 VCHC2 VCHC1 VCHC0 0 0
1 1 1 1 -
(C8h) Set gamma correction characteristics
GS102 GS101 GS100 GS112 GS111 GS110 GS122 GS121 GS120 GS132 GS131 GS130 GS142 GS141 GS140 GS152 GS151 GS150 GS162 GS161 GS160 GS172 GS171 GS170
0 0
(C9h) Set gamma correction characteristics
0 0
(CAh) Set gamma correction characteristics
0 0
(CBh) Set gamma correction characteristics
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Table 7.1.4
Instruction Code (Extended code set, continued)
-: Dont Care
D17 Instructi Refer DC WRB RDB D7 on -8
EPPGMDB 7.1.50 0 1 1 1 0 0 0 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -
D6
1 1 1 1 0 1 1
D5
0 ID24 0 0 0 0 0 -
D4
1 ID23 1 1 1 0 1 -
D3
0 ID22 0 0 0 1 -
D2
0
D1
0
D0
0
(Hex) Function
(D0h) Write ID2,VCOM Offset for EEPROM program VCOM middle voltage trimming in 8color VCOM middle voltage trimming Just ID2 [6:0] are stored in EEPROM (D1h) EEPROM erase (D2h) EEPROM program (D3h) EEPROM read, verify register set macro read , program verify,Erase verify (D9h) VCOM offset bits read Dummy Read Read Parameter Read Parameter (EFh) Write LED control value LED driver type Control value for LDS8861 Contorl value for PWM output
VCOF82 VCOF81 VCOF80 ID21 0 0 0 0 ID20 0 1 1 ERVF 0 db_sel 1 0 1 0 1 -
VCOF5 VCOF4 VCOF3 VCOF2 VCOF1 VCOF0
ID26 ID25
EPERASE EPPROG EPRDVRF RDVCOF
7.1.51 7.1.52 7.1.53 7.1.54
1 1 1 0 1 1 0 0
READ PGMVF
RVCOF5 RVCOF4 RVCOF3 RVCOF2 RVCOF1 RVCOF0 RVCOF82 RVCOF81 RVCOF80
LEDCTRL
7.1.55
0 ADR0 PER1
1 DB3 PER0
1 DB2 STEP2
1 DB1 STEP1
1 TYPE DB0 STEP0
ADR2 ADR1 PER3 PER2
NOTE: 1) After the H/W reset by RESB pin or S/W reset by SWRESET command, each internal register becomes default state (Refer RESET TABLE section) 2) Before command D1(EPER) , supply 22V to the ME_CMP for EEPROM Erase . 3) Before command D2(EPPGM), supply 8.5V to the ME_CMP for EEPROM Program . 4) To use extended code set, the TGS pad should be connected to VSS. Extended code set is just used for module test. If TGS pad is not connected to VSS, all the extended code set will be ignored and regarded as NOP (00h) command. 5) Undefined commands are treated as NOP (00 h) command. 6) Commands 10h, 12h, 13h, 20h, 21h, 26h, 28h, 29h, 30h, 33h, 36h (ML parameter only), 37h, 38h and 39h are updated during V-sync when Module is in Sleep Out Mode to avoid abnormal visual effects. During Sleep In mode, these commands are updated immediately. Read status (09h), Read Display Power Mode (0AH), Read
Display MADCTL (0BH), Read Display Pixel Format (0CH), Read Display Image Mode (0DH), Read Display Signal Mode (0EH) and Read Display Self Diagnostic Result (0FH) of these commands of these commands is updated
immediately both in Sleep In mode and Sleep Out mode.
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7.1.2
NOP (00h)
Parameter No Parameter NOTE: - Dont care Inst / Para NOP DC 0 WRB RDB D17-8 1 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 (Code) (00h)
This command is empty command. It does not have effect on the display module. Description However it can be used to terminate DDRAM data write or read as described in RAMWR (Memory Write), RAMRD (Memory Read) and parameter write commands. Restriction Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value N/A N/A N/A
Register Availability
Default
Flow Chart
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7.1.3
SWRESET: Software Reset (01h)

D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 1 (Code) (01h)
Inst / Para DC WRB RDB D17-8 0 1 SWRESET Parameter No Parameter NOTE: - Dont care
When the Software Reset command is written, it causes a software reset. It resets the commands and parameters to their S/W Reset default values and all source & gate outputs are Description set to VSS (display off). (See default tables in each command description) Note: The DDRAM contents are not affected by this command.
It will be necessary to wait 5msec before sending new command following software reset. The display module loads all display suppliers factory default values to the registers during 5msec.
Restriction
If Software Reset is applied during Sleep Out mode, it will be necessary to wait 120msec before sending Sleep Out command. Software Reset command cannot be sent during Sleep Out sequence.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value N/A N/A N/A
Default
SWRESET
Display whole blank screen Flow Chart

Set Commands to S/W Default Value
Red and Blue

Parameter Display Action Mode Sequential transfer
Sleep In Mode
LEADIS Technology
CONFIDENTIAL
93
LDS285
Version 2.00
7.1.4
RDDID: Read Display ID (04h)

DC 0 WRB 1 1 1 1 RDB D17-8 D7 1 0 ID17 ID27 ID37 D6 0 ID16 ID26 ID36 D5 0 ID15 ID25 ID35 D4 0 ID14 ID24 ID34 D3 0 ID13 ID23 ID33 D2 1 ID12 ID22 ID32 D1 0 ID11 ID21 ID31 D0 0 ID10 ID20 ID30 (Code) (04h) -
Inst / Para RDDID
Dummy Read 1 2nd parameter 1 3rd parameter 1 4th parameter 1 NOTE: - Dont care
This read byte returns 24-bit display identification information. The 1st parameter is dummy data The 2nd parameter (ID17 to ID10): LCD modules manufacturer ID. Description The 3rd parameter (ID27 to ID20): LCD module/driver version ID The 4th parameter (ID37 to UD30): LCD module/driver ID. NOTE: Commands RDID1/2/3(DAh, DBh, DCh) read data correspond to the parameters 2,3,4 of the command 04h, respectively. Restriction
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Availability Yes Yes Yes Yes Yes Default Value ID2 Not Fixed Not Fixed Not Fixed
Default
Power On Sequence S/W Reset H/W Reset
ID1 Not Fixed Not Fixed Not Fixed
ID3 Not Fixed Not Fixed Not Fixed
Serial I/F Mode

RDDID (04h)
Parallel I/F Mode

RDDID (04h)
Host Driver
Legend
Command
Dummy Clock
Dummy Read
Parameter Display
Flow Chart
Send ID1[7:0]
Send ID1[7:0] Action
Send ID2[7:0]
Send ID2[7:0]
Mode Sequential transfer
Send ID3[7:0]
Send ID3[7:0]
LEADIS Technology
CONFIDENTIAL
94
LDS285
Version 2.00
7.1.5
RDDST: Read Display Status (09h)

DC 0 WRB 1 1 1 1 1 RDB D17-8 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 0 1 0 0 1 ST31 ST30 ST29 ST28 ST27 ST26 ST25 ST24 ST23 ST22 ST21 ST20 ST19 ST18 ST17 ST16 ST15 ST14 ST13 ST12 ST11 ST10 ST9 ST8 ST7 ST6 ST5 ST4 ST3 ST2 ST1 ST0 (Code) (09h) -
Inst / Para RDDST
Dummy Read 1 2nd parameter 1 3rd parameter 1 4th parameter 1 th 5 parameter 1 NOTE: - Dont care
Bit ST31 ST30 ST29 ST28 ST27 ST26 ST25 ST24 ST23 ST22 ST21 ST20 ST19 ST18 ST17 ST16 ST15 ST14 ST13 ST12 ST11 ST10 ST9 ST8 ST7 ST6 ST5 ST4 ST3 ST2 ST1 ST0
This command indicates the current status of the display as described in the table below:
Description Booster Voltage Status Row Address Order (MY) Column Address Order (MX) Row/Column Exchange (MV) Scan Address Order (ML) RGB/BGR Order (RGB) Not Used Not Used Not Used Interface Colour Pixel Format Definition Idle Mode On/Off Partial Mode On/Off Sleep In/Out Display Normal Mode On/Off Vertical Scrolling Status Not Used Inversion Status All Pixels On (Not Used) All Pixels Off (Not Used) Display On/Off Tearing effect line on/off Gamma Curve Selection Value 1=Booster on, 0=off 1=Decrement, 0=Increment 1=Decrement, 0=Increment 1= Row/column exchange (MV=1) 0= Normal (MV=0) 1=Decrement, 0=Increment 1=BGR, 0=RGB 0 0 0 110 = 18-bit / pixel (666 mode) 111 = 24-bit / pixel (888 mode) 1 = On, 0 = Off 1 = On, 0 = Off 1 = Out, 0 = In 1 = Normal Display, 0 = Partial Display 1 = Scroll on, 0 = Scroll off 0 1 = On, 0 = Off 0 0 1 = On, 0 = Off 1 = On, 0 = Off 000 = GC0, 001 = GC1, 010 = GC2, 011 = GC3 100~111:Not used 0 = mode1, 1 = mode2 0 0 0 0 0
Description
Tearing effect line mode Not Used Not Used Not Used Not Used Not Used
LEADIS Technology
CONFIDENTIAL
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LDS285
Version 2.00
Restriction
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value (ST31 to ST0): 0000 0000_0111 0001_0000 0000_0000 0000 0xxx xx00_0xxx 0001_0000 0000_0000 0000 0000 0000_0111 0001_0000 0000_0000 0000
Default
Serial I/F Mode

RDDST (09h)
Parallel I/F Mode

RDDST (09h)
Host Driver
Legend
Command Parameter Display
Dummy Clock
Dummy Read
Send ST[31:24]
Send ST[31:24]
Action Mode
Flow Chart
Send ST[23:16] Send ST[23:16] Sequential transfer
Send ST[15:8]
Send ST[15:8]
Send ST[7:0]
Send ST[7:0]
LEADIS Technology
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96
LDS285
Version 2.00
7.1.6
RDDPM: Read Display Power Mode (0Ah)

DC 0 WRB 1 1 RDB D17-8 1 D7 0 D7 D6 0 D6 D5 0 D5 D4 0 D4 D3 1 D3 D2 0 D2 D1 1 D1 D0 0 D0 (Code) (0Ah) -
Inst / Para RDDPM
Dummy Read 1 2nd parameter 1 NOTE: - Dont care

Bit D7 D6 D5 D4 D3 D2 D1 D0
Description Booster Voltage Status Idle Mode On/Off Partial Mode On/Off Sleep In/Out Display Normal Mode On/Off Display On/Off Not Used Not Used Value 1=Booster on, 1 = Idle Mode On, 1 = Partial Mode On, 1 = Sleep Out, 1 = Normal Display, 1 = Display On, 0 0 0=Booster off 0 = Idle Mode Off 0 = Partial Mode Off 0 = Sleep In 0 = Partial Display 0 = Display Off
Description
Restriction
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value (D7 to D0) 0000_1000 (08h) 0000_1000 (08h) 0000_1000 (08h)
Default
Serial I/F Mode

RDDPM (0Ah)
Parallel I/F Mode

RDDPM (0Ah)
Legend
Command
Host Driver
Parameter Display
Flow Chart
Send D [7:0]
Dummy Read Action Mode Send D [7:0] Sequential transfer
LEADIS Technology
CONFIDENTIAL
97
LDS285
Version 2.00
7.1.7
RDDMADCTR: Read Display MADCTR (0Bh)

DC 0 WRB 1 1 RDB D17-8 1 D7 0 D7 D6 0 D6 D5 0 D5 D4 0 D4 D3 1 D3 D2 0 D2 D1 1 D1 D0 1 D0 (Code) (0Bh) -
Inst / Para RDDMADCTR

Bit D7 D6 D5
Description Row Address Order Column Address Order Row/Column Order (MV) Scan Address Order RGB/BGR Order Not Used Not Used Not Used Value 1=Decrement, 0=Increment 1=Decrement, 0=Increment 1= Row/column exchange (MV=1) 0= Normal (MV=0) 1=Decrement, 0=Increment 1=BGR, 0=RGB 0 0 0
Description
D4 D3 D2 D1 D0
Restriction
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value (D7 to D0) 0000_0000 (00h) No change 0000_0000 (00h)
Default
Serial I/F Mode

RDDMADCTR (0Bh)
Parallel I/F Mode

RDDMADCTR (0Bh)
Legend
Command
Host Driver
Parameter Display
Flow Chart
Send D [7:0]
LEADIS Technology
CONFIDENTIAL
98
LDS285
Version 2.00
7.1.8
RDDCOLMOD: Read Display Pixel Format (0Ch)

DC 0 WRB 1 1 RDB D17-8 1 D7 0 D7 D6 0 D6 D5 0 D5 D4 0 D4 D3 1 D3 D2 1 D2 D1 0 D1 D0 0 D0 (Code) (0Ch) -
Inst / Para RDDCOLMOD

Description RGB Interface Color Format Value 0 (Not Used) 0 (Not Used) 0 (Not Used) 0 (Not Used) 0 111=24 bit/pixel 011=12 bit/pixel 101=16 bit/pixel 110=18 bit/pixel
Description
Control Interface Color Format
Restriction
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Availability Yes Yes Yes Yes Yes
Default Value 0000_0111 (24 bit/pixel) No Change 0000_0111 (24 bit/pixel)
Default
Serial I/F Mode

RDDCOLMOD (0Ch)
Parallel I/F Mode

RDDCOLMOD (0Ch)
Legend
Command
Host Driver
Parameter Display
Flow Chart
Send D [7:0]
LEADIS Technology
CONFIDENTIAL
99
LDS285
Version 2.00
7.1.9
RDDIM: Read Display Image Mode (0Dh)

DC 0 WRB 1 1 RDB D17-8 1 D7 0 D7 D6 0 D6 D5 0 D5 D4 0 D4 D3 1 D3 D2 1 D2 D1 0 D1 D0 1 D0 (Code) (0Dh) -
Inst / Para RDDIM

Description Vertical Scrolling On/Off Horizontal Scrolling On/Off Inversion On/Off All Pixels On All Pixels Off Gamma Curve Selection Value 0 (Not used) 0 (Not used) 1 = Inversion is On, 0 = Inversion is Off 0 (Not used) 0 (Not used) 000 = GC0, 001 = GC1 010 = GC2, 011 = GC3 100 to 111 = Not defined
Description
Restriction
Default
Serial I/F Mode

RDDIM (0Dh)
Parallel I/F Mode

RDDIM (0Dh)
Legend
Command
Host Driver
Parameter Display
Flow Chart
Send D [7:0]
LEADIS Technology
CONFIDENTIAL
100
LDS285
Version 2.00
7.1.10 RDDSM: Read Display Signal Mode (0Eh)

Inst / Para RDDSM DC 0 WRB 1 1 RDB D17-8 1 D7 0 D7 D6 0 D6 D5 0 D5 D4 0 D4 D3 1 D3 D2 1 D2 D1 1 D1 D0 0 D0 (Code) (0Eh) -

Description Tearing Effect Line On/Off Tearing effect line mode Horizontal Sync. (RGB I/F) On/Off Vertical Sync. (RGB I/F) On/Off Pixel Clock (DCK, RGB I/F) On/Off Data Enable (ENABLE, RGB I/F) On/Off Not Used Not Used Value 1 = On, 0 = Off 0 = mode1, 1 = mode2 0 0 0 0 0 0
Description
Restriction
Default
Serial I/F Mode

RDDSM (0Eh)
Parallel I/F Mode

RDDSM (0Eh)
Legend
Command
Host Driver
Parameter Display
Flow Chart
Send D [7:0]
LEADIS Technology
CONFIDENTIAL
101
LDS285
Version 2.00
7.1.11 RDDSDR: Read Display Self-Diagnostic Result (0Fh)

Inst / Para RDDSDR DC 0 WRB 1 1 RDB D17-8 1 D7 0 D7 D6 0 D6 D5 0 D5 D4 0 D4 D3 1 D3 D2 1 D2 D1 1 D1 D0 1 D0 (Code) (0Fh) -

Description Register Loading Detection Functionality Detection Chip Attachment Detection Display Glass Break Detection Not Used Not Used Not Used Not Used Value refer section 5.14
Description
0 0 0 0
Restriction
Default
Serial I/F Mode

RDDSDR (0Fh)
Parallel I/F Mode

RDDSDR (0Fh)
Legend
Command
Host Driver
Parameter Display
Flow Chart
Send D [7:0]
LEADIS Technology
CONFIDENTIAL
102
LDS285
Version 2.00
7.1.12 SLPIN: Sleep In (10h)

Inst / Para DC WRB RDB D17-8 1 SLPIN 0 Parameter No Parameter NOTE: - Dont care D7 0 D6 0 D5 0 D4 1 D3 0 D2 0 D1 0 D0 0 (Code) (10h)
This command causes the LCD module to enter the minimum power consumption mode. In this mode the DC/DC converter is stopped, Internal display oscillator is stopped, and panel scanning is stopped.
Source/Gate Output
Blank display
STOP STOP
Description
Memory scan operation
Internal Oscillator
STOP Discharge
DC/DC Converter
MPU interface and memory are still working and the memory keeps its contents This command has no effect when module is already in sleep in mode. Sleep In Mode can only be exit by the Sleep Out Command (11h). Restriction It will be necessary to wait 5msec before sending next command, this is to allow time for the supply voltages and clock circuits to stabilize. It will be necessary to wait 120msec after sending Sleep Out command (when in Sleep In Mode) before Sleep In command can be sent.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value Sleep in mode Sleep in mode Sleep in mode
Default
LEADIS Technology
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103
LDS285
Version 2.00
It takes about 120 msec to get into Sleep In mode (booster off state) after SLPIN command issued. The results of booster off can be check by RDDST (09h) command Bit31.
SPLIN Stop DC/DC Converter
Legend
Command Parameter
Display whole blank
Flow Chart
screen (Automatic No effect to DISP ON/OFF Command)
Stop Internal Oscillator
Display Action Mode
Drain charge from LCD panel
Sleep In Mode Sequential transfer
LEADIS Technology
CONFIDENTIAL
104
LDS285
Version 2.00
7.1.13 SLPOUT: Sleep Out (11h)

Inst / Para DC WRB RDB D17-8 1 SLPOUT 0 Parameter No Parameter NOTE: - Dont care D7 0 D6 0 D5 0 D4 1 D3 0 D2 0 D1 0 D0 1 (Code) (11h)
This command turns off sleep mode. In this mode the DC/DC converter is enabled, Internal display oscillator is started, and panel scanning is started.
Source/Gate Output
STOP
Blank
Memory Contents
(If DISPON 29h is set)
Description
Memory scan operation
START
Internal Oscillator
STOP 0V
DC/DC Converter
Restriction
This command has no effect when module is already in sleep out mode. Sleep Out Mode can only be exit by the Sleep In Command (10h). It will be necessary to wait 5msec before sending next command, this is to allow time for the supply voltages and clock circuits to be stabilized. LDS285 loads all default values of extended and test command to the registers during this 5msec and there cannot be any abnormal visual effect on the display image if those default and register values are same when this load is done and then the LDS285 is already Sleep Out mode. LDS285 is doing self-diagnostic functions during this 5msec. See also section 5.14. It will be necessary to wait 120msec after sending Sleep In command (when in Sleep Out mode) before Sleep Out command can be sent
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value Sleep in mode Sleep in mode Sleep in mode
Default
LEADIS Technology
CONFIDENTIAL
105
LDS285
Version 2.00
It takes 120msec to become Sleep Out mode (booster on mode) after SLPOUT command issued. The results of booster on can be checked by RDDST (09h) command Bit31.
SLPOUT
Legend
Start Internal Oscillator Command Display whole blank screen (Automatic No effect to DISP ON/OFF Commands) Parameter Display Action Mode Charge Offset voltage for LCD Panel Display Memory contents in accordance with the current command table settings Sequential transfer
Flow Chart
Start DC-DC Converter
Sleep Out Mode
LEADIS Technology
CONFIDENTIAL
106
LDS285
Version 2.00
7.1.14 PTLON: Partial Display Mode On (12h)

Inst / Para DC WRB RDB D17-8 1 PTLON 0 Parameter No Parameter NOTE: - Dont care D7 0 D6 0 D5 0 D4 1 D3 0 D2 0 D1 1 D0 0 (Code) (12h)
Description Restriction
This command turns on Partial mode. The partial mode window is described by the Partial Area command (30H) To leave Partial mode, the Normal Display Mode On command (13H) should be written. There is no abnormal visual effect during mode change between Normal mode On <-> Partial mode On. This command has no effect when Partial mode is active.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value Normal Mode On Normal Mode On Normal Mode On
Default
Flow Chart
See Partial Area (30h)
LEADIS Technology
CONFIDENTIAL
107
LDS285
Version 2.00
7.1.15 NORON: Normal Display Mode On (13h)

Inst / Para DC WRB RDB D17-8 1 NORON 0 Parameter No Parameter NOTE: - Dont care Description Restriction D7 0 D6 0 D5 0 D4 1 D3 0 D2 0 D1 1 D0 1 (Code) (13h)
This command returns the display to normal mode. Normal display mode on means Partial mode off. There is no abnormal visual effect during mode change from Normal mode On <-> Partial mode On. This command has no effect when Normal Display mode is active.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value Normal Mode On Normal Mode On Normal Mode On
Default
Flow Chart
See Partial Area and Vertical Scrolling Definition Descriptions for details of when to use this command
LEADIS Technology
CONFIDENTIAL
108
LDS285
Version 2.00
7.1.16 INVOFF: Display Inversion Off (20h)

Inst / Para DC WRB RDB D17-8 D7 D6 D5 D4 1 0 0 1 0 INVOFF 0 Parameter No Parameter NOTE: - Dont care This command is used to recover from display inversion mode. This command makes no change of contents of frame memory. Description This command does not change any other status. Restriction D3 0 D2 0 D1 0 D0 0 (Code) (20h)
This command has no effect when module is already inversion off mode.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value Display Inversion off Display Inversion off Display Inversion off
Default
Legend Display Inversion On Mode

Flow Chart
INVOFF
Action Mode
Display Inversion OFF Mode
Sequential transfer
LEADIS Technology
CONFIDENTIAL
109
LDS285
Version 2.00
7.1.17 INVON: Display Inversion On (21h)

Inst / Para DC WRB RDB D17-8 1 INVON 0 Parameter No Parameter NOTE: - Dont care D7 0 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 1 (Code) (21h)
Description
This command is used to enter into display inversion mode This command makes no change of contents of frame memory. Every bit is inverted form the frame memory to the display. This command does not change any other status. This command has no effect when module is already Inversion On mode.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value Display Inversion off Display Inversion off Display Inversion off
Restriction
Default
Display Inversion OFF Mode
Legend
Flow Chart
INVON
Action Mode
Display Inversion ON Mode
Sequential transfer
LEADIS Technology
CONFIDENTIAL
110
LDS285
Version 2.00
7.1.18 GAMSET: Gamma Set (26h)

Inst / Para INVON DC 0 WRB RDB D17-8 D7 1 0 1 GC7 D6 0 D5 1 D4 0 D3 0 D2 1 D1 0 D0 1 (Code) (26h) -
Parameter 1 NOTE: - Dont care
GC6
GC5
GC4
GC3
GC2
GC1
GC0
This command is used to select the desired Gamma curve for the current display. A maximum of 4 curves can be selected. The curves are defined in Fig 5.9.3 The curve is selected by setting the appropriate bit in the parameter as described in the Table. Description
GC [7:0] 01h 02h 04h 08h Parameter GC0 GC1 GC2 GC3 Curve Selected Gamma Curve 1 Gamma Curve 2 Gamma Curve 3 Gamma Curve 4
Note: All other values are undefined. Restriction Values of GC [7:0] not shown in table above are invalid and will not change the current selected Gamma curve until valid is received.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value 01h 01h 01h
Default
Legend GAMSET
Command Parameter GC [7:0] Display Action New Gamma Curve Loaded Mode Sequential transfer
Flow Chart
LEADIS Technology
CONFIDENTIAL
111
LDS285
Version 2.00
7.1.19 DISPOFF: Display Off (28h)

Inst / Para DC WRB RDB D17-8 1 DISPOFF 0 Parameter No Parameter NOTE: - Dont care D7 0 D6 0 D5 1 D4 0 D3 1 D2 0 D1 0 D0 0 (Code) (28h)
Description
This command is used to enter into DISPLAY OFF mode. In this mode, the output from DDRAM is disabled and blank page is inserted for two frames. This command makes no change of contents of DDRAM. This command does not change any other status. There will be no abnormal visible effect on the display. Exit from this command by Display On (29h) (Example) Memory Display
Restriction
This command has no effect when module is already in Display Off mode.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value Display off Display off Display off
Default
Display On Mode DISPOFF

Flow Chart
Display whole blank screen for 2 frames (Automatic No effect to DISP ON/OFF
Legend
Command Parameter Display Action Mode Sequential transfer
Display Off Mode
LEADIS Technology
CONFIDENTIAL
112
LDS285
Version 2.00
7.1.20 DISPON: Display On (29h)

Inst / Para DC WRB RDB D17-8 1 DISPON 0 Parameter No Parameter NOTE: - Dont care D7 0 D6 0 D5 1 D4 0 D3 1 D2 0 D1 0 D0 1 (Code) (29h)
This command is used to recover from DISPLAY OFF mode. Output from the DDRAM is enabled. This command makes no change of contents of DDRAM. This command does not change any other status. (Example) Memory Description Display
Restriction
This command has no effect when module is already in Display On mode.

Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value Display off Display off Display off
Default
Display Off Mode
Legend Command Parameter
Flow Chart
DISPON
Display Action
Display On Mode
LEADIS Technology
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113
LDS285
Version 2.00
7.1.21 CASET: Column Address Set (2Ah)

Inst / Para CASET 1 Parameter
st
DC 0 1
WRB
RDB D17-8 1 1 1 1 1
D7 0
D6 0
D5 1
D4 0
D3 1
D2 0
D1 1
D0 0
(Code) (2Ah) -
XS15 XS14 XS13 XS12 XS11 XS10 XS9 XS7 XS6 XS5 XS4 XS3 XS2 XS1 XE15 XE14 XE13 XE12 XE11 XE10 XE9 XE7 XE6 XE5 XE4 XE3 XE2 XE1
XS8 XS0 XE8 XE0
2nd Parameter 1 rd 3 Parameter 1 th 4 Parameter 1 NOTE: - Dont care
This command is used to define area of DDRAM where MPU can access. This command makes no change on the other driver status. The value of XS [15:0] and XE [15:0] are referred when RAMWR command comes. Each value represents one column line in the DDRAM. (Example)
XS [15:0]
Description
XE [15:0]
Restriction
XS [15:0] always must be equal to or less than XE [15:0] When XS [15:0] or XE [15:0] is greater than maximum address like below, data of out of range will be ignored. (Parameter range: 0 XS [15:0] XE [15:0] 239 (00EFh)): MV=0 (Parameter range: 0 XS [15:0] XE [15:0] 319 (013Fh)): MV=1 (about MV register, refer section 6.1.30 ( Row / Column exchange ) )
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value XE [15:0] XE [15:0] (MV=0) (MV=1) 00EFh(239d) 00EFh(239d) 013Fh(319d) 00EFh(239d)
Status
XS [15:0] 0000h 0000h 0000h
Default
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LDS285
Version 2.00
CASET
1 & 2
rd
st
nd
parameter XS [15:0]
3 & 4 parameter XE [15:0]
th
RASET
Display Action
1 & 2 parameter YS [15:0] rd th 3 & 4 parameter YE [15:0]
st
nd
IF Needed
RAMWR
Flow Chart
Image Data D1[15:0],D2[15:0] ..Dn[15:0]
Any Command
LEADIS Technology
CONFIDENTIAL
115
LDS285
Version 2.00
7.1.22 RASET: Row Address Set (2Bh)

Inst / Para RASET 1 Parameter
st
DC 0 1
WRB
RDB D17-8 1 1 1 1 1
D7 0
D6 0
D5 1
D4 0
D3 1
D2 0
D1 1
D0 1
(Code) (2Bh) -
YS15 YS14 YS13 YS12 YS11 YS10 YS9 YS7 YS6 YS5 YS4 YS3 YS2 YS1 YE15 YE14 YE13 YE12 YE11 YE10 YE9 YE7 YE6 YE5 YE4 YE3 YE2 YE1
YS8 YS0 YE8 YE0
2nd Parameter 1 rd 3 Parameter 1 th 4 Parameter 1 NOTE: - Dont care
This command is used to define area of DDRAM where MPU can access. This command makes no change on the other driver status. The value of YS [15:0] and YE [15:0] are referred when RAMWR command comes. Each value represents one column line in the DDRAM. (Example) Description
YS [15:0]
YE [15:0]
YS [15:0] always must be equal to or less than YE [15:0] When YS [15:0] or YE [15:0] are greater than maximum row address like below, data of out of range will be ignored. (Parameter range: 0 YS [15:0] YE [15:0] 319 (013Fh)): MV=0 (Parameter range: 0 YS [15:0] YE [15:0] 239 (00EFh)): MV=1 (about MV register, refer section 6.1.30 ( Row / Column exchange ) )
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value YE [15:0] YE [15:0] (MV=0) (MV=1) 013Fh(319d) 013Fh(319d) 00EFh (239d) 013Fh(319d)
Restriction
Status
YS [15:0] 0000h 0000h 0000h
Default
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116
LDS285
Version 2.00
CASET
IF Needed
1 & 2 parameter XS [15:0] rd th 3 & 4 parameter XE [15:0]
st
nd
RASET
Display Action
1 & 2
rd
st
nd
parameter YS [15:0]
3 & 4 parameter YE [15:0]
th
RAMWR
Flow Chart IF Needed

Image Data D1[15:0],D2[15:0] ..Dn[15:0]
Any Command
LEADIS Technology
CONFIDENTIAL
117
LDS285
Version 2.00
7.1.23 RAMWR: Memory Write (2Ch)

Inst / Para RAMWR DC 0 WRB : RDB D15-8 1 D15-8 1 : : D15-8 1 D7 0 D7 : D7 D6 0 D6 : D6 D5 1 D5 : D5 D4 0 D4 : D4 D3 1 D3 : D3 D2 1 D2 : D2 D1 0 D1 : D1 D0 0 D0 : D0 (Code) (2Ch) : -
Data write 1 : : Data write 1 NOTE: - Dont care
Description
Restriction
This command is used to transfer data MPU to DDRAM. This command makes no change to the other driver status. When this command is accepted, the column register and the row register are reset to the Start Column/Start Row positions. The Start Column/Start Row positions are different in accordance with MADCTR setting. (See 5.2.3) Then D [15:0] is stored in DDRAM and the column register and the row register increment as in Fig 5.2.4. Sending any other command can stop Frame Write. In all color modes, there is no restriction on length of parameters.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value Contents of memory is set randomly Contents of memory is not cleared Contents of memory is not cleared
Default
RAMWR
Image Data
Flow Chart
D1[15:0],D2[15:0], .,Dn[15:0
Display Action Mode Sequential transfer
Any Command
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7.1.24 RAMRD: Memory Read (2Eh)

Inst / Para RAMRD DC 0 WRB 1 1 : 1 RDB D15-8 1 D15-8 : : D15-8 D7 0 D7 : D7 D6 0 D6 : D6 D5 1 D5 : D5 D4 0 D4 : D4 D3 1 D3 : D3 D2 1 D2 : D2 D1 1 D1 : D1 D0 0 D0 : D0 (Code) (2Eh) : -
Dummy read 1 Data read 1 : : Data read 1 NOTE: - Dont care
Description
This command is used to transfer data from DDRAM to MPU. This command makes no change to the other driver status. When this command is accepted, the column register and the row register are reset to the Start Column/Start Row positions. The Start Column/Start Row positions are different in accordance with MADCTR setting. (See section 5.2.3) Then D[15:0] is read back from the DDRAM and the column register and the row register increment as in Fig. 5.2.4. Frame Read can be canceled by sending any other command. In all color modes, there is no restriction on length of parameters.
Note Memory Read is only possible via the Parallel Interface.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset
RAMRD Legend Dummy Command Parameter
Restriction
Availability Yes Yes Yes Yes Yes Default Value Contents of memory is set randomly Contents of memory is not cleared Contents of memory is not cleared
Default
Flow Chart
Display Image Data D1[15:0],D2[15:0] ..Dn[15:0] Action Mode Sequential transfer Any Command
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7.1.25 PTLAR: Partial Area (30h)

Inst / Para PTLAR
st
DC 0
WRB
1 parameter 1 PSL14 PSL13 PSL12 PSL11 PSL10 PSL9 PSL8 2nd parameter 1 PSL6 PSL5 PSL4 PSL3 PSL2 PSL1 PSL0 rd PEL14 PEL13 PEL12 PEL11 PEL10 PEL9 PEL8 3 parameter 1 th PEL6 PEL5 PEL4 PEL3 PEL2 PEL1 PEL0 4 parameter 1 NOTE: - Dont care This command defines the partial modes display area. There are 4 parameters associated with this command, the first defines the Start Row (PSL) and the second the End Row (PEL), as illustrated in the figures below. PSL and PEL refer to the DDRAM row address counter. If End Row > Start Row when MADCTL ML=0:
Start Row Non-displaying Area
RDB D17-8 D7 1 0 1 PSL15 1 PSL7 1 PEL15 1 PEL7
D6 0
D5 1
D4 1
D3 0
D2 0
D1 0
D0 0
(Code) (30h)
PSL [15:0]
Partial Display Area
PEL [15:0]
End Row Non-displaying Area
If End Row > Start Row when MADCTL ML=1:

End Row Non-displaying Area Non-displaying Area
PEL [15:0]
Description
PSL [15:0]
Start Row Non-displaying Area
If End Row < Start Row when MADCTL ML=0:

End Row
PEL [15:0]
Non-displaying Area
PSL [15:0]
Start Row
Restriction
If End Row = Start Row then the Partial Area will be one row deep. PSL[15:0] and PEL[15:0] should have below range (Parameter range: 0 PSL[15:0], PEL[15:0] 319 (013Fh) )
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Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Availability Yes Yes Yes Yes Yes Default Value PSL [15:0] 0000h 0000h 0000h PEL [15:0] 013Fh 013Fh 013Fh
Status
Default
1. To Enter Partial Mode
2. To Exit Partial Mode
PTLAR
Partial Mode
DISPOFF
PSL [15:0]
Optional To prevent Tearing Effect Image display
PEL [15:0]
NORON Legend
PTLON
Partial Mode OFF

Flow Chart
Partial Mode
RAMRW
Image Data D1[15:0],D2[15:0] ..Dn[15:0] Action Mode Sequential transfer
DISPON
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7.1.26 TEOFF: Tearing Effect Line OFF (34h)

Inst / Para DC WRB RDB D17-8 1 TEOFF 0 Parameter No Parameter NOTE: - Dont care D7 0 D6 0 D5 1 D4 1 D3 0 D2 1 D1 0 D0 0 (Code) (34h)
Description This command is used to turn OFF (Active Low) the Tearing Effect output signal from the TE signal line. Restriction This command has no effect when Tearing Effect output is already OFF.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes
Status
Default Value Off Off Off
Default
Legend
Command
TE Line Output ON
Parameter Display
Flow Chart
TEOFF
Action Mode
TE Line Output OFF
Sequential transfer
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7.1.27 TEON: Tearing Effect Line ON (35h)

Inst / Para TEON DC 0 WRB RDB D17-8 1 1 D7 0 D6 0 D5 1 D4 1 D3 0 D2 1 D1 0 D0 1 M (Code) (35h) -
This command is used to turn ON the Tearing Effect output signal from the TE signal line. This output is not affected by changing MADCTR bit ML. The Tearing Effect Line On has one parameter, which describes the mode of the Tearing Effect Output Line. (-=Dont Care). When M=0: The Tearing Effect Output line consists of V-Blanking information only.
tvdl tvdh
Description
Vertical Time Scale When M=1: The Tearing Effect Output line consists of both V-Blanking and H-Blinking information.
tvdl tvdh
Vertical Time Scale See Section 5.2.7 for more information.
Note: During Sleep In Mode with Tearing Effect Line On, Tearing Effect Output pin will be active Low.
Restriction
This command has no effect when Tearing Effect output is already OFF.
Default
Status Power On Sequence S/W Reset H/W Reset
Default Value Tearing effect off & M=0 Tearing effect off & M=0 Tearing effect off & M=0
TE Line Output OFF
Legend
Command Parameter
TEON Flow Chart

TE Mode Parameter (M)
TE Line Output ON
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7.1.28 MADCTR: Memory Data Access Control (36h)

Inst / Para MADCTR DC 0 WRB RDB D17-8 1 1 D7 0 MY D6 0 MX D5 1 MV D4 1 ML D3 0 RGB D2 1 D1 1 D0 0 (Code) (36h) -
This command defines read/write scanning direction of DDRAM. This command makes no change on the other driver status. Bit Assignment
Bit MY MX MV ML RGB NAME ROW ADDRESS ORDER COLUMN ADDRESS ORDER ROW/COLUMN EXCHANGE SCAN ADDRESS ORDER RGB-BGR ORDER DESCRIPTION These 3bits controls MPU to memory write/read direction. (See Section 5.2.3) LCD refresh direction control Color selector switch control. DDRAM must be updated after the RGB bit change. (0=RGB color filter panel, 1=BGR color filter panel)
ML: Scan Address Order ML=0

Memory
Sent First Sent 2nd Sent 3rd
Display
Sent last
Description
ML=1
Memory
Sent last
Display
Sent 3rd Sent 2nd Sent First
RGB=0
RG B
RGB: RGB-BGR Order RGB=1

RG B RG B
SIG1 SIG1
Driver IC SIG2 SIG2
SIG128 SIG128
RG B RG B
SIG1 SIG1
Driver IC SIG2 SIG2
RG B
SIG128 SIG128
BGR BGR
RG B RG B RG B RG B
BGR BGR BGR BGR
LCD Panel
LCD Panel
Restriction
D2, D1 and D0 of the 1st parameter are set to 000internally.
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Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset
Availability Yes Yes Yes Yes Yes Default Value MY=0,MX=0,MV=0,ML=0,RGB=0 No Change MY=0,MX=0,MV=0,ML=0,RGB=0
Default
MADCTR
Legend
Command Parameter
1 parameter
st
Flow Chart
(MY, MX, MV, ML, RGB)
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7.1.29 IDMOFF: Idle Mode Off (38h)

Inst / Para DC WRB RDB D17-8 1 IDMOFF 0 Parameter No Parameter NOTE: - Dont care D7 0 D6 0 D5 1 D4 1 D3 1 D2 0 D1 0 D0 0 (Code) (38h)
Description
Restriction
This command is used to recover from Idle mode on. There will be no abnormal visible effect on the display mode change transition. In the idle off mode, 1. LCD can display maximum 4k, 65k, 262k or 16M-colors. 2. Normal frame frequency is applied. This command has no effect when module is already in idle off mode.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value Idle Mode Off Idle Mode Off Idle Mode Off
Default
Idle mode on
Legend
Command Parameter
IDMOFF Display
Flow Chart
Idle mode off
Action Mode Sequential transfer
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7.1.30 IDMON: Idle Mode On (39h)

Inst / Para DC WRB RDB D17-8 1 IDMON 0 Parameter No Parameter NOTE: - Dont care D7 0 D6 0 D5 1 D4 1 D3 1 D2 0 D1 0 D0 1 (Code) (39h)
This command is used to enter into Idle mode on. There will be no abnormal visible effect on the display mode change transition. In the idle on mode, 1. Color expression is reduced. The primary and the secondary colors using MSB of each R,G and B in the DDRAM, 8 color depth data is displayed. 2. 8-Color mode frame frequency is applied. 3. Exit from IDMON by Idle Mode Off (38h) command (Example) Memory Display
Description
Color Black Blue Red Magenta Green Cyan Yellow White
R 7 R 6R 5 R 4 R 3 R 2 R 1 R 0 0XXXXXXX 0XXXXXXX 1XXXXXXX 1XXXXXXX 0XXXXXXX 0XXXXXXX 1XXXXXXX 1XXXXXXX
G7 G6 G5 G4 G3 G2 G1 G0 0XXXXXXX 0XXXXXXX 0XXXXXXX 0XXXXXXX 1XXXXXXX 1XXXXXXX 1XXXXXXX 1XXXXXXX
X: dont care B 7 B6 B5 B 4 B3 B 4 B1 B 0 0XXXXXXX 1XXXXXXX 0XXXXXXX 1XXXXXXX 0XXXXXXX 1XXXXXXX 0XXXXXXX 1XXXXXXX
Restriction
This command has no effect when module is already in idle on mode.

Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value Idle Mode Off Idle Mode Off Idle Mode Off
Default
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Idle mode off
Legend
Command Parameter
IDMON Display
Flow Chart
Idle mode on
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7.1.31 COLMOD: Interface Pixel Format (3Ah)

Inst / Para COLMOD DC 0 WRB RDB D17-8 1 1 D7 0 D6 0 RP2 D5 1 RP1 D4 1 RP0 D3 1 D2 0 P2 D1 1 P1 D0 0 P0 (Code) (3Ah) -
Description This command is used to define the format of RGB picture data, which is to be transferred via the MPU(P2-0) & RGB(RP2-0) Interface. The formats are shown in the table:
Interface Pixel Format Not Defined Not Defined Not Defined Not Defined Not Defined Not Defined 18Bit/Pixel 24Bit/Pixel P2(RP2) 0 0 0 0 1 1 1 1 P1(RP1) 0 0 1 1 0 0 1 1 P0(RP0) 0 1 0 1 0 1 0 1
NOTE: In 18 Bit/Pixel mode, the LSB Expansion is applied to transfer data into the DDRAM.
Restriction There is no visible effect until the DDRAM is written to.

Default
Default 24Bit/Pixel No Change 24Bit/Pixel
Example: Legend
24Bit/Pixel Mode Command Parameter COLMOD Display Action 110 Mode Sequential transfer
Flow Chart
18Bit/Pixel Mode
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7.1.32 WRDISBV : Write Display Brightness (51h)

Inst / Para WRDISBV DC 0 WRB RDB D17-8 D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 1 0 0 0 1 1 DBV7 DBV6 DBV5 DBV4 DBV3 DBV2 DBV1 DBV0 (Code) (51h) -
Description This command is used to adjust then brightness value of the display. It should be checked what the relationship between this written value and output brightness of the display is. This relationship is defined on the display module specification. 00h value means the lowest brightness and FFh value means the highest brightness. Restriction
The display supplier cannot use this command for tuning(e.g. factory tuning. Etc), because this command is only for Nokia.
Default
Default FFh FFh FFh
Example: Legend
Current Brightness Value Command Parameter WRDISBV Display Action DBV[7:0] Mode Sequential transfer
Flow Chart
New Brightness value
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7.1.33 RDDISBV : Read Display Brightness (52h)

Inst / Para RDDDISBV Dummy read 2nd Parameter DC 0 1 1 WRB 1 1 RDB D17-8 D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 1 0 0 1 0 DBV7 DBV6 DBV5 DBV4 DBV3 DBV2 DBV1 DBV0 (Code) (52h) -
NOTE: - Dont care
Description This command returns the brightness value of the display. It should be checked what the relationship between this written value and output brightness of the display is. This relationship is defined on the display module specification. 00h value means the lowest brightness and FFh value means the highest brightness. Restriction
Default
Default FFh FFh FFh
Example: Serial I/F Mode

RDDISBV[52h]
Parallel I/F Mode

RDDISBV[52h]
Legend
Command
Host Driver
Parameter Display
Flow Chart
Send 2 parameter
nd
Dummy Read
Action Mode
Send 2 parameter Sequential transfer
nd
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7.1.34 WRCTRLD: Write CTRL Display (53h)

Inst / Para WRCTRLD DC 0 WRB RDB D17-8 1 1 D7 0 D6 1 D5 0 BCTRL D4 1 D3 0 D2 0 BL D1 1 D0 1 (Code) (53h) -
Description This command is used to control brightness setting.

BCTRL : Brightness Controll Block On/Off. This bit is always used to switch brightness for display . 0 = Off ( Brightness registers are 00h ) 1 = On ( Brightness registers are active ) BL : Backlight Control On/Off 0 = Off ( Completely turn off backlight circuit : Control Lines must be low.) 1 = On
Restriction
The display supplier cannot use this command for tuning(e.g. factory tuning. Etc), because this command is of only for Nokia.
Default
Default 00h 00h 00h
Example: Legend
Command Parameter WRCTRLD Display Action BCTRL, BL Mode Sequential transfer
Flow Chart
New Control value
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7.1.35 RDCTRLD : Read CTRL Value Display (54h)

Inst / Para RDCTRLD Dummy read 2nd Parameter DC 0 1 1 WRB 1 1 RDB D17-8 1 D7 0 D6 1 D5 0 BCTRL D4 1 D3 0 D2 1 BL D1 0 D0 0 (Code) (54h) -
NOTE: - Dont care
Description This command returns the brightness control value. ( See Chapter 7.1.34 WRCTRLD )
BCTRL : Brightness Controll Block On/Off. This bit is always used to switch brightness for display . 0 = Off ( Brightness registers are 00h ) 1 = On ( Brightness registers are active ) BL : Backlight Control On/Off 0 = Off ( Completely turn off backlight circuit : Control Lines must be low.) 1 = On
Restriction
Default
Default 00h 00h 00h

RDCTRLD[54h]
Parallel I/F Mode

RDCTRLD[54h]
Legend
Command
Host Driver
Parameter Display
Flow Chart
Send 2 parameter
nd
Dummy Read
Action Mode
nd
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7.1.36 WRCABC: Write Content Adaptive Brightness (55h)

Inst / Para WRCTRLD DC 0 WRB RDB D17-8 1 1 D7 0 D6 1 D5 0 D4 1 D3 0 D2 0 D1 1 C1 D0 1 C0 (Code) (53h) -
Description This command is used to set parameters for image content based adaptive brightness control functionality.
There is possible to use 4 different modes for content adaptive image functionality, which are difined on a table below
C1 0 0 1 1 C0 0 1 0 1 Function OFF User Interface Image Still Picture Moving Image Note
Restriction
Default
Default 00h 00h 00h
Example: Legend
Command Parameter WRCABC Display Action C1,C0 Mode Sequential transfer
Flow Chart
New Adaptive Image
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7.1.37 RDCABC : Read Content Adaptive Brightness (56h)

Inst / Para RDCABC Dummy read 2nd Parameter DC 0 1 1 WRB 1 1 RDB D17-8 1 D7 0 D6 1 D5 0 D4 1 D3 0 D2 1 D1 1 C1 D0 0 C0 (Code) (56h) -
NOTE: - Dont care
Description This command is used to read the settings for image content based adaptive brightness control functionality.
There is possible to use 4 different modes for content adaptive image functionality, which are difined on a table below
C1 0 0 1 1 C0 0 1 0 1 Function OFF User Interface Image Still Picture Moving Image Note
Restriction
Default
Default 00h 00h 00h

RDCABC[56h]
Parallel I/F Mode

RDCABC[56h]
Legend
Command
Host Driver
Parameter Display
Flow Chart
Send 2 parameter
nd
Dummy Read
Action Mode
nd
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7.1.38 RDID1: Read ID1 Value (DAh)

Inst / Para RDID1 DC 0 WRB 1 1 RDB D17-8 D7 1 1 ID17 D6 1 ID16 D5 0 ID15 D4 1 ID14 D3 1 ID13 D2 0 ID12 D1 1 ID11 D0 0 ID10 (Code) (DAh) -
Dummy read 1 2nd Parameter 1 NOTE: - Dont care
This read byte returns 8-bit LCD modules manufacturer ID Description The 1st parameter is dummy data The 2nd parameter (ID17 to ID10): LCD modules manufacturer ID. NOTE: See command RDDID (04h), 2nd parameter.
Restriction
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value Not Fixed Not Fixed Not Fixed
Default
Serial I/F Mode

RDID1 (DAh)
Parallel I/F Mode

RDID1 (DAh)
Legend
Command
Host Driver
Parameter Display
Flow Chart
Send 2 parameter
nd
Dummy Read
Action Mode
nd
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7.1.39 RDID2: Read ID2 Value (DBh)

Inst / Para RDID2 DC 0 WRB 1 1 RDB D17-8 1 D7 1 1 D6 1 ID26 D5 0 ID25 D4 1 ID24 D3 1 ID23 D2 0 ID22 D1 1 ID21 D0 1 ID20 (Code) (DBh) -
This read byte returns 8-bit LCD module/driver version ID The 1st parameter is dummy data Description The 2nd parameter (ID26 to ID20): LCD module/driver version ID Parameter Range: ID=80h to FFh NOTE: See command RDDID (04h), 3rd parameter. Restriction
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value Not Fixed Not Fixed Not Fixed
Default
Serial I/F Mode

RDID2 (DBh)
Parallel I/F Mode

RDID2 (DBh)
Legend
Command
Host Driver
Parameter Display
Flow Chart
Send 2 parameter
nd
Dummy Read
Action Mode
nd
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7.1.40 RDID3: Read ID3 Value (DCh)

Inst / Para RDID3 DC 0 WRB 1 1 RDB D17-8 D7 1 1 ID37 D6 1 ID36 D5 0 ID35 D4 1 ID34 D3 1 ID33 D2 1 ID32 D1 0 ID31 D0 0 ID30 (Code) (DCh) -
This read byte returns 8-bit LCD module/driver ID. Description The 1st parameter is dummy data The 2nd parameter (ID37 to ID30): LCD module/driver ID. NOTE: See command RDDID (04h), 4th parameter. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value Not Fixed Not Fixed Not Fixed
Restriction
Default
Serial I/F Mode

RDID3 (DCh)
Parallel I/F Mode

RDID2 (DCh)
Legend
Command
Host Driver
Parameter Display
Flow Chart
Send 2 parameter
nd
Dummy Read
Action Mode
nd
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7.1.41 IFMODE: Set Display Interface Mode (B0h)

Inst / Para IFMODE
st
DC 0
WRB
RDB D17-8 1 -
D7 1
D6 0
D5 1
D4 1
D3 0
D2 0
D1 0
D0 0
(Code) (B0h)
1 parameter 1 2nd parameter 1 NOTE: - Dont care
1 1
DW
DP
EP
IF1 HSP
IF0 VSP
Sets the operation status of the display interface. The setting becomes effective as soon as the command is received. 1st parameter: Interface mode set
IF1 0 0 1 1 IF0 0 1 0 1 Data Transfer Mode MPU data transfer RGB data transfer1 RGB data transfer2 RGB data transfer3
Description
2nd parameter: RGB Interface bus width set

DW 0 1 RGB Interface Data Width 24-bit (1-transfer for one pixel) 8-bit (1-transfer for one pixel)
2nd parameter: Clock polarity set for RGB interface DP: DCK polarity set (0=data fetched at the rising edge, 1=data fetched at the falling edge) EP: ENABLE polarity (0= High enable for RGB interface, 1=Low enable for RGB interface) HSP: HSYNC polarity (0=Low level sync clock, 1=High level sync clock) VSP: VSYNC polarity (0= Low level sync clock, 1= High level sync clock)
F
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Availability Yes Yes Yes Yes Yes
Status
Default
IF [1:0] 00 00 00
Default Value DW DP/EP/HSP/VSP 0 0/0/0/0 0 0/0/0/0 0 0/0/0/0
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IFMODE
Legend Command
1st parameter: IF [1:0] 2nd parameter: DW/ DP/EP/HSP/VSP Flow Chart
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7.1.42 DISCLK: Display Clock Set (B1h)

Inst / Para DISCLK 1 parameter 2 parameter 3 parameter 4 parameter 5th parameter 6 parameter
th th rd nd st
DC 0 1 1 1 1 1 1
WRB
RDB D17-8 1 1 1 1 1 1 1
-
D7 1
HA7 HB7 -
D6 0
HA6 HB6 -
D5 1
HA5
D4 1
HA4
D3 0
HA3
D2 0
HA2
D1 0
HA1
D0 1
HA0
(Code) (B1h) -
BPA5 BPA4 BPA3 BPA2 BPA1 BPA0 FPA5 FPA4 FPA3 FPA2 FPA1 FPA0 HB5 HB4 HB3 HB2 HB1 HB0 BPB5 BPB4 BPB3 BPB2 BPB1 BPB0 FPB5 FPB4 FPB3 FPB2 FPB1 FPB0
Display clock condition set.

1st to 4th parameter: Display clock set for full colour display mode. HA [8:0]: Number of clocks during 1H = HA BPA [5:0]: Number of lines for vertical back porch FPA [5:0]: Number of lines for vertical front porch 5th to 8th parameter: Display clock set for 8-colour display mode. HB [8:0]: Number of clocks during 1H = HB BPB [5:0]: Number of lines for vertical back porch FPB [5:0]: Number of lines for vertical front porch Description By using DISCLK command, frame frequency can be set like below fFRA (Hz) = 1 / ((Number of gate + 1 dummy gate + BPA + FPA) * ((HA+1) * 2usec)) for full colour display mode fFRB (Hz) = 1 / ((Number of gate + 1 dummy gate + BPB + FPB ) * ((HB+1) * 2usec)) for 8-colour display mode BPA (BPB) and FPA (FPB) are related to the vertical mode TE signal pulse width. TE (vertical mode, high pulse width) = (BFA + FPA+2) * ((HA+1) * 2usec) for full colour display mode TE (vertical mode, high pulse width) = (BFB + FPB+2) * ((HB+1) * 2usec) for 8-colour display mode Restriction Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes
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Status Power On Sequence S/W Reset H/W Reset HA [7:0] 23d (17h) 23d (17h) 23d (17h) BPA [5:0] 16d (10h) 16d (10h) 16d (10h)
Default Value FPA [5:0] HB [7:0] 6d (06h) 28d (1Ch) 6d (06h) 28d (1Ch) 6d (06h) 28d (1Ch)
BPB [5:0] 16d (10h) 16d (10h) 16d (10h)
FPB [5:0] 6d (06h) 6d (06h) 6d (06h)
Default
The default frame frequency (normal mode, 320 gate + 1 dummy gate) = 1/((321+16+6)*(23+1)*2usec) = 60.8Hz The default frame frequency (idle mode, 320 gate + 1 dummy gate) = 1/( (321+16+6)*(28+1)*2usec) = 50.2Hz Vertical TE signal high pulse width = (16+6+2)*(23+1)*2usec = 1,152 usec (for normal mode) = (16+6+2)*(28+1)*2usec = 1,392 usec (for idle mode)
DISCLK
Flow Chart
1 and 2 parameter: HA [7:0] 3rd parameter: BPA [5:0] 4th parameter: FPA [5:0] 5th and 6th parameter: HB [7:0] 7th parameter: BPB [5:0] 8th parameter: FPB [5:0]
st
nd
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7.1.43 INVCTR: Inversion Control (B2h)

Inst / Para INVCTR 1 parameter 2nd parameter
st
DC 0 1 1
WRB
RDB D17-8 1 1 1 -
D7 1 0 0
D6 0 0 0
D5 1 0 0
D4 1 0 0
D3 0 -
D2 0
D1 1
D0 0
(Code) (B2h) -
NLA2 NLA1 NLA0 NLB2 NLB1 NLB0
Display inversion mode set 1st parameter: for full colour display mode NLA2 to NLA0: line inversion value set 2 parameter: for 8 colour display mode NLB2 to NLB0: line inversion value set NLA2 (NLB2) 0 0 0 0 1 1 1 1
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value 1 parameter 01h 01h 01h
st
nd
Description
NLA1 (NLB1) 0 0 1 1 0 0 1 1
NLA0 (NLB0) 0 1 0 1 0 1 0 1
Inversion Frame inversion 1-Line inversion 2-Line inversion 3-Line inversion 4-Line inversion 5-Line inversion 6-Line inversion 7-Line inversion
Restriction
Status
Default
2 parameter 00h 00h 00h
nd
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Legend
INVCTR
Command Parameter
Flow Chart
1 parameter: NLA [2:0] 2nd parameter: NLB [2:0]
st
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7.1.44 REGCTR: Regulator Control (C0h)

Inst / Para REGCTR 1 parameter
st
DC 0 1
WRB
RDB D17-8 1 1
-
D7 1
-
D6 1
VR2
D5 0
VR1
D4 0
VR0
D3 0
-
D2 0
VS2
D1 0
VS1
D0 0
VS0
(Code) (C0h) -
Regulator voltage control

The 1st parameter: VR [2:0]: VR regulator output control VS [2:0]: VS regulator output control Description
VR [2:0] 0 1 2 3 4 5 6 7 VR output VR = 3.00V VR = 3.50V VR = 3.75V VR = 4.00V VR = 4.25V VR = 4.50V VR = 4.75V VR = 5.00V VS [2:0] 0 1 2 3 4 5 6 7 VS/VG output VS = 3.00V VS = 3.50V VS = 3.75V VS = 4.00V VS = 4.25V VS = 4.50V VS = 4.75V VS = 5.00V
Restriction
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Availability Yes Yes Yes Yes Yes Default Value VR [2:0] 3h 3h 3h VS [2:0] 5h 5h 5h
Legend Command
Default
REGCTR
1st parameter Flow Chart
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7.1.45 VCOMCTR: VCOML / VCOMH Voltage Control (C1h)

Inst / Para VCOMCTR
st
DC 0
WRB
1 parameter 1 2nd parameter 1 NOTE: - Dont care
RDB D17-8 1 1 1
D7 1 -
D6 1 -
D5 0
D4 0
D3 0
D2 0
D1 0
D0 1
(Code) (C1h) -
VCLC5 VCLC4 VCLC3 VCLC2 VCLC1 VCLC0 VCHC5 VCHC4 VCHC3 VCHC2 VCHC1 VCHC0
VCOML / VCOMH Voltage Control

The 1st parameter: VCOML voltage control (See below table) The 2nd parameter: VCOMH voltage control (See below table) Description
VCLC [5:0] 0 1 2 : 60 61 ~ 63 VCOML output voltage VCOML = -2.00 V VCOML = -1.95 V VCOML = -1.90 V : VCOML = +1.00V Not permitted VCHC [5:0] 0 1 2 : 60 61 ~ 63 VCOMH output voltage VCOMH = +2.50 V VCOMH = +2.55 V VCOMH = +2.60 V : VCOMH = +5.50V Not permitted
Restriction
Default value of VCOMH will be fixed to the trimmed value during wafer test.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset VCLC [5:0] 32h 32h 32h Availability Yes Yes Yes Yes Yes Default Value VCHC [5:0] See note See note See note
Default
NOTE: After Wafer level test, the default value of VCHC will be trimmed to fit the target VCOM amplitude.
VCOMCTR
Legend Command
1st parameter: VCLC [5:0] Flow Chart 2nd parameter: VCHC [5:0]
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7.1.46 GAMCTR1: Set Gamma Correction Characteristics (C8h)

Inst / Para GAMCTR1 1 parameter 2nd parameter 3rd parameter 4 parameter
th st
DC 0 1 1 1 1
WRB
RDB D17-8 1 1 1 1 1
-
D7 1
D6 1
D5 0
GS102 GS122 GS142 GS162
D4 0
GS101 GS121 GS141 GS161
D3 1
GS100 GS120 GS140 GS160
D2 0
GS112 GS132 GS152 GS172
D1 0
GS111 GS131 GS151 GS171
D0 0
GS110 GS130 GS150 GS170
(Code) (C8h)
Set the gray scale voltage to adjust the gamma characteristics of the TFT panel.
Description
It apply to gamma curve selection by instruction code 26h. 1st to 4th parameter: Gamma curve1 adjustment register
Restriction
Status
Default
Default Value GS10[2:0] ~ GS17[2:0] 4/4/4/4/4/4/4/4 4/4/4/4/4/4/4/4 4/4/4/4/4/4/4/4
GAMCTR1
Legend Command
Flow Chart
1nd parameter 2 parameter .. 4th parameter
st
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7.1.47 GAMCTR2: Set Gamma Correction Characteristics (C9h)

Inst / Para GAMCTR2 1 parameter 2nd parameter 3rd parameter 4th parameter
st
DC 0 1 1 1 1
WRB
RDB D17-8 1 1 1 1 1
-
D7 1
D6 1
D5 0
GS202 GS222 GS242 GS262
D4 0
GS201 GS221 GS241 GS261
D3 1
GS200 GS220 GS240 GS260
D2 0
GS212 GS232 GS252 GS272
D1 0
GS211 GS231 GS251 GS271
D0 1
GS210 GS230 GS250 GS270
(Code) (C9h)
Description
Restriction
Status
Default
GAMCTR2
Legend Command
Flow Chart
1 parameter 2nd parameter .. 4th parameter
st
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7.1.48 GAMCTR3: Set Gamma Correction Characteristics (CAh)

st
DC 0 1 1 1 1
WRB
RDB D17-8 1 1 1 1 1
-
D7 1
D6 1
D5 0
GS302 GS322 GS342 GS362
D4 0
GS301 GS321 GS341 GS361
D3 1
GS300 GS320 GS340 GS360
D2 0
GS312 GS332 GS352 GS372
D1 1
GS311 GS331 GS351 GS371
D0 0
GS310 GS330 GS350 GS370
(Code) (CAh)
Description
Restriction
Status
Default
GAMCTR3
Legend Command
Flow Chart
st
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7.1.49 GAMCTR4: Set Gamma Correction Characteristics (CBh)

st
DC 0 1 1 1 1
WRB
RDB D17-8 1 1 1 1 1
-
D7 1
D6 1
D5 0
GS402 GS422 GS442 GS462
D4 0
GS401 GS421 GS441 GS461
D3 1
GS400 GS420 GS440 GS460
D2 0
GS412 GS432 GS452 GS472
D1 1
GS411 GS431 GS451 GS471
D0 1
GS410 GS430 GS450 GS470
(Code) (CBh)
Description
Restriction
Status
Default
GAMCTR4
Legend Command
Flow Chart
st
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7.1.50 EPPGMDB: Write ID2, VCOM Offset Value

Inst / Para
EPPGMDB
DC 0 1 1
WRB
Parameter Parameter
RDB D17-8 1 1 1 1 -
D7 1 ID26
D6 1 ID25
D5 0 ID24
D4 1 ID23
D3 0 ID22
D2 0
D1 0
D0 0
VCOF80
(Code) (D0h) -
VCOF82 VCOF81
VCOF5 VCOF4 VCOF3 VCOF2 VCOF1
VCOF0
ID21
ID20
db_sel
This command is used to write the values of ID2 , VCOM and VCOM8 to internal register. These value is programmed into EEPROM by command EPPGM(D2h). VCOM Offset Control 1st Parameter: VCOM offset control(8color)
VCOF8 [2:0] 0(default) 1 2 3 4 5 6 7 VCLC (Internal) VCLC VCLC-3 VCLC-2 VCLC-1 VCLC VCLC+1 VCLC+2 VCLC+3 VCHC (Internal) VCHC VCHC-3 VCHC-2 VCHC-1 VCHC VCHC+1 VCHC+1 VCHC+3
2nd Parameter: VCOM offset control

VCOF [5:0] 0(default) 1 : 31 32 33 : 63 VCLC (Internal) VCLC VCLC-31 : VCLC-1 VCLC VCLC+1 : VCLC+31 VCHC (Internal) VCHC VCHC-31 : VCHC-1 VCHC VCHC+1 : VCHC+31
Description
NOTE: If VCLC (Internal) or VCHC (Internal) is less than 0, it becomes 0. If VCLC (Internal) or VCHC (Internal) is larger than 31, it becomes 31. The VCOF[5:0] is stored in EEPROM to fit contrast. 3rd Parameter: ID2[6:0] Write 7-bit LCD module/driver version ID to save it to EEPROM. 3rd Parameter: db_sel 0 = Using the EEPROM data for making VCOMH & VCOML. 1 = Using the internal register values written by EPPGMDB for VCOMH & VCOML. The following drawing shows how to use db_sel to fix the VCOF and the VCOF8.
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MPU By command EPPGMDB
Internal Register
VCOF[5:0] db_sel : VCOF8[2:0

0 : EEPROM data is used 1 : internal Register data is used
M U X EEPROM
VCOF[5:0] VCOF8[2:0]
VCOM Gen
VCOMH VCOML
LDS285
The user shoule fix VCOF and VCOF8 to adjust the VCOMH and VCOML output voltage level. The user can use db_sel to find out which value is suitable for VCOMH and VCOML. If the user sets db_sel to 1, then LDS285 uses the internal register value to make the proper VCOMH and VCOML output voltage instead of the value read from EEPROM. That means that the user can control and monitor the VCOMH and VCOML output voltage by changing the parameter of the command EPPGMDB and find out the proper value of the 1st and the 2nd parameter of the command EEPGMDB before programming the VCOF[5:0] and VCOF8[2:0] into EEPROM.
Restriction
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Status
Default
VCOF8[2:0] 0 0 0
Default Value VCOF[5:0] ID2 0 Not Fixed (80 ~ FFh) 0 Not Fixed (80 ~ FFh) 0 Not Fixed (80 ~ FFh)
db_sel 0 0 0
Legend
EPPGMDB (D0h) Command Parameter Send 1 parameter
st
Display Action
Flow Chart
Send 2 parameter
nd
Send 3 parameter
rd
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7.1.51 EPERASE: EPROM Erase (D1h)

Inst / Para EPERASE Parameter Description Restriction DC WRB 0 No Parameter RDB 1 D17-8 D7 1 D6 1 D5 0 D4 1 D3 0 D2 0 D1 0 D0 1 (Code) (D1h)
EEPROM data erase. It will be necessary to wait more than 150msec after EEPROM erase start . Refer to 7.3.3&7.3.4 EEPROM access flow. EPERASE should be excuted in Sleep-in mode.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability No No No No Yes Default Value Disable Disable Disable
Default
EPERASE
Legend Command Display
Flow Chart
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7.1.52 EPPROG: EPROM Program (D2h)

Inst / Para EPPROG Parameter Description Restriction DC WRB 0 No Parameter RDB 1 D17-8 D7 1 D6 1 D5 0 D4 1 D3 0 D2 0 D1 1 D0 0 (Code) (D2h)
EEPROM data program. It will be necessary to wait more than 100msec after EEPROM program start . Refer to 6.3.3&6.3.4 EEPROM access flow. EEPROG should be excuted in Sleep-in mode.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability No No No No Yes Default Value Disable Disable Disable
Default
EPPROG
Flow Chart
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7.1.53 EPRDVRF: EPROM Read Verify (D3h)

Inst / Para EPRDVRF Parameter DC 0 1 WRB RDB 1 1 D17-8 D7 1 D6 1 D5 0 D4 1 D2 D1 0 1 PGM READ ERVF VF D3 0 D0 1
0
(Code) (D3h)
.When READ =1, PGMVF =0 & ERVF =0 , then EEPROM data are normally read to Internal register. .When READ =0, PGMVF =1 & ERVF =0, then the read verification for the programmed data will be executed by using the internal reference voltage(VDD1). This mode is to read the programmed value from EEPROM under the more serious condition than normal read mode. .When READ =0, PGMVF =0 & ERVF = 1, then the read verification for the erased data verification will be executed by using the external reference voltage.(ME_CMP ). This mode is to read the erased value from EEPROM under the more serious condition than normal read mode. It will be necessary to wait more than 100usec after EEPROM read start . Refer to 7.3.3&6.3.4 EEPROM access flow.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value Disable Disable Disable
Description
Restriction
Default
EPREAD
Flow Chart
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7.1.54 RDVCOF: VCOM offset registers bits Read Back (D9h)

DC WR RD D17-8 D7 B B 1 1 RDVCOF 0 Dummy Read 1 1 1 2nd Parameter 1 1 3rd Parameter 1 Inst / Para D6 1 D5 0 -
D4 1 -
D3 1 -
D2 0 -
D1 0 -
D0 1 -
(Code) (D9h) Dummy
RVCOF5 RVCOF4 RVCOF3 RVCOF2 RVCOF1 RVCOF0

RVCOF82 RVCOF81 RVCOF80
This read 6-bit VCOM register offset value and additional 4-bit VCOM offset value. (refer to 6.1.60) The 1st parameter is dummy data Description The 2nd parameter RVCOF[5:0] : range 0d ~ 63d The 2nd parameter RVCOF8[2:0]: range 0 ~ 7. Restriction
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Availability Yes Yes Yes Yes Yes Default Value RVCOF[5:0], RVCOF8[2:0] -
Default
Serial I/F Mode

RDVCOF
Parallel I/F Mode

RDVCOF
Legend
Command
Host Driver
Parameter Display
Flow Chart
Send 2 parameter
nd
Dummy Read
Action Mode
Send 3 parameter
rd
Send 2 parameter Sequential transfer Send 3 parameter

rd
nd
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7.1.55 LEDCTRL: Write the configuration for LED driver

Inst / Para
EPPGMDB
DC 0 1 1
WRB
Parameter Parameter
RDB D17-8 1 1 1 1 -
D7 1 0 0
D6 1 -
D5 1 -
D4 0 -
D3 1 DB3
D2 1 DB2 0
D1 1 DB1 0
D0 1 TYPE DB0 0
(Code) (EFh) -
ADR2 ADR1 ADR0
PER3 PER2 PER1 PER0
This command is used to configure the LED driver control 1st Parameter: TYPE 0 : When LDS285 controls LED Driver type with pwm pulse contol. 1 : When LDS285 controls LED Driver LDS8816 with 1-wire digital interface. 2nd Parameter: ADR[2:0], DB[3:0] When TYPE = 1, LDS285 write DB[3:0] to ADDR[2:0] register in LDS8861. ( Please refer to Section 6.4 and the specification for LDS8861 ) 3rd Parameter: PER[3:0] When TYPE = 0, PER[3:0] decide the period of PWM pulse which is sent through LCD_CNT. (Please refer to Section 6.4 ) Restriction
Description
Status
Default
TYPE 0 0 0
Default Value ADR[2:0] DB[3:0] 0 Eh 0 Eh 0 Eh
PER[3:0] 0 0 0
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Legend
LEDCTRL(EFh) Command Parameter Display Send 1 parameter
st
Action Mode
Flow Chart
Send 2 parameter
nd
Sequential transfer
Send 3 parameter
rd
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7.2 RESET TABLE (DEFAULT VALUE) (TBD)

Item DDRAM Sleep In/Out Display On/Off Display mode (normal/partial) Display Inversion On/Off Display Idle Mode On/Off Column: Start Address (XS) Column: End Address (XE) Row: Start Address (YS) Row: End Address (YE) After Power On Random In Off Normal Off Off 0000h 00EFh 0000h 013Fh After Hardware Reset No Change In Off Normal Off Off 0000h 00EFh 0000h 013FFh After Software Reset No Change In Off Normal Off Off 0000h
007Fh (239d) (when MV=0) 009Fh (319d) (when MV=1)
0000h
009Fh (319d) (when MV=0) 007Fh (239d) (when MV=1) FFh
Brightness Control Value *3) FFh FFh Gamma setting GC0 GC0 Partial: Start Address (PSL) 0000h 0000h Partial: End Address (PEL) 013Fh 013Fh Tearing: On/Off Off Off Tearing Effect Mode *4) 0 (Mode1) 0 (Mode1) Memory Data Access Control 0/0/0/0/0 0/0/0/0/0 (MY/MX/MV/ML/RGB) Interface Pixel Color Format 7 (24-Bit/Pixel) 7 (24-Bit/Pixel) RDDPM 08h 08h RDDMADCTR 00h 00h RDDCOLMOD 7 (24-Bit/Pixel) 7 (24-Bit/Pixel) RDDIM 00h 00h RDDSM 00h 00h RDDSDR 00h 00h ID1 TBD TBD ID2 TBD TBD ID3 TBD TBD Notes: 1. There will be no abnormal visible effects on the display when S/W or H/W Reset is applied. 2. Powered-On Reset finishes within 10s after both VDD1_IO, VDD1 & VDD2 are applied. 3. Brightness conrol value is related with the command WRDISBV(51h). 4. TE Mode 1 means Tearing Effect Output Line consists of V-Blanking Information only.
GC0 0000h 013Fh Off 0 (Mode1) No Change No Change 08h No Change No Change 00h 00h 00h TBD TBD TBD
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7.3
7.3.1
INSTRUCTION SETUP FLOW

Initializing with the Built-in Power Supply Circuits (TBD)
Initializing Start (Power ON)

H/W Reset
Power Input: VSS, VDD1 and VDD2 (Any order) Wait Until Power Stabilization !RES = L Wait for more than 10s !RES = H Wait for more than 5ms
SLPOUT (Sleep mode OFF & OSC/Booster On)
Power Supply Set
INVON / INVOFF (Display Inversion / Normal Set) IDMON / IDMOFF (Idle Mode On/Off) PTLAR / PTLON / PTLOFF (Partial Area Set & Partial On/Off) - Partial start/end line set (PSB, PEB) SCRLAR (Area Scroll Set) - Top fixed area, scroll area and bottom fixed area set (TFA, VSA, BFA) VSCSAD (Scroll Start Address Set) - Scroll start address (SSA) MADCTR (Memory Data Access Control) - Row direction (MY), column direction (MX), address direction (V), scan direction (ML) and RGB order COLMOD (Interface Pixel Format Set) WRCTRLD ( Brightness control) On/Off
Display Environment Set2 (If not used, can be skipped)
RASET / CASET (Row/Column Address Set) - Start/end row address set (YS, YE), Start/end column address set (XS, XE) RAMWR (Memory Data Write) Wait for more than 120ms after power control command DISPON (Display ON)
Display Data Write & Display On
Initializing End
Fig. 7.3.1
Initializing with the built-in power supply circuits
The initializing sequence does not have any effect on the display. The display is in its normal background color during the initialization.
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7.3.2
Power OFF Sequence (TBD)
Power OFF Start (Without H/W Reset)

DISPOFF (Display OFF) All of the common & segment pins become VC potential. SLPIN (Sleep IN) All the liquid crystal power supply circuits and oscillator circuit become OFF.
Stop the Power Supply: VDD2 and VDD1 stop (any order)
Power OFF End
Power OFF Start (With H/W Reset)

H/W Reset
!RES = L Wait for more than 10s !RES = H
Stop the Power Supply: VDD2 and VDD1 stop (any order)
Power OFF End
Fig. 7.3.2
Power OFF sequence
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7.3.3
EEPROM Access Sequence for Initialization (Data Clear)
Start
EXTC = VDD1 RESET Apply 21.0V ~ 23.0V at ME_CMP pad EEPROM Data Clear * EPERASE command Wait for more than 150msec
Remove ME_CMP External Power * SLPOUT command
EEPROM Clear Data Verification
* Erase Verify Command : EPRDVRF ( D3h ) 1st Parameter : 02h * RDVCOF command * RDDID2 command
Read data all 0? Yes
No
End
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7.3.4
EEPROM Access Sequence for program (Data write) (TBD)

Start
EXTC = VDD1 RESET
* EPPROM data Write to internal register Command : EPPGMDB (D0h) 1st parameter : {5b0,VCOF8[2:0]} 2nd parameter: {2b0, VCOF[5:0]} rd 3 parameter: {ID2[6:0],db_sel}
Apply 8.2V ~ 8.8V at ME_CMP pad
EEPROM Programming
* EPPROG command Wait for more than 40msec
Remove ME_CMP External Power * SLPOUT command * Program Verify Command : EPRDVRF ( D3h ) st 1 Parameter : 04h
EEPROM Programming Verify
* RDVCOF command * RDDID2 command
Read data all correct? Yes
No
Re-execute EEPROM Initialization (clear) Refer to 7.3.3
End
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SPECIFICATIONS
(VSS = 0V) Unit V V V V V C
8.1 ABSOLUTE MAXIMUM RATINGS

Item Supply voltage (1) Supply voltage (2) Drive Supply Voltage Logic input voltage range Logic output voltage range Operating temperature range Symbol VDD1 VDD2 VGH VGL VIN VO TOPR Value - 0.3 ~ + 2.0 - 0.3 ~ + 3.6 - 0.3 ~ + 28.0 - 0.3 ~ VDD1 + 0.3 - 0.3 ~ VDD1 + 0.3 - 30 ~ + 75
Storage temperature range TSTG - 55 ~ + 125 C NOTE: If the absolute maximum rating of even is one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. Absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the product within the range of the absolute maximum ratings
8.2 ESD PROTECTION LEVEL

Table 8.2.1 ESD models.
Model Human Body Model Machine Model
Test Condition C = 100 pF, R = 1.5 k C = 200 pF, R = 0.0
Protection Level > 2000 > 200
Unit V V
8.3 LATCH-UP PROTECTION LEVEL

The device will not latch up at trigger current levels less than 100 mA.
8.4 LIGHT SENSITIVITY

The operation of the IC will not be materially altered by incident light.
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8.5 MAXIMUM SERIES RESISTANCE

The driver will operate in Chip on Glass applications with series resistances (due to ITO track resistance). Voltages are specified at module I/O assuming maximum values as in Table 7.5.1.
Table 8.5.1 Maximum series resistance on module.
Name VDD1 VDD2 VSS OSC SRGB, SINV, SMX, SMY, VGLX4, FRM, EXTC, PSEL TGS, TEST2, TEST3 P68, BS2, BS1, BS0 RESB CSB (!SCE) DC (SCL) WRB RDB TE, VSYNCO D15 to D0 D23 to D16, VDO DCK, ENABLE, VSYNC, HSYNC VGH VGL VCOMH,VCOML VR VS VREG_DC VDC1 C1P, C1M C2P, C2M C3P, C3M C4P, C4M C5P, C5M C6P, C6M
Type Power supply Power supply Power supply Input Input
Maximum Series Resistance 10 10 10 100 100
Unit

Input Input Input Input Input Input Output Input / Output Input
100 100 100 100 100 100 100 100 100
Capacitor connection Capacitor connection Capacitor connection Capacitor connection Capacitor connection Capacitor connection Booster1 Power Supply Capacitor connection Capacitor connection Capacitor connection Capacitor connection Capacitor connection Capacitor connection
10 10 10 10 10 5 5 10 10 10 10 10 10
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8.6
8.6.1
DC CHARACTERISTICS
Basic Characteristics
(VSS=0V, VDD1=1.65V to 1.95V, VDD2=2.3V to 2.9V,Ta = -30 to 70C)
Symbol Conditions Related Pins MIN TYP MAX Unit
Parameter Power & Operating Voltages
I/O interface Voltage Logic Operating voltage Analog Operating voltage Gate Drive High Voltage1 Gate Drive Low Voltage1 Drive Supply Voltage1
Input / Output
V DD1IO VDD1 VDD2 VGH VGL VGH-VGL
PSEL=0 -
*2) VDD1_IO,VDD1 *2) VDD1 *2) VDD2 *3) VGH *3) VGL *3) VGH, VGL
1.65 1.65 2.3 9 -15 15
1.8/2.75 1.8 2.75 16.0 -12.0 28.0
3.3 1.95 3.3 20.0 -6.0 30 V
High level input voltage Low level input voltage High level output voltage Low level output voltage Input leakage current Oscillator frequency
Booster
VIH VIL VOH VOL IIL fOSC IOH = -1.0mA IOL = +1.0mA VIN = VDD1 or VSS IAVDD=1mA, dual-type, X2 IAVDD=1mA, single-type, X2 IAVDD=1mA, single-type, X3 IGH=300uA, 4*VR IGL=-300uA, -3*VR ICL=-300uA, -1*VDD2 Default, No load Default, No load
*1) *2) *1) *2) *2) D17 to D0, TE, TEST1 *1) *2) -
0.7VDD1 VSS 0.8VDD1 VSS -1.0 450
500
VDD1 0.3VDD1 VDD1 0.2VDD1 +1.0 550

A
kHz
AVDD boost voltage1 AVDD boost voltage2 AVDD boost voltage3 VGH boost voltage VGL boost voltage VCL boost voltage VS output voltage VR output voltage
AVDD1 AVDD2 AVDD3 VGH VGL VCL VS VR
*3) AVDD *3) AVDD *3) AVDD *3) VGH *3) VGL *3) VCL *3) VS *3) VR
1.9*VDD2 1.8*VDD2 2.7*VREG_ DC 3.6*VR -2*VR -1*VDD2 3.00 3.00
2.0*VDD2 2.0*VDD 3.0*VREG_ DC
4.2 4.00
4.0*VR -1.8*VR -0.9*VDD2 6.00 5.00
NOTE: *1) SRGB, SINV, SMX, SMY, DCK, ENABLE, VSYNC, HSYNC, OSC, P68, ,BS2, BS1, BS0, CSB, RESB, DC, WRB, RDB, D23 to D0 pins *2) *3) When the measurement are performed with LCD module, Measurement Points are like below
Measurement point for *3) FPC Measurement point for *2)
LCD Panel Connector pin or flex side

Capacitor
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Parameter VCOM Generator
Symbol
Conditions
Related Pins
MIN
TYP
MAX
Unit
VCOM amplitude
VCOMA
No load VCOM output = High IVCOM = 1mA VCOM output = Low IVCOM = 1mA Rap~Rjp, Ran~Rjn, R0~R62 of gray voltage generator VS=3.75V, VSO=V0 at positive, VOUT=V0-2V VS=3.75V, VSO=V0 at negative, VOUT=V0-2V VSS1+1.0 ~ VS-1.0
VCOMH VCOML VCOM VCOM 200 200 TBD
VCOM output high resistance RVCOMH VCOM output low resistance

Source Driver
RVCOML
TBD
Gray scale resistance
Rgray IVOSH IVOSL
S1 to S720 S1 to S720 S1 to S720 S1 to S720
0.7*Rx 100 0.1 -
Rx -200 200
10 30
1.3*Rx -100 20 50
A A
*1) *2) Drive output current
mV mV V k
Output voltage deviation Output voltage range

Gate Driver
DVOS VOS RONG
VSS1+0.1V ~ VSS1+1.0 S1 to S720 VS-1.0 ~ VS-0.1V Ta = 25C S1 to S720 G1 to G320
VS-0.1 3
*3) Output ON resistance
NOTE: 1) VSO is the output voltage of source output pins S1 to S720. 2) VOUT is the applied voltage to source output pins S1 to S720 3) Resistance value when -0.1[mA] is applied during the ON status of the gate output pin G1 to G320. RON [] = V [V] / 0.1[mA] (V: Voltage change when 0.1[mA] is applied in the on status.)
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8.6.2 Current Consumption

Host I/F Mode of operation Frame Inversion Frequency Mode
TBD TBD TBD TBD TBD TBD
Image
Note 1 Note 2 Note 3 Note 4 Note 5 Note 5
Current consumption Memory Data Typical Worst case Access Control VDD2 VDD1 VDD2 VDD1 (MY:MX:MV) (mA) (mA) (mA) (mA)
X;X;X X;X;X X;X;X X;X;X X;X;X X;X;X TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
- Normal Mode On - Partial Mode Off - Idle Mode Off - Sleep Out Mode
Host interface NOT active
60Hz
- Normal Mode On - Partial Mode Off - Idle Mode On - Sleep Out Mode - Normal Mode Off - Partial Mode On (32 lines) - Idle Mode Off - Sleep Out Mode - Normal Mode Off - Partial Mode On (32 lines) - Idle Mode On - Sleep Out Mode - Sleep In Mode
60Hz
60Hz
TBD
Grey Levels
X;X;X
TBD
TBD
TBD
TBD
TBD 60Hz TBD N/A N/A
Note 6 Note 7 N/A 262k Colors NOTE 8
X;X;X X;X;X X;X;X 0;0;0 0;0;1 0;1;0 0;1;1 1;0;0 1;0;1 1;1;0 1;1;1 0;0;0 0;0;1 0;1;0 0;1;1 1;0;0 1;0;1 1;1;0 1;1;1
TBD TBD 0.002 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
TBD TBD 0.010 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
Host interface active
- Normal Mode On - Partial Mode Off - Idle Mode Off - Sleep Out Mode
CPU Access @ 15fps 60Hz TBD 262k Colors NOTE 8 CPU Access @ 25fps
Typical Case: NOTE: X Do not care TA = 25C 1. All pixels black VDD2 = 2.75V VDD1 = 1.8V 2. Checker board one by one 3. Checker board 4 by 4 Worst Case: 4. Grey-scale from top to bottom TA = -30 to70C 5. 20% Black, 80%White VDD2 = 2.5V to 2.9V VDD1 = 1.65V to 1.95V 6. Black & White Checker board 8 by 8. Includes Process Variance. 7. Absolute Worst Case Patterns: Defined by Display Supplier 8. Absolute Worst Case Patterns and Sequences: Defined by Display Supplier 9. Absolute worst case VDD current is less than TBD mA in the case of CPU access is inactive, Normal Mode On, Partial Mode Off, Idle Mode Off, Sleep Out mode. 10. Absolute worst case VDD1_IOI current is less than TBD mA in the case of CPU access is inactive, Normal Mode On, Partial Mode Off, Idle Mode Off, Sleep Out mode. 11. Inrush currents are not included in current consumption values
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8.7
8.7.1
AC CHARACTERISTICS(TBD)
Parallel Interface Characteristics (8080-series MPU)
tCHW tCHW VIH VIL tCS VIH VIL tAST tWRL tAHT tWC VIH VIL tRCS/tRCSFM tRC/tRCFM tRDL/tRDLFM VIH tRDH/tRDHFM tDST tDHT VIL tRAT/tRATFM VOH VOL tODH VOH VOL tCSF VIH VIL tWRH tAHT tCSH tCSF
!CS
D/!C
!WR
!RD
D17 to D0
VIH VIL
Fig. 8.7.1
Parallel Interface characteristics (8080-series MPU)
(VSS=0V, VDD1=1.65V to 1.95V, VDD2=2.5V to 2.9V,Ta = -30 to 75C

Signal
DC
Symbol tAST tAHT
Parameter Address setup time Address hold time (Write/Read)
MIN 10 10
CSB
tCHW tCS tRCS tRCSFM tCSF tCSH tWC tWRH tWRL tRC tRDH tRDL tRCFM tRDHFM tRDLFM tDST tDHT tRAT tRATFM tODH
Chip select H pulse width Chip select setup time (Write) Chip select setup time (Read ID) Chip select setup time (Read FM) Chip select wait time (Write/Read) Chip select hold time Write cycle Control pulse H duration Control pulse L duration Read cycle (ID) Control pulse H duration (ID) Control pulse L duration (ID) Read cycle (FM) Control pulse H duration (FM) Control pulse L duration (FM) Data setup time Data hold time Read access time (ID) Read access time (FM) Output disable time
0 35 45 355 10 10 100 35 35 160 90 45 450 90 355 10 10 20
WRB
RDB (ID)
RDB (FM)
D17 to D0
MAX 40 340 80
Unit
Description
ns
ns
ns
ns
When read ID data
ns
When read from DDRAM
ns
For maximum CL=30pF For minimum CL=8pF
NOTE: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDD1 for Input signals. For output, see Section
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7.7.6.1
Input Signal Slope tr
VIH=0.7*VDD1 VIL=0.3*VDD1
Output Signal Slope tf tr tf
VOH=0.8*VDD1 VOL=0.2*VDD1
tCHW
!CS
tWC
!WR, !RD
tCSF Min. 5ns
Note: Logic high and low levels are specified as 30% and 70% of VDD1IO for
Fig. 8.7.2 Chip select timing
!CS
!WR
!RD
twrh trdh trdhfm
Note: Logic high and low levels are specified as 30% and 70% of VDD1IO for input
Fig. 8.7.3 Write to read and read to write timing
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8.7.2
Parallel Interface Characteristics (6800-series MPU)

tCHW tCHW VIH VIL tCS tCSH tCSF
!CS
D/!C
VIH VIL
R/!W
VIH VIL
tAST
tAHT
tRC/tRCFM tRCS/tRCSFM tWC VIH VIL tWRH tDST tDHT tWRL tRDL/tRDLFM VIL VIH tRDH/tRDHFM tRAT/tRATFM
tAHT
tODH
D1 to D0
VIH VIL
Fig. 8.7.4
Parallel Interface characteristics (6800-series MPU)

Signal
DC
CSB
Symbol tAST tAHT tCHW tCS tRCS tRCSFM tCSF tCSH
Parameter Address setup time Address hold time (Write/Read) Chip select H pulse width Chip select setup time (Write) Chip select setup time (Read ID) Chip select setup time (Read FM) Chip select wait time (Write/Read) Chip select hold time
MIN 10 10 0 35 45 355 10 10
WRB
RDB (ID)
RDB (FM)
D17 to D0
tWC tWRH tWRL tRC tRDH tRDL tRCFM tRDHFM tRDLFM tDST tDHT tRAT tRATFM tODH
Write cycle Control pulse H duration Control pulse L duration Read cycle (ID) Control pulse H duration (ID) Control pulse L duration (ID) Read cycle (FM) Control pulse H duration (FM) Control pulse L duration (FM) Data setup time Data hold time Read access time (ID) Read access time (FM) Output disable time
100 35 35 160 90 45 450 90 355 10 10 20
MAX 40 340 80
Unit
Description
ns
ns
ns
ns
When read ID data
ns
When read from DDRAM
ns
For maximum CL=30pF For minimum CL=8pF
NOTE: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDD1_IO for Input signals. For output, see Section 7.7.6.1
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8.7.3
Serial Interface Characteristics (3-Pin Serial)
!SCE
tCSS tSCYCW/tSCYCR tSLW/tSLR tSCC VIH VIL tSDS tSHW/tSHR tSDH tf tr tCSH tCHW
SCL
SDA (SDI)
tACC tOH
SDA (SDO)
Fig. 8.7.5
3-pin serial interface characteristics

Parameter Serial clock cycle (Write) SCL H pulse width (Write) SCL L pulse width (Write) Data setup time (Write) Data hold time (Write) Serial clock cycle (Read) SCL H pulse width (Read) SCL L pulse width (Read) Symbol Conditions
tSCYCW tSHW tSLW tSDS tSDH tSCYCR tSHR tSLR tACC tOH tSCC tCHW tCSS tCSH
SCL SDA SCL SDA For maximum CL=30pF For minimum CL=8pF SDA For maximum CL=30pF For minimum CL=8pF !SCE !SCE !SCE
MIN 100 35 35 30 30 150 60 60
TYP
MAX
Unit
50 50
ns ns ns ns ns ns ns
Access rime Output disable time SCL to Chip select SCEB H pulse width Chip select setup time Chip select hold time
10 15 15 45 60 65
ns
NOTE: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDD1 for Input signals. For output, see Section 7.7.6.2
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8.7.4 Serial Interface Characteristics (4-Pin Serial)
!SCE
tCSS tSCYCW/tSCYCR tSLW/tSLR tSCC VIH VIL tSDS tSHW/tSHR tSDH tf tr tCSH tCHW
SCL SDA (SDI)
tDCS
tDCH
D/!C
tACC tOH
SDA (SDO)
Fig. 8.7.6
4-pin serial interface characteristics

Parameter Serial clock cycle (Write) SCL H pulse width (Write) SCL L pulse width (Write) Data setup time (Write) Data hold time (Write) DC setup time DC hold time Serial clock cycle (Read) SCL H pulse width (Read) SCL L pulse width (Read) Symbol Conditions
tSCYCW tSHW tSLW tSDS tSDH tDCS tDCH tSCYCR tSHR tSLR tACC tOH tSCC tCHW tCSS tCSH
SCL SDA DC SCL SDA For maximum CL=30pF For minimum CL=8pF SDA For maximum CL=30pF For minimum CL=8pF !SCE !SCE !SCE
MIN 100 35 35 30 30 30 30 150 60 60
TYP
MAX
Unit
50 50
ns ns ns ns ns ns ns ns
Access rime Output disable time SCL to Chip select SCEB H pulse width Chip select setup time Chip select hold time
10 15 15 45 60 65
ns
NOTE: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDD1 for Input signals. For output, see Section 7.7.6.2
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8.7.5
RGB Interface Characteristics
VSYNC HSYNC
V IH V IL tDSYN VIH VIL tDCSH
ENABLE
tDCSS tDCYC
DCK
tDLW tDDS tDHW tDDH
D23-D1, VD0
Fig. 8.7.7
RGB Interface characteristics

Symbol tDCYC tDLW tCHW tDDS tDDH tDCSS tDCSH Parameter DCK cycle time DCK Low time DCK High time RGB Data setup time RGB Data hold time ENABLE setup time ENABLE hold Time Conditions Related Pins MIN TBD TBD TBD 20 20 150 150 TYP MAX Unit
DCK DCK, D23-D1, VD0 ENABLE DCK, HSYNC, VSYNC
ns ns ns ns
tDSYN
SYNC setup time
20
NOTE: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less.
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8.7.6
Reset Input Timing
Shorter than 5s
tRESW
!RES
tREST
Internal Status
Normal Operation
Resetting
Initial Condition (Default for H/W reset)
Fig. 8.7.8
Reset input timing

Symbol Parameter Related Pins MIN TYP MAX Note Unit s
tRESW
*1) Reset low pulse width
RESB -
10 -
5 120
When reset applied during Sleep In mode When reset applied during Sleep Out mode
ms ms
tREST
*2) Reset complete time -
NOTE: 1) Spike due to an electrostatic discharge on RESB line does not cause irregular system reset according to the table below.
RESB Pulse Shorter than 5s Longer than 10s Between 5s and 10s Action Reset Rejected Reset Reset Start
2) During the resetting period, the display will be blanked (The display is entering blanking sequence, which maximum time is 120 ms, when Reset Starts in Sleep Out mode. The display remains the blank state in Sleep In mode) and then return to Default condition for H/W reset. 3) During Reset Complete Time, ID2 and VCOMOF value in OTP will be latched to internal register during this period. This loading is done every time when there is H/W reset complete time (tREST) within 5ms after a rising edge of RESB. 4) Spike Rejection also applies during a valid reset pulse as shown below:
10s Reset is accepted 10s
1s
Less than 1sec width positive spike will be rejected.
5) It is necessary to wait 5msec after releasing RESB before sending commands. Also Sleep Out command cannot be sent for 120msec. .
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8.7.7
Measurement Conditions
8.7.7.1 tRATFM, tODH Measurement Condition Measurement Condition Set-up
Data Generator
Oscilloscope See NOTE Connector
LCD Panel
FPC
External components for test condition (pull-down and pull-up cases) which are removed after test: Resistor: 3kOhm 5% Capacitor: 8 or 30pF 10% See NOTE
Connector Pin / Measurement Point
NOTE: Capacitances and resistances of the oscilloscopes probe must be included externals components in these measurements Minimum Value Measurement
70%
!RD
tODH
D(n) [n=0..23]
(pulled up)
D(n) [n=0..23]
(pulled down) Measurement circuit pulled down
External components on the connector pin
0% 100%
Measurement circuit pulled up

VDD1 3kOhm
D(n) [n=0..23]
(pulled down)
Measurement point on the connector pin
3kOhm 8pF
D(n) [n=0..23]
(pulled up)
8pF
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Maximum Value Measurement
70%
RDB D(n) [n=0..23]

(pulled up)
30% tRAT/tRATFM tODH
20% 80%
D(n) [n=0..23]
0% 100%

VDD1
D(n) [n=0..23]
(pulled down)
3kOhm 30pF
3kOhm
D(n) [n=0..23]
(pulled up)
30pF
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8.7.7.2 tACC, tOH Measurement Condition Measurement Condition Set-up
Data Generator
Oscilloscope See NOTE Connector
LCD Panel
FPC
External components for test condition (pull-down and pull-up cases) which are removed after test: Resistor: 3kOhm 5% Capacitor: 8 or 30pF 10% See NOTE
Connector Pin / Measurement Point
NOTE: Capacitances and resistances of the oscilloscopes probe must be included externals components in these measurements Minimum Value Measurement
70%
SCL SDA
(pulled up)
30% 100% tOH
tACC
SDA
0%
0% 100%

VDD1 3kOhm
SDA (DOUT) SDA (DOUT)

3kOhm 8pF
8pF
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Maximum Value Measurement
70%
!RD
tACC tOH
SDA
(pulled up)
20% 80%
SDA
0% 100%

VDD1
3kOhm
SDA (DOUT) SDA (DOUT)

3kOhm 30pF
30pF
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9
9.1
REFERENCE APPLICATIONS
MICROPROCESSOR INTERFACE
Interfacing with 3-Pin Serial Mode (P68 = "L", BS2=L, BS1 = "L", BS0 = "L")
MPU L D S 285
P68 BS2 BS1 BS0 !R E S !C S D /!C (S C L ) !R D !W R (D /!C ) D 2 3 to D 1 D 0 (S D A )
9.1.1
VSS1
!R E S !C S SCL O p en O p en V D 2 3 to V D 1 SDA
G ra p h ic C o n tro lle r
VD0 D C K, EN ABLE VSYNC, HSYNC O PEN
VD0 DCK, ENABLE VSYNC, HSYNC VSYNCO
If R G B in te rfa c e is n o t u s e d , p le a s e c o n n e c t th e s e p in s an d D 2 3 ~ D 1 p in s to V S S 1
Fig. 9.1.1
Interfacing with 3-Pin Serial Mode
9.1.2 Interfacing with 4-Pin Serial Mode (P68 = "H", BS2=L, BS1 = "L", BS0 = "L")
VDD1 MPU
P68 BS2 BS1 BS0 !R E S !C S D /!C (S C L ) !R D !W R (D /!C ) D 2 3 to D 1 D 0 (S D A )
L D S 285
VSS1
!R E S !C S SCL O p en D /!C V D 2 3 to V D 1 SDA
VD0 DCK, ENABLE VSYNC, HSYNC O PEN
If R G B in te rfa c e is n o t u s e d , p le a s e c o n n e c t th e s e p in s a n d D 2 3 ~ D 1 p in s to V S S 1
Fig. 9.1.2
Interfacing with 4-Pin Serial Mode
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9.1.3
Interfacing with 8080-series MPU 8-Bit Bus (P68 = "L", BS2=L, BS1 = "L", BS0 = "H")
VDD1 8 0 8 0 -S e rie s M P U
P68 BS2 BS1 BS0 RESB CSB D /!C !R D !W R VSS1 D 7 to D 0
L D S 285
VSS1
!R E S !C S D /!C !R D !W R D 2 3 to D 8 D 7 to D 0
VSS1
VSS1 VSS1 O PEN
In th e p a ra lle l in te rfa c e m o d e , R G B in te rfa c e c a n n o t b e u se d
Fig. 9.1.3
Interfacing with 8-bit 8080-series
9.1.4 Interfacing with 6800-series MPU 8-Bit Bus (P68 = "H", BS2=L, BS1 = "L", BS0 = "H")
P68 BS2 BS1 BS0 RESB CSB RS E R /!W VSS1 D 7 to D 0
L D S 285
VSS1
!R E S !C S D /!C (R S ) !R D (E ) !W R (R /!W ) D 2 3 to D 8 D 7 to D 0
VSS1 VSS1 VSS1 O PEN

In th e p a ra lle l cannot be used

in te rfa c e m ode, RGB in te rfa c e
Fig. 9.1.4
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9.1.5
Interfacing with 8080-series MPU 9-Bit Bus (P68 = "L", BS2=H, BS1 = "L", BS0 = "L")
P68 BS2 BS1 BS0 !R E S !C S D /!C !R D !W R VSS1 D 8 to D 0
L D S 285
VSS1
!R E S !C S D /!C !R D !W R D 2 3 to D 9 D 8 to D 0


Fig. 9.1.5
9.1.6 Interfacing with 6800-series MPU 9-Bit Bus (P68 = "H", BS2=H, BS1 = "L", BS0 = "L")
P68 BS2 BS1 BS0 RESB CSB RS E R /!W VSS1 D 8 to D 0
L D S 285
VSS1
!R E S !C S D /!C (R S ) !R D (E ) !W R (R /!W ) D 2 3 to D 9 D 8 to D 0
Fig. 9.1.6
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9.1.7 Interfacing with 8080-series MPU 16-Bit Bus (P68 = "L", BS2=L, BS1 = "H", BS0 = "H")
P68 BS2 BS1 BS0 RESB CSB D /!C !R D !W R VSS1 D 1 5 to D 0
L D S 285
VSS1
!R E S !C S D /!C !R D !W R D 2 3 to D 1 6 D 1 5 to D 0
Fig. 9.1.7
9.1.8 Interfacing with 6800-series MPU 16-Bit Bus (P68 = "H", BS2=L, BS1 = "H", BS0 = "H")
P68 BS2 BS1 BS0 !R E S !C S RS E R /!W VSS1 D 1 5 to D 0
L D S 285
VSS1
!R E S !C S D /!C (R S ) !R D (E ) !W R (R W ) D 2 3 to D 1 6 D 1 5 to D 0
VSS1 VSS1 VSS1 VSYNCO


Fig. 9.1.8
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9.1.9
Interfacing with 8080-series MPU 18-Bit Bus (P68 = "L", BS2=H, BS1 = "H", BS0 = "L")
P68 BS2 BS1 BS0 RESB CSB D /!C !R D !W R VSS1 D 1 7 to D 0
L D S 285
VSS1
!R E S !C S D /!C !R D !W R D 2 3 to D 1 8 D 1 7 to D 0
VSS1 D C K, EN ABLE VSYNC, HSYNC O PEN


Fig. 9.1.9
9.1.10 Interfacing with 6800-series MPU 18-Bit Bus (P68 = "H", BS2=H, BS1 = "H", BS0 = "L")
V D D 1 IO 6 8 0 0 -S e rie s M P U L D S 285
P68 BS2 BS1 BS0 !R E S !C S RS E R /!W VSS1 D 1 7 to D 0
VSS1
!R E S !C S D /!C (R S ) !R D (E ) !W R (R /!W ) D 2 3 to D 1 8 D 1 7 to D 0
VSS1 D C K, EN ABLE VSYNC, HSYNC O PEN


Fig. 9.1.10
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9.2
9.2.1
CONNECTIONS WITH LCD PANEL

One Layer Connection for Gate output
RGB filter order = BGR (from left top of the panel)
CASE2 R G B B G R
G319 : : : : : G3 G1 S720 G2 S1 G320
RGB filter order = RGB (from left top of the panel)

CASE1
G320 : : : : : G4 G2
R B G
G319 : : : :
SMX = 1 SMY = 1 SRGB = 1 S1 = Filter B S2 = Filter G S3 = Filter R
: : : : : G4 G2 S720 G2
SMX = 1 SMY = 1 SRGB = 0 S1 = Filter R S2 = Filter G S3 = Filter B
: G3 G1 S1
Bumps down
LDS284
G1 G319
Bumps down
LDS284
G1 G319
. G320
. G320
CASE3
G319 : : : : : G3 G1 S1 S720
CASE4 R G B B G R
G320 : : : : : G4 G2 G319
R B G
G320 : : : :
: : : : : G3 G1 S1
: G4 G2 S720
G1 G319
Bumps up
LDS284
G2 G320
G1 G319
Bumps up
LDS284
G2 G320
CASE5
G319
CASE6
LDS284
G320 G2 S720 G319
LDS284
G320 G2 S720
.
G1 G3 : : : : : G319
G1 S1
Bumps down
G B B G R
.
G2 G4 : : : : : G320
.
G1 G3 : : : : : G319
G1 S1
Bumps down
G R B G R
.
G2 G4 : : : : : G320
CASE7
G320
CASE8
LDS284
G319 G1 S1 G320
LDS284
G319 G1 S1
.
G2 G4 : : : : : G320
G2 S720
Bumps up
G B B G R
.
G1 G3 : : : : : G319
.
G2 G4 : : : : : G320
G2 S720
Bumps up
G R B G R
.
G1 G3 : : : : : G319
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9.2.2 Two Layer Connection for Gate output

RGB filter order = RGB (from left top of the panel)
CASE9
G2 : : : : : G318 G320 S720 G2 S1
RGB filter order = BGR (from left top of the panel)

CASE10
G2
B B G
G1 : : : :
R B G
G1 : : : :
: : : : : G318 G320 S720 G2
: G317 G319
: G317 G319 S1
Bum ps down
LDS284
G1 . G319
Bum ps down
LDS284
G1 . G319
G320
G320
CASE11
G1 : : : : : G317 G319 S1 S720
CASE12 G B B G R
G2 : : : : : G318 G320 G1
R B G
G2 : : : :
: : : : : G317 G319 S1
: G318 G320 S720
G1 G319
Bum ps up
LDS284
G2 G320
G1 G319
Bum ps up
LDS284
G2 G320
CASE13
G319
CASE14
LDS284
G320 G2 S720 G319
LDS284
G320 G2 S720
.
G319 G317 : : : : : G1
G1 S1
Bum ps down
G B B G R
.
G320 G318 : : : : : G2
.
G319 G317 : : : : : G1
G1 S1
Bum ps down
G R B G R
.
G320 G318 : : : : : G2
CASE15
G320
CASE16
LDS284
G319 G1 S1 G320
LDS284
G319 G1 S1
.
G320 G318 : : : : : G0
G2 S720
Bum ps up
G B B G R
.
G319 G317 : : : : : G1
.
G320 G318 : : : : : G0
G2 S720
Bum ps up
G R B G R
.
G319 G317 : : : : : G1
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9.3
EXAMPLE CONNECTION WITH PANEL (CASE11)
Frame Memory
(1,1)
(1,1)
240 x 320 Panel Viewing Area
(240,320)
G319 - - G1 S1 - - -- S720 G2 - - - G320 LDS285 Bumps Up
SMX = VSS SMY = VSS SRGB = VSS
Bumps Down
IC LCD (Front Side) GLASS
Bumps up
LCD (Front Side) GLASS IC
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9.4
CONNECTION EXAMPLE WITH EXTERNAL COMPONENTS
V DD V D D2 VD D 1 VD D 2 VD C 1 VR EG _D C
D1 C1 C1
C2
O ptional
VS VR
D1
AVD D C 1P C 1M C 2P C 2M C 3P C 3M C 4P C 4M C 5P C 5M C 6P C 6M
C2 C2 C2 C3 C3 C3 C1
VG H VC L VG L
D1
C3 C1 C1
C1 C2 C3 D1
C1 C1
= = = =
1.0F ~ 2.2F(T ypical :1.0uF) 1.0F ~ 2.2F(T ypical :2.2uF) 0.22F Schottk y diode VF(Forward) = 0.3V / 50m A
VC O M H VC O M L
VSS
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9.4.1
Application Circuit Example
NOTE: 1) To use extended command set like EEPROM program, EXTC should be connected to VDD1 and External voltage should be appled to ME_CMP pad, so, EXTC and ME_CMP should have probing point for mass production.
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9.5
EXTERNAL COMPONENTS CONNECTION

Connection Typical capacitance value 1.0 uF 1.0 uF 1.0 uF 1.0 uF
Pad Name
VCOMH VCOML VGL VCL VSS1_R VSS1 VSS2 VSS2_DC VDD1_R VDD2_DC VGH C6+, C6C5+, C5C4+, C4C3+, C3C2+, C2C1+, C1VDC1 VREG_DC AVDD VR VS VDD1 VGL AVDD VS
Connect to Capacitor (Max 6V): VCOMH---(+)----| |--- (-)------VSS Connect to Capacitor (Max 3V): VCOML ---(-)----| |--- (+)-----VSS Connect to Capacitor (Max 12V): VGL ---(-)----| |--- (+)-----VSS Connect to Capacitor (Max 5V): VCL ---(-)----| |--- (+)-----VSS Connect to VSS(GND) Connect to VSS(GND) Connect to VSS(GND) Connect to VSS(GND) Connect to VDD1 Connect to VDD2 Connect to Capacitor (Max 16V): VGH ---(+)----| |--- (-)-----VSS Connect to Capacitor (Max 5V): C6+ ---(+)----| |--- (-)-----C6Connect to Capacitor (Max 7V): C5+ ---(+)----| |--- (-)-----C5Connect to Capacitor (Max 7V): C4+ ---(+)----| |--- (-)-----C4Connect to Capacitor (Max 7V): C3+ ---(+)----| |--- (-)-----C3Connect to Capacitor (Max 5V): C2+ ---(+)----| |--- (-)-----C2Connect to Capacitor (Max 5V): C1+ ---(+)----| |--- (-)-----C1Connect to VDD2( in case of x3 avdd3 mode, Connect to VREG_DC) Connect to Capacitor (Max 2.6V): VREG_DC ---(+)----| |--- (-)-----VSS Connect to Capacitor (Max 6V): AVDD ---(+)----| |--- (-)-----VSS Connect to Capacitor (Max 6V): VR ---(+)----| |--- (-)-----VSS Connect to Capacitor (Max 6V): VS ---(+)----| |--- (-)-----VSS When PSEL = Low VDDI (Digital Power) When PSEL = High Connect to Capacitor (Max 5V): VDD1 (R) ---(+)----| |--- (-)-----VSS Connect to Shottky Diode between VSS Connect to Shottky Diode between VDD2 Connect to Shottky Diode between VDD2
1.0 uF 1.0 uF 1.0 uF 1.0 uF 1.0 uF 2.2 uF 2.2 uF 2.2 uF 2.2 uF 1.0 uF 1.0 uF
2.2 uF VF = 0.3V / 50mA VF = 0.3V / 50mA VF = 0.3V / 50mA
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10 CHIP INFORMATION
10.1 CHIP OVERVIEW
1140
Non-parttern area
30 40 30 30 40 30
115 100 535 280

(1357) (4) (1) (1362)
330
100
G2 G4
100
Bump Align
(5)
3220
(8)
Input Pad Dimension
G318 (1198) G320 DUMMY
60
70
(1194)
60 140
24
S000 S001
(384-1)*60=22980 Output Pad Dimension
14420
22000 um
20
Source Pad Gate Pad VCOM Pad Gate control Pad Diagnostic Pad Input Pad Dummy Pad Align Mark
19 21 100 25
(475)
S718 S719 S720 DUMMY
220
(471)
G319 G317
(299)
3220
280 535
(312)
G3 G1
100
(307) (306)
115
330
LDS285 Bumps Up
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NOTE: * Chip Size = 22,000 x 1140 (Excluding Scribe Lane) * Chip Thickness = 410 12 m * Bump height = 15 3 m (chip to chip), less than 2 m (pad to pad in one chip)
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10.2 BUMP INFORMATION

10.2.1 Source / Gate / VCOM / Gate control / Output side dummy Pad Format
Item Pad pitch Bump width Bump length Bump to Bump gap1 (Vertical) Bump to Bump gap2 (Horizontal) Bump area Chip boundary to Bump edge Symbol A B C D E B*C F Size Source / Gate / VCOM / Gate control / / Output side dummy pad 20um 21 um 100 um 25 um 19 um 2 2100 um 8.5 um
Chip Boundry
F B
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10.2.2 Input / Input side dummy Pad Format

Item Pad pitch Bump width Bump length Bump to Bump gap (Horizontal) Bump area Chip boundary to Bump edge Symbol A B C E B*C F Size Input / Input side dummy pad 70 um 50 um 80 um 20 um 2 4000 um 12.5 um
F B
Chip Boundry
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10.3 PAD COORDINATES

Table 10.3.1 Pad Center Coordinates
No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Name DUMMY DUMMY DUMMY DUMMY PADA<0> PADA<1> PADB<1> ME_CMP ME_CMP ME_CMP ME_CMP ME_VME5 ME_VME5 D<23> D<22> D<21> D<20> D<19> D<18> VSYNCO DUMMY OSC TGS D_VDD1IO D_VSS1 P68 EXTC BS0 BS1 BS2 SRGB DUMMY DUMMY VD0 RSB VSYNC HSYNC DCK ENABLE D<17> D<16> D<15> D<14> D<13> D<12> D<11> D<10> D<9> D<8> SMY
X -10885 -10815 -10745 -10465 -10395 -10325 -10255 -10185 -10115 -10045 -9975 -9905 -9835 -9765 -9695 -9625 -9555 -9485 -9415 -9345 -9275 -9205 -9135 -9065 -8995 -8925 -8855 -8785 -8715 -8645 -8575 -8505 -8435 -8365 -8295 -8225 -8155 -8085 -8015 -7945 -7875 -7805 -7735 -7665 -7595 -7525 -7455 -7385 -7315 -7245
Y -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5
No 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Name DUMMY SMX D<7> D<6> D<5> D<4> D<3> D<2> D<1> D<0> SINV LED_CNT RDB WRB DC CSB D_VDD1IO DUMMY FRM TE TEST2 TEST3 TEST1 TEST4 DUMMY DUMMY DUMMY DUMMY DUMMY PSEL DUMMY DUMMY DUMMY DUMMY DUMMY VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2
X -7175 -7105 -7035 -6965 -6895 -6825 -6755 -6685 -6615 -6545 -6475 -6405 -6335 -6265 -6195 -6125 -6055 -5985 -5915 -5845 -5775 -5705 -5635 -5565 -5495 -5425 -5355 -5285 -5215 -5145 -5075 -5005 -4935 -4865 -4795 -4725 -4655 -4585 -4515 -4445 -4375 -4305 -4235 -4165 -4095 -4025 -3955 -3885 -3815 -3745
Y -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5
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No 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150
Name VDD2 VDD1_IO VDD1_IO VDD1_IO VDD1_IO VDD1_IO VDD1_IO VDD1_IO VS VS VS VS VS VS VS VS VDD1_R VDD1_R VDD1_R VDD1_R VDD1_R VDD1_R VDD1_R VDD1_R VDD1_R VSS1_R VSS1_R VSS1_R VSS1_R VSS1_R VSS1_R VSS1_R VSS1_R VSS1_R VSS1_R VSS1_R VSS1_R VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VDD1 VDD1
X -3675 -3605 -3535 -3465 -3395 -3325 -3255 -3185 -3115 -3045 -2975 -2905 -2835 -2765 -2695 -2625 -2555 -2485 -2415 -2345 -2275 -2205 -2135 -2065 -1995 -1925 -1855 -1785 -1715 -1645 -1575 -1505 -1435 -1365 -1295 -1225 -1155 -1085 -1015 -945 -875 -805 -735 -665 -595 -525 -455 -385 -315 -245
Y -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5
No 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200
Name VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1_R VDD1_R VDD1_R VDD1_R VSS1_R VSS1_R VSS1_R VSS1_R VSS1_R VSS1_R VSS1_R VSS1_R VSS1_R VSS1_R VCOM VCOM VCOM VCOM VCOM VCOM VCOMH VCOMH VCOMH VCOMH VCOMH VCOMH VCOML VCOML VCOML VCOML VCOML VCOML VR VR VR VR VR VR VR VR
X -175 -105 -35 35 105 175 245 315 385 455 525 595 665 735 805 875 945 1015 1085 1155 1225 1295 1365 1435 1505 1575 1645 1715 1785 1855 1925 1995 2065 2135 2205 2275 2345 2415 2485 2555 2625 2695 2765 2835 2905 2975 3045 3115 3185 3255
Y -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5
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No 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250
Name VCL VCL VCL VGH VGH VGH AVDD AVDD AVDD AVDD AVDD AVDD AVDD VREG_DC VREG_DC VREG_DC VDC1 VDC1 VDC1 VDC1 VDC1 VDD2 VDD2 VDD2 VDD2 VDD2_DC VDD2_DC VDD2_DC VDD2_DC VDD2_DC C1M C1M C1M C1M C1M C1P C1P C1P C1P C1P C2M C2M C2M C2M C2M C2P C2P C2P C2P C2P
X 3325 3395 3465 3535 3605 3675 3745 3815 3885 3955 4025 4095 4165 4235 4305 4375 4445 4515 4585 4655 4725 4795 4865 4935 5005 5075 5145 5215 5285 5355 5425 5495 5565 5635 5705 5775 5845 5915 5985 6055 6125 6195 6265 6335 6405 6475 6545 6615 6685 6755
Y -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5
No 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300
Name VSS2 VGL VGL VGL VGL VGL VGL VGL VGL VGL VGL VGL VGL VSS2 VSS2 VSS2 VSS2_DC VSS2_DC VSS2_DC VSS2_DC VSS2_DC VSS2_DC DUMMY C6M C6M C6M DUMMY C6P C6P C6P DUMMY C3M C3M C3M C3P C3P C3P C4M C4M C4M C4P C4P C4P C5M C5M C5M C5P C5P C5P PADA<2>
X 6825 6895 6965 7035 7105 7175 7245 7315 7385 7455 7525 7595 7665 7735 7805 7875 7945 8015 8085 8155 8225 8295 8365 8435 8505 8575 8645 8715 8785 8855 8925 8995 9065 9135 9205 9275 9345 9415 9485 9555 9625 9695 9765 9835 9905 9975 10045 10115 10185 10255
Y -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5
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No 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350
Name DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY G<1> G<3> G<5> G<7> G<9> G<11> G<13> G<15> G<17> G<19> G<21> G<23> G<25> G<27> G<29> G<31> G<33> G<35> G<37> G<39> G<41> G<43> G<45> G<47> G<49> G<51> G<53> G<55> G<57> G<59> G<61> G<63> G<65> G<67> G<69> G<71> G<73> G<75> G<77>
X 10325 10395 10465 10745 10815 10885 10670 10650 10630 10610 10590 10570 10550 10530 10510 10490 10470 10450 10430 10410 10390 10370 10350 10330 10310 10290 10270 10250 10230 10210 10190 10170 10150 10130 10110 10090 10070 10050 10030 10010 9990 9970 9950 9930 9910 9890 9870 9850 9830 9810
Y -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5
No 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400
Name G<79> G<81> G<83> G<85> G<87> G<89> G<91> G<93> G<95> G<97> G<99> G<101> G<103> G<105> G<107> G<109> G<111> G<113> G<115> G<117> G<119> G<121> G<123> G<125> G<127> G<129> G<131> G<133> G<135> G<137> G<139> G<141> G<143> G<145> G<147> G<149> G<151> G<153> G<155> G<157> G<159> G<161> G<163> G<165> G<167> G<169> G<171> G<173> G<175> G<177>
X 9790 9770 9750 9730 9710 9690 9670 9650 9630 9610 9590 9570 9550 9530 9510 9490 9470 9450 9430 9410 9390 9370 9350 9330 9310 9290 9270 9250 9230 9210 9190 9170 9150 9130 9110 9090 9070 9050 9030 9010 8990 8970 8950 8930 8910 8890 8870 8850 8830 8810
Y 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5
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No 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450
X 8790 8770 8750 8730 8710 8690 8670 8650 8630 8610 8590 8570 8550 8530 8510 8490 8470 8450 8430 8410 8390 8370 8350 8330 8310 8290 8270 8250 8230 8210 8190 8170 8150 8130 8110 8090 8070 8050 8030 8010 7990 7970 7950 7930 7910 7890 7870 7850 7830 7810
Y 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5
No 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500
Name G<279> G<281> G<283> G<285> G<287> G<289> G<291> G<293> G<295> G<297> G<299> G<301> G<303> G<305> G<307> G<309> G<311> G<313> G<315> G<317> G<319> DUMMY DUMMY DUMMY S<720> S<719> S<718> S<717> S<716> S<715> S<714> S<713> S<712> S<711> S<710> S<709> S<708> S<707> S<706> S<705> S<704> S<703> S<702> S<701> S<700> S<699> S<698> S<697> S<696> S<695>
X 7790 7770 7750 7730 7710 7690 7670 7650 7630 7610 7590 7570 7550 7530 7510 7490 7470 7450 7430 7410 7390 7370 7350 7130 7110 7090 7070 7050 7030 7010 6990 6970 6950 6930 6910 6890 6870 6850 6830 6810 6790 6770 6750 6730 6710 6690 6670 6650 6630 6610
Y 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5
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No 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550
Name S<694> S<693> S<692> S<691> S<690> S<689> S<688> S<687> S<686> S<685> S<684> S<683> S<682> S<681> S<680> S<679> S<678> S<677> S<676> S<675> S<674> S<673> S<672> S<671> S<670> S<669> S<668> S<667> S<666> S<665> S<664> S<663> S<662> S<661> S<660> S<659> S<658> S<657> S<656> S<655> S<654> S<653> S<652> S<651> S<650> S<649> S<648> S<647> S<646> S<645>
X 6590 6570 6550 6530 6510 6490 6470 6450 6430 6410 6390 6370 6350 6330 6310 6290 6270 6250 6230 6210 6190 6170 6150 6130 6110 6090 6070 6050 6030 6010 5990 5970 5950 5930 5910 5890 5870 5850 5830 5810 5790 5770 5750 5730 5710 5690 5670 5650 5630 5610
Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5
No 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600
X 5590 5570 5550 5530 5510 5490 5470 5450 5430 5410 5390 5370 5350 5330 5310 5290 5270 5250 5230 5210 5190 5170 5150 5130 5110 5090 5070 5050 5030 5010 4990 4970 4950 4930 4910 4890 4870 4850 4830 4810 4790 4770 4750 4730 4710 4690 4670 4650 4630 4610
Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5
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No 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650
X 4590 4570 4550 4530 4510 4490 4470 4450 4430 4410 4390 4370 4350 4330 4310 4290 4270 4250 4230 4210 4190 4170 4150 4130 4110 4090 4070 4050 4030 4010 3990 3970 3950 3930 3910 3890 3870 3850 3830 3810 3790 3770 3750 3730 3710 3690 3670 3650 3630 3610
Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5
No 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700
X 3590 3570 3550 3530 3510 3490 3470 3450 3430 3410 3390 3370 3350 3330 3310 3290 3270 3250 3230 3210 3190 3170 3150 3130 3110 3090 3070 3050 3030 3010 2990 2970 2950 2930 2910 2890 2870 2850 2830 2810 2790 2770 2750 2730 2710 2690 2670 2650 2630 2610
Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5
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No 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750
X 2590 2570 2550 2530 2510 2490 2470 2450 2430 2410 2390 2370 2350 2330 2310 2290 2270 2250 2230 2210 2190 2170 2150 2130 2110 2090 2070 2050 2030 2010 1990 1970 1950 1930 1910 1890 1870 1850 1830 1810 1790 1770 1750 1730 1710 1690 1670 1650 1630 1610
Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5
No 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800
X 1590 1570 1550 1530 1510 1490 1470 1450 1430 1410 1390 1370 1350 1330 1310 1290 1270 1250 1230 1210 1190 1170 1150 1130 1110 1090 1070 1050 1030 1010 990 970 950 930 910 890 870 850 830 810 790 770 750 730 710 690 670 650 630 610
Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5
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No 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850
X 590 570 550 530 510 490 470 450 430 410 390 370 350 330 310 290 270 250 230 210 190 170 150 130 110 90 70 50 30 10 -10 -30 -50 -70 -90 -110 -130 -150 -170 -190 -210 -230 -250 -270 -290 -310 -330 -350 -370 -390
Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5
No 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900
X -410 -430 -450 -470 -490 -510 -530 -550 -570 -590 -610 -630 -650 -670 -690 -710 -730 -750 -770 -790 -810 -830 -850 -870 -890 -910 -930 -950 -970 -990 -1010 -1030 -1050 -1070 -1090 -1110 -1130 -1150 -1170 -1190 -1210 -1230 -1250 -1270 -1290 -1310 -1330 -1350 -1370 -1390
Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5
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No 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950
X -1410 -1430 -1450 -1470 -1490 -1510 -1530 -1550 -1570 -1590 -1610 -1630 -1650 -1670 -1690 -1710 -1730 -1750 -1770 -1790 -1810 -1830 -1850 -1870 -1890 -1910 -1930 -1950 -1970 -1990 -2010 -2030 -2050 -2070 -2090 -2110 -2130 -2150 -2170 -2190 -2210 -2230 -2250 -2270 -2290 -2310 -2330 -2350 -2370 -2390
Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5
No 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000
X -2410 -2430 -2450 -2470 -2490 -2510 -2530 -2550 -2570 -2590 -2610 -2630 -2650 -2670 -2690 -2710 -2730 -2750 -2770 -2790 -2810 -2830 -2850 -2870 -2890 -2910 -2930 -2950 -2970 -2990 -3010 -3030 -3050 -3070 -3090 -3110 -3130 -3150 -3170 -3190 -3210 -3230 -3250 -3270 -3290 -3310 -3330 -3350 -3370 -3390
Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5
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No 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050
X -3410 -3430 -3450 -3470 -3490 -3510 -3530 -3550 -3570 -3590 -3610 -3630 -3650 -3670 -3690 -3710 -3730 -3750 -3770 -3790 -3810 -3830 -3850 -3870 -3890 -3910 -3930 -3950 -3970 -3990 -4010 -4030 -4050 -4070 -4090 -4110 -4130 -4150 -4170 -4190 -4210 -4230 -4250 -4270 -4290 -4310 -4330 -4350 -4370 -4390
Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5
No 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100
X -4410 -4430 -4450 -4470 -4490 -4510 -4530 -4550 -4570 -4590 -4610 -4630 -4650 -4670 -4690 -4710 -4730 -4750 -4770 -4790 -4810 -4830 -4850 -4870 -4890 -4910 -4930 -4950 -4970 -4990 -5010 -5030 -5050 -5070 -5090 -5110 -5130 -5150 -5170 -5190 -5210 -5230 -5250 -5270 -5290 -5310 -5330 -5350 -5370 -5390
Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5
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No 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150
X -5410 -5430 -5450 -5470 -5490 -5510 -5530 -5550 -5570 -5590 -5610 -5630 -5650 -5670 -5690 -5710 -5730 -5750 -5770 -5790 -5810 -5830 -5850 -5870 -5890 -5910 -5930 -5950 -5970 -5990 -6010 -6030 -6050 -6070 -6090 -6110 -6130 -6150 -6170 -6190 -6210 -6230 -6250 -6270 -6290 -6310 -6330 -6350 -6370 -6390
Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5
No 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200
Name S<44> S<43> S<42> S<41> S<40> S<39> S<38> S<37> S<36> S<35> S<34> S<33> S<32> S<31> S<30> S<29> S<28> S<27> S<26> S<25> S<24> S<23> S<22> S<21> S<20> S<19> S<18> S<17> S<16> S<15> S<14> S<13> S<12> S<11> S<10> S<9> S<8> S<7> S<6> S<5> S<4> S<3> S<2> S<1> DUMMY DUMMY DUMMY G<320> G<318> G<316>
X -6410 -6430 -6450 -6470 -6490 -6510 -6530 -6550 -6570 -6590 -6610 -6630 -6650 -6670 -6690 -6710 -6730 -6750 -6770 -6790 -6810 -6830 -6850 -6870 -6890 -6910 -6930 -6950 -6970 -6990 -7010 -7030 -7050 -7070 -7090 -7110 -7130 -7150 -7170 -7190 -7210 -7230 -7250 -7270 -7290 -7350 -7370 -7390 -7410 -7430
Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5
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No 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250
X -7450 -7470 -7490 -7510 -7530 -7550 -7570 -7590 -7610 -7630 -7650 -7670 -7690 -7710 -7730 -7750 -7770 -7790 -7810 -7830 -7850 -7870 -7890 -7910 -7930 -7950 -7970 -7990 -8010 -8030 -8050 -8070 -8090 -8110 -8130 -8150 -8170 -8190 -8210 -8230 -8250 -8270 -8290 -8310 -8330 -8350 -8370 -8390 -8410 -8430
Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5
No 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300
X -8450 -8470 -8490 -8510 -8530 -8550 -8570 -8590 -8610 -8630 -8650 -8670 -8690 -8710 -8730 -8750 -8770 -8790 -8810 -8830 -8850 -8870 -8890 -8910 -8930 -8950 -8970 -8990 -9010 -9030 -9050 -9070 -9090 -9110 -9130 -9150 -9170 -9190 -9210 -9230 -9250 -9270 -9290 -9310 -9330 -9350 -9370 -9390 -9410 -9430
Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5
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No 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350
X -9450 -9470 -9490 -9510 -9530 -9550 -9570 -9590 -9610 -9630 -9650 -9670 -9690 -9710 -9730 -9750 -9770 -9790 -9810 -9830 -9850 -9870 -9890 -9910 -9930 -9950 -9970 -9990 -10010 -10030 -10050 -10070 -10090 -10110 -10130 -10150 -10170 -10190 -10210 -10230 -10250 -10270 -10290 -10310 -10330 -10350 -10370 -10390 -10410 -10430
Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5
No 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362
Name G<14> G<12> G<10> G<8> G<6> G<4> G<2> DUMMY DUMMY DUMMY DUMMY DUMMY
X -10450 -10470 -10490 -10510 -10530 -10550 -10570 -10590 -10610 -10630 -10650 -10670 -10613 10613
Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 -468 -468
KEY_COG KEY_COG
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PRODUCT NOTICE
No part of this document may be copied or reproduced in any form without the prior written consent of Leadis Technology, Inc.
Leadis makes no representations or warranties with respect to the accuracy or completeness of the contents of this document. Leadis specifications and product descriptions are subject to change at any time without notice due to product improvements or other reasons. As a result, we recommend that customers contact Leadis for the latest product information before purchasing or using any Leadis product.
These materials are intended as a reference to assist our customers in the selection and application of Leadis products. These materials do not convey any license (express, implied or otherwise) under any intellectual property rights of Leadis or others. Leadis assumes no responsibility for any infringement of patents or other rights of third parties that may result from the use of these materials.
Except as set forth in Leadis Standard Terms and Conditions of Sale, Leadis assumes no liability, and disclaims any express or implied warranty, relating to its products, including, but not limited to, any implied warranties of merchantability, fitness for a particular purpose or noninfringement. Leadis products have not been designed, tested or manufactured for use in applications where the failure, malfunction or inaccuracy of the products carries a risk of death or serious bodily injury or damage to tangible property, including, but not limited to, nuclear facilities, aircraft navigation or communication, emergency systems, or other applications with a similar degree of potential hazard.
Please contact Leadis for further details on these materials or the products described herein.
2007 LEADIS Technology, Inc. All rights reserved. LEADIS and the LEADIS logo are trademarks of LEADIS Technology, Inc.
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LDS285

Feb. 27, 2007

240 (RGB) x 320 16M-Color TFT Driver

MPU INTERFACE ......................................................................................................................................10

DISPLAY DATA RAM (DDRAM)................................................................................................................26

5.3 5.4 5.5 5.6 5.7 5.8

LCD POWER GENERATION CIRCUIT.....................................................................................................61

5.10 POWER ON/OFF SEQUENCE..................................................................................................................71

240 (RGB) x 320 16M-Color TFT Driver

ADAPTIVE BCAKLIGHT CONTROL AND LED DRIVER CONTROL

LABC ( LIGHT ADAPTIVE BACKLIGHT CONTROL) ...............................................................................79

6.2 6.3 6.4

CABC ( CONTENT ADAPTIVE BACKLIGHT CONTROL)........................................................................82

CABC AND LABC .....................................................................................................................................83 LED DRIVER CONTROL ...........................................................................................................................84

INSTRUCTION CODE ...............................................................................................................................88

240 (RGB) x 320 16M-Color TFT Driver

RESET TABLE (DEFAULT VALUE) (TBD) .............................................................................................160

240 (RGB) x 320 16M-Color TFT Driver

INSTRUCTION SETUP FLOW ................................................................................................................161

CONNECTIONS WITH LCD PANEL .......................................................................................................188

EXAMPLE CONNECTION WITH PANEL (CASE11) ..............................................................................190

240 (RGB) x 320 16M-Color TFT Driver

CONNECTION EXAMPLE WITH EXTERNAL COMPONENTS .............................................................191

EXTERNAL COMPONENTS CONNECTION..........................................................................................193

10.3 PAD COORDINATES...............................................................................................................................198

240 (RGB) x 320 16M-Color TFT Driver

Document No: LTT285A-000

Prepared by: Sam_oh

240 (RGB) x 320 16M-Color TFT Driver

240 (RGB) x 320 16M-Color TFT Driver

240 (RGB) x 320 16M-Color TFT Driver

720 Source Buffer D/A Converter Level Shifter Data Latch

MTP System Clock Generator

P68 BS2, BS1, BS0 RESB CSB RDB WRB(D!C) DC(SCL)

ME_CMP SMX, SMY SRGB, SINV, EXTC LED_CNT

PADB0 to PADB4 PADA0 to PADA4

240 (RGB) x 320 16M-Color TFT Driver

Driver output pins S1 to S720 O G1 to G320 O Power supply pins

240 (RGB) x 320 16M-Color TFT Driver

Pin Description (continued)

240 (RGB) x 320 16M-Color TFT Driver

Pin Description (continued)

Name Type Host interface pins P68,BS2,BS1, I BS0 RESB I

WRB (RW) (D/!C)

240 (RGB) x 320 16M-Color TFT Driver

Pin Description (continued)

Name Mode Select SRGB SINV SMX SMY EXTC

240 (RGB) x 320 16M-Color TFT Driver

Pin Description (continued)

240 (RGB) x 320 16M-Color TFT Driver

Interface Type Selection

Pin Connection according to the Interface Type

240 (RGB) x 320 16M-Color TFT Driver

S: Start data tranamission P: Stop data tranamission TB: tranamission byte

Command1 code is interrupped by command2

Write interrupt sequence

240 (RGB) x 320 16M-Color TFT Driver

8080-Series Parallel Interface (P68 = "L")

8080-series RDB WRB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

240 (RGB) x 320 16M-Color TFT Driver

8080-Series parallel bus protocol, write to register or display DDRAM

240 (RGB) x 320 16M-Color TFT Driver

Read display RAM data