2005-IfX-Muenker-Spurious Sidebands Phase Noise Basics 20051220

Phase Noise and Spurious Sidebands in Frequency Synthesizers
Christian M nker u
i=0 0.8 i=1 0.6 i=2 i=3 0.4
0.2 J (x)
i
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0.4
0.6 10 8 6 4 2 0 x 2 4 6 8 10
Version 3.2 December 20, 2005 Muenker@ieee.org
Christian M nker u
Phase Noise and Spurious Sidebands in Frequency Synthesizers v3.2
December 20, 2005
Contents
I
1 2
PLL Basics
Introduction Around The Loop in a Day 2.1 Basic PLL Theory . . . . . . . . . . . . . . . . . . . . 2.1.1 A Linear Model for the PLL? . . . . . . . . . 2.1.2 Excess Phase . . . . . . . . . . . . . . . . . . 2.1.3 A linear model! . . . . . . . . . . . . . . . . . 2.2 Type I PLLs (Averaging Loop Filter) . . . . . . . . . . 2.2.1 Type I, second order PLL . . . . . . . . . . . . 2.2.2 Time Domain . . . . . . . . . . . . . . . . . . 2.2.3 Frequency Domain . . . . . . . . . . . . . . . 2.2.4 Type I, second / third order PLL, with one zero 2.3 Type II PLLs (Integrating Loop Filter) . . . . . . . . . 2.3.1 Type II, second order PLL . . . . . . . . . . . 2.3.2 Frequency Response . . . . . . . . . . . . . . 2.3.3 Type II, third order PLL . . . . . . . . . . . . 2.3.4 Dual Path Loop Filters . . . . . . . . . . . . . 2.4 Comparison of Type I and Type II PLLs . . . . . . . . 2.4.1 Type I PLLs (Averaging Loop Filter) . . . . . 2.5 Loop Filter Impedance . . . . . . . . . . . . . . . . . 2.5.1 Averaging Loop Filter . . . . . . . . . . . . . 2.5.2 Integrating Loop Filter . . . . . . . . . . . . . 2.6 Post-Filter and Higher Order PLLs . . . . . . . . . . . 2.6.1 Attenuation of Reference Frequency . . . . . . PLL Building Blocks 3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Phase Detector . . . . . . . . . . . . . . . . . . . . . 3.2.1 Analog Multiplier (Type 1 PD) . . . . . . . . . 3.2.2 EXOR (Type 2 PD) . . . . . . . . . . . . . . . 3.2.3 EXOR + FD (Perrott) . . . . . . . . . . . . . . 3.2.4 JK Flip-Flop (Type 3 PD) . . . . . . . . . . . 3.2.5 Tristate PFD (Type 4 PD) . . . . . . . . . . . 3.2.6 Hogges Phase Detector . . . . . . . . . . . . 3.2.7 (Modied) Triwave Phase Detector . . . . . . 3.3 Charge Pumps . . . . . . . . . . . . . . . . . . . . . . 3.3.1 Single Ended Designs . . . . . . . . . . . . . 3.3.2 The Dead Zone and How to Get Around It . . . 3.3.3 Charge Pumps and Two-State Phase Detectors 3.4 Loop Filter . . . . . . . . . . . . . . . . . . . . . . . 3.5 Divider . . . . . . . . . . . . . . . . . . . . . . . . . 3
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CONTENTS
3.6
3.5.1 3.5.2 3.5.3 3.5.4 VCO .
Dual Modulus Prescaler Multi Modulus Divider . High-Speed Flip Flops . Synchronization . . . . . . . . . . . . . . . . . .
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47 49 51 51 51 53 55 56 56 58 59 63 63 65 65 66 68 68 69 69 70 73 73 73 73 74 75 75 78
4 Fractional-N PLLs 4.1 First Order Fractional-N PLLs . . . . . . . . . . . . . . . . 4.2 Higher Order Fractional-N PLLs . . . . . . . . . . . . . . . 4.2.1 Sampling and Quantization . . . . . . . . . . . . . . 4.2.2 Delta Modulation . . . . . . . . . . . . . . . . . . . 4.2.3 Principle of Sigma-Delta Modulation (SDM) . . . . 4.2.4 Different Architectures for Sigma-Delta Modulators 4.2.5 Performance Comparison . . . . . . . . . . . . . . . 5 PLL Modeling and Simulation 5.1 Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.1 Bilinear Transform . . . . . . . . . . . . . . . . . 5.1.2 1st Order Low Pass . . . . . . . . . . . . . . . . . 5.1.3 2nd Order Low Pass . . . . . . . . . . . . . . . . 5.1.4 Third Order Low Pass . . . . . . . . . . . . . . . 5.1.5 Integrating Loop Filters . . . . . . . . . . . . . . 5.1.6 Loop Filter Modeling in VHDL . . . . . . . . . . 5.1.7 Loop Filter Modeling Using Exponential Functions 5.2 VCO Modeling . . . . . . . . . . . . . . . . . . . . . . . 5.3 Accuracy Limitation of Sampled / Quasi-Analog Models . 5.3.1 Amplitude Quantization . . . . . . . . . . . . . . 5.3.2 Timing Quantization . . . . . . . . . . . . . . . . 5.4 Noise Modeling . . . . . . . . . . . . . . . . . . . . . . . 5.4.1 Event Driven Approach . . . . . . . . . . . . . . . 5.5 Spectral Estimation of Simulation Results . . . . . . . . .
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II Spurious Sidebands
6 Reference Frequency Feedthrough 6.1 FM / PM Modulation Basics . . . . . . . . . . . . . . . 6.2 Sinusoidal Disturbance of Tuning Voltage . . . . . . . . 6.3 Periodic Disturbances of Tuning Voltage . . . . . . . . . 6.4 Sidebands Induced By DC Leakage Current . . . . . . . 6.5 Narrow Pulses on the Tuning Voltage . . . . . . . . . . . 6.6 The Magical Mystery Spur: Dividing Spurious Sidebands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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83 83 85 87 88 90 95 97 98 98 101 101 102 103 104 105 106 107
7 Other Sources of Spurious Sidebands 7.1 Spurious Sidebands Depending on the Output Frequency ( -Spurs) . . 7.1.1 RF Leakage Into the System Frequency Path . . . . . . . . . . 7.2 Spurious Sidebands Depending on the VCO Frequency ( -Spurs) . . . 7.2.1 VCO / LO Leakage Into the System / Reference Frequency Path 7.2.2 System Frequency Harmonics Spurious . . . . . . . . . . . . . 7.2.3 Fractional-N Spurs . . . . . . . . . . . . . . . . . . . . . . . . 7.3 Spurious Sidebands Tracking the Carrier ( -Spurs) . . . . . . . . . . . 7.3.1 Reference Frequency Modulating the VCO . . . . . . . . . . . 7.3.2 System Frequency Modulating the VCO . . . . . . . . . . . . . 7.3.3 Reference / System Frequency Modulating the LO Distribution
Christian M nker u Phase Noise and Spurious Sidebands in Frequency Synthesizers v3.2
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December 20, 2005
CONTENTS
7.4 8
7.3.4 LF Injection into the System Frequency Path . . . . . . . . . . . . . 108 Intermodulation Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Spurious of Fractional-N PLLs 111 8.1 Spurious Sidebands of First Order Fractional-N PLLs . . . . . . . . . . . . . 111
III Phase Noise and Jitter

9 Phase Noise and Jitter 9.1 Jitter . . . . . . . . . . . . . . . . . . . . . . . . 9.1.1 Jitter of Driven Systems (PM Jitter) . . . 9.1.2 Jitter of Autonomous Systems (FM Jitter) 9.2 Jitter Measures . . . . . . . . . . . . . . . . . . 9.2.1 Cycle Jitter (or Cycle-to-Cycle Jitter) . . 9.2.2 Period Jitter . . . . . . . . . . . . . . . . 9.2.3 Long-Term Jitter . . . . . . . . . . . . . 9.2.4 Accumulated Jitter . . . . . . . . . . . . 9.2.5 Absolute Jitter . . . . . . . . . . . . . . 9.2.6 Allen-Variation . . . . . . . . . . . . . . 9.3 Phase Error . . . . . . . . . . . . . . . . . . . . 9.4 Phase Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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117 117 117 118 118 118 118 119 119 119 119 119 120 123 123 125 127 127 129 132 132 132
10 Noise In The PLL 10.1 Noise Transfer Properties of the PLL . . . . . . 10.1.1 The Famous PLL Noise Formula . . . . 10.2 Noise Contributors in the PLL . . . . . . . . . 10.2.1 Divider Noise . . . . . . . . . . . . . . 10.2.2 Phase Detector and Charge Pump Noise 10.2.3 Reference Noise . . . . . . . . . . . . 10.2.4 VCO Noise . . . . . . . . . . . . . . . 10.2.5 Noise of Loop Filter Resistors . . . . .
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IV
Related Fields
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11 Modulation and Demodulation 139 11.1 Digital Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 11.2 Digital Demodulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
The Toolbox
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143 143 144 145 146 149 149 149 150 151
A Fourier and Laplace Analysis and Synthesis A.1 Fourier Series . . . . . . . . . . . . . . . A.2 Fourier Integral . . . . . . . . . . . . . . A.3 Discrete / Fast Fourier Transform . . . . . A.4 Some Fourier Transformations . . . . . . B Noise B.1 Statistical Terms . . . . . B.2 Thermal Noise . . . . . B.3 Flicker Noise (1/f Noise) B.4 Shot Noise . . . . . . . .
Christian M nker u
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December 20, 2005
CONTENTS
B.5 Bandlimited Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 C Switching and Sampling C.1 Switched Signals . . . . . . . . . . C.2 Sampled Signals . . . . . . . . . . . C.3 Switched (Cyclostationary) Noise . C.4 Intermodulation of Two Frequencies C.5 Clipped Signals . . . . . . . . . . . D FM / PM Signals D.1 Sinusoidal Modulation Signals . D.2 Periodic Modulation Signals . . D.3 Phase / Frequency Shift Keying . D.4 Statistical Modulation Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 153 154 154 158 159 161 161 162 164 164 167 167 167 168 168 169 169 169 170
E Signal Energy and Power E.1 The Basics: Energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . E.2 The Basics: Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . E.3 Power of a Periodic Signal . . . . . . . . . . . . . . . . . . . . . . . . E.3.1 Calculation of Signal Power in the Time Domain . . . . . . . . E.3.2 Calculation of Signal Power from the Auto-Correlation Function E.3.3 Calculation of Signal Power in the Frequency Domain . . . . . E.4 Power of Statistical Processes . . . . . . . . . . . . . . . . . . . . . . . E.5 Power of FM / PM Modulated Signals . . . . . . . . . . . . . . . . . .
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F Second Order (PT2) Approximation 173 F.1 Basic PT2 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 F.2 PT2 System with a Zero . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 G Bits and Pieces G.1 Normal Distribution and Error Function G.2 Bessel Functions . . . . . . . . . . . . G.3 Trigonometric Theorems and Identities . G.4 Quadratic Equation . . . . . . . . . . . G.5 Differentials and Integrals . . . . . . . H Variable and Acronym Denitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 177 180 181 182 183 185
Christian M nker u
December 20, 2005
CONTENTS
Preface
The most exciting phrase to hear in science, the one that heralds new discoveries, is not Eureka! (I found it!) but Thats funny... Isaac Asimov The purpose of computing is insight, not numbers. R.W. Hamming, Numerical Methods for Engineers and Scientists.
The spark which started off this script was a commercial, three day course on PLLs which I attended back in the year 2000. The material of the course was so badly organized and contained so many errors that I grew angry and thought I can do better than that!. It turned out that this was not so easy to achieve but I tried to write down the basics, little secrets and the dirty tricks of PLL design while learning them myself. In the beginning I did this to structure the complex material for myself, later on colleagues got interested and now the basic theory chapters also serve as a compendium for students attending my PLL lectures. My goal of working as an engineer always is to boil problems down to a level of complexity where it can be tackled using back-of-the-envelope formulas. True, sometimes the envelope has to be quite large, but I still believe in the old GIGO mantra: garbage in, garbage out. Running complex simulations without understanding the basic mechanisms and model limitations gives very accurate results - for a different reality. In a way, the power of modern simulation tools and computers leads to less understanding because you are no longer forced to work out the core of the problem manually. Of course, computer simulations have become an essential part of PLL design. But before ring up the simulator, you should nd a simulation methodology with a suitable level of abstraction and simplication. Some theoretical background helps to decide whatever is suitable for a given system. And after the simulation, results should be checked for plausibility on the back of the famous envelope. Therefore, the chapter on PLL modeling will be extended in the near future. This script is a work-in-progress with lots of loose ends, nevertheless I hope it will help you to get in loop. Feedback (Muenker@ieee.org) is most welcome! Munich, February 2005, Christian M nker u
Christian M nker u
December 20, 2005
CONTENTS
Christian M nker u
December 20, 2005
Part I
PLL Basics
Chapter 1
Introduction
It aint necessarily so... George Gershwin
Frequency synthesizers are among the most critical components of modern communication systems. They create the local oscillator (LO) signal that serves as the RF carrier to transmit data over the air or some kind of wire-bound interface and to mix the received signal back down into the baseband domain. Frequency synthesis is usually achieved using some kind of phase locked loop (PLL) which locks the signal of a high frequency oscillator to the signal of a stable reference oscillator with a selectable frequency ratio. In the future, direct digital synthesis (DDS) and RF analog-to-digital converters (ADCs) combined with advanced digital signal processing will nd their way into more RF systems due to their superior channel switching speed and reproducibility. Nowadays, these methods are still too power hungry and expensive for most consumer wireless applications, therefore only PLLs are treated here. An ideal carrier signal would be a pure sinusoid, showing a single spectral line. In reality, there are always random noise and other disturbances, corrupting the signals. In the time domain, these disturbances show as jitter which e.g. reduces the data eye of a clock and data recovery unit. In the frequency domain, noise broadens the signal spectrum, i.e. the carrier now has a frequency distribution instead of one single line. It also shows as a noise oor, far away from the carrier. Additionally, there may be discrete sidebands of the carrier, caused by some periodic disturbance signal. These lines are called spurious sidebands (g. 1.1).
Vctrl + v e
V
ctrl
|Svco(f)|
Tref
f0f ref
f0
f0+f ref
Figure 1.1: Disturbance of the VCO control voltage producing phase noise and spurious sidebands on the VCO output
11
12
Introduction
Spectral purity has become very important as more and more network subscribers are being tucked into the limited number of frequency channels, making bandwidth a valuable resource that may not be wasted by spurious emissions. In order to use this resource most effectively, frequency synthesizers have to fulll ever increasing demands: Fast settling time: GSM and some other communications standards use frequency division duplexing (FDD) / time division multiple access (TDMA) which require changing frequencies between every receive and transmit slot. For optimum usage of time and frequency slots, this frequency hopping has to be as fast and smooth as possible. Low phase noise: Wide band noise from the local oscillator can leak into other frequency channels during transmission, disturbing other subscribers. While receiving, local oscillator wide band noise can mix large signal disturbances down into the target channel, desensitizing the receiver. Noise within the channel bandwidth is also unwanted because it increases the bit error rate (BER) for both receive and transmit case. Low spurious sidebands: Unwanted sidebands of the receive / transmit center frequency have similar effects as noise. Low power: Portable devices have only limited energy supplies, frequency synthesizers have to save power just like other building blocks. These requirements have to be fullled with less (and less expensive) components in short design cycles to be competitive. However, phase locked loops are complex building blocks that are hard to analyze in a strictly mathematical way and hard to simulate. This tutorial tries to bridge the gap between precise computer simulations, giving little insight into system mechanisms, and between hand-waving simplications allowing only qualitative answers based on questionable assumptions. Currently, there is little material available covering the aspects of spurious sidebands and phase noise generation in PLLs in depth while still keeping an engineering point of view:, complexity must be reduced to achieve an understanding of the system that allows making the right design choices in a short time without losing too much accuracy. Part I reviews some PLL basics needed for the following analyses: chapter 2 takes a walk round the loop and looks at PLLs from a control theory point of view, with the focus on different loop lter architectures and their inuence on settling time etc. A novel approach is presented for approximating the inuence of the loop lter on spurious and phase noise performance that will be used throughout this tutorial. Chapter 3 covers the building blocks of a PLL like phase detector, VCO etc. and their inuence on system behavior. Part II looks at the mechanisms of spurious sideband generation: chapter 6 starts with a little modulation theory to explain how low frequency disturbances in the system can create spurious sidebands in the radio frequency domain. Some typical examples of real-life disturbances are analyzed, leading to simple equations that allow making intelligent design decisions. Chapter 7 gives an overview of different disturbance mechanisms in PLLs, going a little further into the details of practical PLL design. In chapter 8, the specialties of fractional-N PLLs concerning spurious generation are analyzed. Part III deals with noise in PLLs: After an introduction to the concepts of phase noise and jitter in chapter 9, chapter 10, covers the noise mechanisms in different blocks and their contribution to the overall PLL noise. Finally, Part IV is as a kind of toolbox with some of the mathematical tools needed for PLL analysis: Fourier analysis, noise and modulation theory etc. are explained in greater detail than in the main parts.
Christian M nker u Phase Noise and Spurious Sidebands in Frequency Synthesizers v3.2 December 20, 2005
Chapter 2
Around The Loop in a Day

Wichtig ist, was hinten raus kommt. H. Kohl
Overview: This chapter gives an introduction to PLL behavior from a signal / control theory point of view. A simple, linear model is used to develop concepts like bandwidth, phase margin and settling time. The focus is on the different behavior for PLLs containing one or two integrators (type I / type II). Finally, an approximation for loop lter transimpedance is derived that makes PLL analysis in the frequency domain easier.
2.1 Basic PLL Theory

2.1.1 A Linear Model for the PLL?
Essentially, a PLL is a strongly non-linear system, especially during the lock-in process. Time-domain analysis is required to treat design problems like capture range or jitter suppression. Simulations in the time domain are tedious, mathematical analysis is very difcult if not impossible. This makes small-signal analysis - i.e. regarding the frequency response - a desirable alternative: It gives valuable informations concerning loop stability (phase margin) and bandwidth, settling time or noise transfer of a system. This is especially interesting for systems which have to fulll requirements concerning spectral purity like frequency synthesizers for wireless applications. The main advantage of small-signal analysis (as usual) are its simplicity and speed, allowing back-of-the-envelope calculations and fast design optimizations. However, it requires a linear time-invariant (LTI) system - which a PLL (as initially stated) clearly isnt. Still, the benets of this analysis are so dramatic that a lot of bold simplications are made just to run this analysis on a PLL: The signal frequencies at both inputs of the phase detector are the same. In reality, this is only true when the PLL is in or near lock. Having only one frequency in the system1
1 PLLs
with a divider by N can also be treated as well see soon.
13
14
allows using the concept of phase and of complex frequencies. The reference frequency is at least 10 times higher than the PLL bandwidth. This allows aproximating the discrete-time blocks (phase detector, divider) as time-continous blocks. The changes in phase difference at the phase detector are so small that the building blocks behave in a linear way. When the phase difference approaches or 2 (depending on the PD) the transfer function may become very non-linear and nally even non-monotonous. That settled, well develop a linear model with simple behavioral models that predicts the main dynamic features of a PLL. The different building blocks of a PLL will be discussed in detail in chapter 3. A more in-depth treatment of loop dynamics can be found in [Gar79], [Bes98], [Roh97, pp. 1 - 78].
2.1.2
Excess Phase
Under these assumptions, signals in the loop are nearly periodic, i.e. periodic with a phase modulation e (t): s(t) = A cos (0t + e (t)) The total phase of the signal s(t) is (2.1.1)
0 (t) = 0t + e (t)
(2.1.2)
As we assumed that the signals in the PLL have a constant frequency, the phase component 0t merely rises in a linear way with time. This is somewhat boring and predictable - we are more interested in deviations from this linear behavior: the deviation is called excess phase e (t). That is also the part the PLL operates on: The phase detector calculates the difference between reference phase and divided VCO phase. If both signals have the same frequency (which we have assumed), the linear phase term will cancel out:
(t) =
= e,re f (t) e,div (t) = e (t)
0t + e,re f (t) 0t + e,div (t)
(2.1.3)
From now on, when talking of reference phase, VCO phase etc. we will actually mean their excess phase. Note: Altough we have assumed a constant and common frequency in the system, the instantanous total (angular) frequency of the signal s(t) in (2.1.1) is
(t) = 0 +
e (t) t . = (t)
e
(2.1.4)
where the second part could be dened as excess frequency.

15
2.1.3
A linear model!
With the exception of the loop lter well just use a simple behavioral model of the building blocks in this chapter - lets start with the phase detector (PD). We dont care about the implementation, it might be an analog or a digital type, with or without a charge pump it has two inputs for reference and (divided) VCO phase and an output whose average is proportional to the phase difference of its two inputs. Thats all for the moment! The equation describing PD behavior is deceivingly simple: VPD,out (t) = K re f (t) div (t) = K e (t) (2.1.5)
The output of the phase detector is usually a voltage that pulses with the reference frequency. We are only interested in slowly changing processes and regard its slowly changing average voltage. From a system point of view, nobody will notice that we are cheating a little because the loop lter does exactly this job - smoothing and averaging the phase detector output. The proportionality factor K is called phase detector gain. In 2.1.5 we have silently assumed that the PD has a voltage output - that is not necessarily so, it is only important that PD, loop lter and VCO t together. In the frequency domain, the model is equally simple: VPD,out (s) = K re f (s) div (s) = K e (s) (2.1.6)
Again, VPD,out (s) is the average PD detector voltage in the complex frequency domain. Next in line is the loop lter - it has to be a low-pass lter, otherwise the loop wont become stable. Depending on system and requirements, the loop lter transfer function F(s) may include one pole at the origin (integrator), some other poles and z zero(s) in the transfer function. z must be less than the total number of poles pLF of the lter (otherwise it wouldnt be a low-pass ...). In general, the transfer function of such a low-pass can be written as F(s) = KF (s + sz,1 )(s + sz,2 ) (s + sz,z ) (s + s p,1 )(s + s p,2 ) (s + s p,p ) z< p (2.1.7)
In most PLL applications, the number of zeros z is 0 or 1, the number of poles p is rarely higher than 3. The loop lter gain constant KF can have the dimension 1 (e.g. voltage in, voltage out), but it may as well have the dimension of a transimpedance - current from the charge pump is converted into a control voltage for the VCO. The Voltage Controlled Oscillator (VCO) has an output frequency vco that depends on the control voltage vctrl (t) at its tuning input2 . In our simple model, the VCO is characterized by two constants: its free running frequency FR determines the output frequency when the tuning voltage is zero. The gain factor Kvco describes how much the tuning voltage changes the output frequency:
vco = FR + Kvco vctrl (t)
(2.1.8)
We are more interested in the output phase of the VCO than in its frequency which can be derived by integrating its frequency: Vctrl (s) vco (s) = Kvco (2.1.9) s s The loop gain factor KO is the product of phase detector, loop lter and VCO gain factors, K KF and Kvco : (s) =
2 There
are Current Controlled Oscillators (CCOs) as well.
Christian M nker u
December 20, 2005
16
. KO = K KF Kvco
(2.1.10)
The last block is the divider, which - per denition - divides the VCO frequency by N. This block is only needed for frequency synthesis applications, it makes no sense for clock and data recovery or skew reduction applications. Phase is also divided by N as its the integral of frequency.
div (t) = vco (t)/N div (t) = vco (t)/N
(2.1.11) (2.1.12)
Now lets put the blocks together: Figure 2.1 shows a block diagram of a PLL, g. 2.2 its control theory equivalent.
Phase Detector / Charge Pump

ref + ref i = 0 N PD + CP
Loop Filter
F(s)
VCO
0+ 0
Divider
cut here to open loop
1 N
0 , 0
Figure 2.1: PLL block diagram
ref
vco, vco G(s)
div= vco N
PD / CP / LF / VCO Divider H(s)
Figure 2.2: PLL block diagram - control theory point of view Usually, the reference phase re f is regarded as the input and the VCO phase vco as the output signal of a PLL (g. 2.1). Then, the forward gain G(s) (no feedback path) is dened by G(s) =
0 (s) Kvco = K F(s) e (s) s
(2.1.13)
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17
As the VCO is an integrator with regard to its output phase, there is an 1/s term in the open loop gain (pole at the origin). The feedback transfer function H(s) is dened by the divider ratio N H(s) = div (s) = 1/N vco (s) (2.1.14)
The product of forward and feedback transfer function is the open loop gain GH(s) (open feedback path) of the system as GH(s) = K Kvco F(s) div (s) = re f (s) Ns (2.1.15)
As the loop lter transfer function F(s) has to be a low-pass function, the open loop gain GH(s) also has a low pass characteristic. Its order p - which is also the order of the PLL is the total number of poles in the open loop transfer function GH(s). It is equal to the order of the low pass lter pLF plus one due to the VCO acting as an integrator. If the loop lter contains another integrator, the PLL is called a Type II PLL. A normal loop lter without integrator gives a Type I PLL - and there is no such thing as a Type III PLL because systems with more than two poles at the origin (=integrator) are always unstable. Even Type II PLLs have an open loop phase shift of 180 at low frequencies and must be stabilized by introducing a zero (which brings the phase back down) in the loop. Now we close the loop and look at the closed loop tranfer function T (s): T (s) = vco (s) G(s) KO F(s) = = re f (s) 1 + GH(s) s + KO F(s)/N (2.1.16)
First, we look at the frequency domain and do a straight line approximation to get a feel for the PLL behavior. The frequency where the magnitude of the open loop gain becomes one, |GH( j )| = 1, is called open loop bandwidth or unity gain frequency fc . fc is an important parameter in PLL (and most other control systems) design. It is also roughly the frequency where the magnitude of the closed loop gain starts dropping. The sampled principle of digital PLLs introduces an additional delay of approx. 1/2 fre f which deteriorates the phase margin near the reference frequency. Therefore, the phase detector reference frequency fre f has to be signicantly higher than fc . N |G( j )| (c / )
pz
|T ( j )|
for for
c [|GH( j )| c [|GH( j )|
1] 1]
This shows that all PLLs have roughly the same kind of closed loop transfer function (g. 2.3): up to the open loop bandwidth fc , the open loop gain |GH(s)| 1 and the closed loop gain T (s) is only determined by the division ratio N in the feedback path. Changes of the reference phase appear multiplied by the divider ratio at the output. This is very similiar to an OP-AMP circuit whose behaviour only depends on the feedback network up to a certain frequency. At frequencies above fc (outside the loop bandwidth), the feedback loop is no longer effective (|GH(s)| 1) and the transfer function is only determined by the forward gain function G(s). In this frequency range, the PLL behaves like a lowpass of order p z, the closed loop transfer function drops with (p z) 20 dB/dec. At frequencies around fc , |T ( j )| may exhibit peaking, depending on the phase margin.
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December 20, 2005
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log |C(j )| log N 3dB f 3dB B f n

Figure 2.3: Closed loop gain |T ( j )| and noise bandwidth Bn
The -3dB bandwidth B3dB = f p of the closed loop gain is a very important parameter, it species the maximum change rate of the reference signal the PLL output still can follow. In frequency synthesis applications, the reference frequency usually isnt changed or modulated, here f p gives the bandwidth for noise components on the reference signal to inuence the PLL output. A lower bandwidth gives a better reference noise suppression. The -3dB bandwidth is dened as the frequency where . |T ( j )| = |T (0)|/ 2 = N/ 2 (2.1.17)
It also gives the maximum frequency up to which noise from the VCO is suppressed by the control loop operation - for this noise component, a smaller bandwidth means worse noise performance (see chapter 10 for details). In general, it is not so easy to determine the closed loop behaviour from the open loop transfer function. For a well behaved system with reasonable phase margin, open and closed loop bandwidth are approximately equal, fc f p . fc = f p when T (s) is a second order system with a phase margin of 45 . For synthesizer applications, the systems noise bandwidth Bn of the PLL is very important: Bn = 1 2
0
|T ( j )|2 d N2
(2.1.18)
Bn is the equivalent brick-wall bandwidth (see B.5) of the system for noise being added at 2 the reference input (re f ). Bn allows a quick calculation of the output phase noise no of a PLL if the dominant noise contribution comes from the PD inputs (reference, divider & PD noise) and has a at noise power spectral density N0 :
2 no = Bn
N0 2 N Ps
(2.1.19)
where Ps is the signal power at the PLL output. For most applications, PLLs (and other control systems as well) can be approximated by a second order system (appendix F) which is well known in control and system theory. This allows calculating the bandwidth, settling time, amount of peaking etc. in closed form without a great loss of accuracy, e.g. T (s) = N 2 s2 /n + 2( s/n ) + 1 (2.1.20)
where n is the eigenfrequency of the closed loop and is the damping ratio. Depending on the PLL type, the denominator may have a zero. The transient behaviour (F.1.4) depends
2.2 Type I PLLs (Averaging Loop Filter)
19
strongly on the damping ratio : For = 0, the two poles of T (s) sit on the imaginary axis and the system shows undamped oscillations at the frequency n . Increasing the damping ratio lets the poles wander towards the negative real axis on an arc (conjugate complex poles). In the time domain, this corresponds to an exponentially damped sinusoidal signal. Increasing reduces the overshoot and also the frequency of the ringing (g. 2.8). For > 1, the system is overdamped; its step response will be an exponential decay with two time constants. In the PLL world, the step response (F.1.4) describes the PLL frequency response when the reference frequency or the divider ratio makes a jump.

The most simple version of a PLL is one with a simple RC (rst order) lter. This lter averages the output of the phase detector (PD). This lter adds a pole to the open loop transfer function but no integrator, therefore, we get a Type I, second order PLL. Lets have a look at the transfer function:
Open Loop Gain (dB)

0 dB
20db/dec
Phase
n
40db/dec
0 90
m
60db/dec
180
1 c
log
Figure 2.4: Bode plot for open loop gain T ( j ) of type I, 2nd / 3rd order PLLs (no zero)
2.2.1
Type I, second order PLL

1 sT1 + 1 . with T1 = R1C1
The transfer function of a rst order loop lter (g. 2.5) is: F(s) = (2.2.1)
The open loop transfer function GH(s) becomes GH(s) = KO Ns (sT1 + 1) (2.2.2)
showing one pole at the origin and one at s = 1 = 1/T1 . The magnitude of the open loop gain transfer function is
20
to VCO VPD= ICPR1 PD PD/CP C1 C2 I CP= VPD / R1 R1 R2 R2
to VCO
C1 R1
C2
2nd pole 1st pole 1st pole
2nd pole
Figure 2.5: Averaging loop lters of 1st / 2nd order (no zero)
|GH(s)| =
KO KO = N ( j T1 ) N
2 T12 1
(2.2.3)
The closed loop transfer function becomes G(s) KO F(s) vco (s) s/1 +1 = = = re f (s) 1 + GH(s) s + KO F(s)/N s + N(s/KO +1)
1
KO
T (s) = = = s1,2
N KO N = 2 sN (s/1 + 1) + KO s N/(KO 1 ) + sN/KO + 1 N

2 s2 /n + 2( /n )s + 1
2 N n 2 + 2( )s + 2 s n n
(2.2.4) (2.2.5)
= n (
2 1) = n ( j
1 2)
using the familiar notation from control theory for a second order system (see appendix F):
Natural Frequency and Damping Ratio for a Type I PLL

KO 1 N 1 N n = 2KO 2
Natural Frequency : Damping :
. = . =
(2.2.6) N 1 KO (2.2.7)
Depending on n and , the output signal can be an exponential function, a damped sinusoid or an undamped oscillation. The natural frequency n is the geometric average of loop gain KO /N and corner frequency of the loop lter, 1 , i.e. some sort of gain-bandwidth-product. It determines the frequency of oscillation (if there is one). The damping ratio determines how much damping there is in the system. Here, it directly depends on the loop lter bandwidth and inversely on the loop gain KO /N - well see that this is an undesirable correlation.
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December 20, 2005
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When s 0, T (s) 1 which means the PLL tracks slow changes of the input phase. For fast changes (s ), T (s) 0, indicating that the PLL has a low-pass characteristic regarding the reference input. The inverse Laplace transform of (2.2.4) gives the impulse response vco, (t) of the PLL. Depending on the damping ratio , the response is an exponential function ( 1), an exponentially damped sinusoid (0 < < 1) or an undamped oscillation ( = 0). In praxis, nearly all well-designed PLLs have a of 0.3 . . . 0.9 because this gives the fastest settling time together with an acceptable overshoot (as well later see):
vco, (t) =
n e n t
12
sin
1 2 nt
for
0< <1
(2.2.8)
(2.2.5) shows what happens when you increase the loop gain GH(s): When KO /N = 0, n is zero and at innity. The roots of the closed loop transfer function T (s) are the same as the open loop poles, s1 = 0, s2 = 1 (try evaluating (2.2.5) ... (2.2.1) for the limit KO /N 0). Increasing KO /N moves the roots on the real axis until they meet in the middle at 1 /2 when = 1. From here on, the roots become complex and part from the real axis in a 90 angle, zeta decreases furtheron. This means, the pulse response of a type I, second order PLL becomes more oscillatory with increasing loop gain but never becomes unstable. The trajectory of the roots can be displayed in a so called root locus diagram (g. 2.6). (2.2.4) shows that the roots have a constant real part of 1 /2 and an imaginary part of 1 2 n for 0 < 1.
KO : 0 j = cos
n 1 2 1 RC n = 1 2
1 =
Figure 2.6: Root locus diagram for typ I, rst order PLL
2.2.2
Time Domain
Keep in mind that the following calculations are only correct as long |e (t)| < max which is the maximum phase error of the PD (usually /2 or , depending on the type of PD). Larger phase errors cause a cycle slip, i.e. the PD skips one cycle. Final Value: The nal value theorem of Laplace theory (2.2.9) allows to predict the settling behavior of a system:
22
Final Value Theorem

t
lim h(t) = lim sH(s)

s0
(2.2.9)
H(s) is the product of the stimulus and the system pulse response - H(s) could be the closed loop transfer function T (s) ( pulse response) or T (s)/s ( step response) etc. Now, lets have a look what happens when our rst order, type I PLL is treated with different stimuli: T (s) ; sk
lim h(t) = =
s0
lim s
k = 0, 1, 2, . . . N
s0
lim s1k
2 s2 /n + 2( /n )s + 1
What does this mean? A pulse disturbance of the input phase (k = 0) completely disappears at the VCO output after a while, a phase step (k = 1) at the input appears multplied by N at the output and a phase ramp (= frequency step, k = 2) leads to an innitely increasing phase at the VCO, i.e. a frequency change. This behavior is not surprising - it is exactly what a PLL is supposed to do - and well see that all PLLs behave in the same way. Step Response The case of step response is of special importance: T (s) = T (s) 1 N = 2 2 s s s /n + 2( /n )s + 1 (2.2.11)
0 N =
for k = 0 for k = 1 for k 2
(pulse response) (step response) (ramp response) (2.2.10)
For damping ratios between 0 and 1, the PLL will respond with an exponentially damped sinusoidal ringing: e n t 12 12
vco, (t) = 1
sin
1 2 nt + ; = tan1
for
0< <1
(2.2.12) Its time constant is = 1/ n = 2T1 , the ringing frequency is 1 2 n . The steady-state error ess of C (t) approaches zero for t which is good because this means that the phase error will be completely eliminated in the end. How long this settling takes is an important performance criterium: the settling time, Ts , is dened as the time required for the system to settle within a certain percentage of the input amplitude [Dor92, p. 164] (g. 2.7). Settling and rise time can be calculated easily by ignoring the sinusoidal component of (2.2.12):
Settling time and rise time for Type I PLL
Ts Tr
Christian M nker u
= ln( ) = 2 ln( )T1 = (ln 0.9 ln 0.1) 4.4T1
(10% 90%)
(2.2.13) (2.2.14)
December 20, 2005
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c (t)
Mp
Overshoot
1+ 1 0.9 Tr 1
ess
0.1 Tp Ts
Figure 2.7: Step response parameters: Overshoot, settling and steady-state error
The amount of phase error peaking or overshoot Mp, and the corresponding peak time Tp, can be obtained by calculating the maximum of (2.2.12) or the zero of (2.2.8). c(t) becomes zero when the sine function becomes zero, i.e. when nn t = . The maximum of vco, (t) occurs at n = 1:
Peaking time for Type I PLL

Tp, =
n
12
(2.2.15)
Now, the maximum can be calculated from (2.2.12):
Relative Maximum of Phase Error (Type I PLL)

Mp, = vco, (Tp ) = 1 + e

1 2
(2.2.16)
For many applications, it is important to regard the phase error e (t) = div (t) re f (t) at the input. We dene a phase error transfer function He (s) as: He,I (s) = = re f (s) div (s) e (s) = = 1 T (s)/N re f (s) re f (s) s2 + 2 n s 2 s2 + 2 n s + n (2.2.17)
and use our stimulus signals re f (s) = c/sk again for pulse, step and ramp input (k = 0, 1, 2). Well use the nal value theorem (2.2.9) once more
lim e (t) = =
s0
lim se (s) lim s1k s2 + 2 n s ; 2 s2 + 2 n s + n k = 0, 1, 2, . . .
s0
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December 20, 2005
24
0 0
2 N c = c KO n
for for for
k=0 k=1 k=2
2.2.18 shows that a phase pulse or a phase step at the input disappears after some time. The PLL as a control system gets rid of these disturbances. But what happens if the input of the PLL sees a frequency jump of = c (e.g. by a change in the reference frequency fre f or the division ratio N? In the phase domain, this is equivalent to a ramp function, e (t) = t. (2.2.18) predicts that the phase error will be different by cN/KO after the disturbance, an effect that creates problems for some applications.
2.2.3
Frequency Domain
In the frequency domain, the magnitude of the steady state response is |T ( j )| = N

2 (1 2 /n )2 + (2 /n )2
(2.2.19)
n is the geometric mean of the open loop gain KO /N and the -3dB frequency of the LPF (1/T1 = 1 ), i.e. it sort of indicates the Gain-Bandwidth product of the loop. denes the damping, i.e. how much overshoot and ringing the transient response has. Figure 2.8 shows how affects the step and frequency response of this type of PLL, the markers in the step response show the time needed for 2% settling. The fastest settling is achieved with a damping of = 0.707.
Step Response 1.5 =0.3 1 =1 =0.71 0.5 =0.5
Amplitude
=2
=0.71 =0.5 =0.3 =1 =2 15
5 Time / Settling Time ( t)

n
10
Bode Magnitude Diagram 10 =0.3 0 Magnitude (dB) 10 20 30 40 1 10 =2 =1 =0.5 =0.71
40
dB
/ de
10 Frequency (/ )
n
10
Figure 2.8: Step Response and Frequency Response of Type I, 2nd Order PLL
The -3dB closed loop bandwidth can be calculated from (2.2.19) as

25
Closed Loop Bandwidth for Type I PLL

n 2 n 2
B3dB [Hz] = =
1 2 2 +
2 4 2 + 4 4
(2.2.20)
for = 0.707
For values of < 0.707, |T (s)| exhibits peaking with a relative maximum of Mp at the frequency p
Frequency Peaking of Type I PLL
M p
1 2 1 2 2 12
(2.2.21) (2.2.22)
= n
A high loop gain is desirable to suppress phase errors. Sideband or noise suppression usually denes an upper corner frequency of the LPF. However, the damping is inversely proportional to the loop gain, and damping values below 0.5 lead to excessive gain peaking of the loop response and long settling times. This means, with a loop lter like that, loop gain K and the time constant of the LPF T1 cannot be chosen independently. Noise BW Bn = 1/4K ???
2.2.4
Type I, second / third order PLL, with one zero

to VCO VPD= ICP R1 PD/CP C2 C1 R2 2nd pole 1st pole / zero 1st pole / zero I CP = VPD / R1 R1 PD to VCO
C2 R1 R2 2nd pole C1
Figure 2.9: Averaging Loop Filters of 1st / 2nd order (one zero) Type I PLLs do not need a zero in the loop lter transfer function but in some cases it is helpful to obtain a larger loop bandwidth or to reach a special transfer characteristic (g. 2.9). Especially when using a simple rst order low-pass, the zero gives one more degree of freedom to allow for choosing both K and T2 : F(s) =
Christian M nker u
sT2 + 1 sT1 + 1
. . with T1 = (R1 + R2 )C, T2 = R2C
(2.2.23)
December 20, 2005
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Open Loop Gain (dB)

0 dB
20db/dec 40db/dec
Phase
n
40db/dec
20db/dec
0 90
2 1
180 3
log
Figure 2.10: Bode Plot for Open Loop Gain GH( j ) of Type I, 2nd / 3rd order PLLs (one zero)
As always, there is no free lunch: worse spurious and noise suppression is the price that has to be paid for the extended bandwidth and higher exibility that come with the zero.
2.3 Type II PLLs (Integrating Loop Filter)

A Type II PLL has an integrating loop lter which looks purely capacitive at low frequencies (pole at the origin). The phase detector / charge pump combination needs to deliver a current into the loop lter. Alternatively, the active loop lter topology (2.12b) rst transforms the voltage output of the PD into an current via R1 which is then integrated. Due to the integrating behaviour, only special phase detector types can be used, most common is the use of a phase / frequency detector with tri-state charge-pump output (type 4). Figure 2.12 shows some realisations for such charge pump / phase detector / loop lter combinations. When the PLL is in lock, the integral of the charge pump current over one reference cycle must be zero, otherwise the loop lter voltage and hence the VCO frequency would drift away.
2.3.1
Type II, second order PLL
This PLL has two integrators in the loop (VCO and integrating loop lter), therefore it needs a zero in G(s) to be stable: F(s) = 1 1 + sT2 s T1 (2.3.1)
For a charge pump + R2C2 combination, T1 = C2 and T2 = R2C2 , for an active integrator, T1 = R1C2 and T2 = R2C2 . The resulting open loop transfer function is T (s) =
Christian M nker u
K 1 + sT2 N s2 T1
(2.3.2)
December 20, 2005
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Open Loop Gain (dB)

0 dB
Phase
40db/dec
2nd order 3rd order 4th order
n
20db/dec 60db/dec
90
135
40db/dec
m
2 c 1 3
180
log
Figure 2.11: Bode Plot for Open Loop Gain GH( j ) of type II, 3rd / 4th order PLL
a: Charge Pump
b: Active Integrator
2nd order C1
R3 PD/CP C2 C1 R2
to VCO
1st order R1
C2
R2
C3
+
R3 3rd order
to VCO
3rd order 2nd order 1st order
PD
C3
Figure 2.12: Integrating Loop Filters of 1st / 2nd / 3rd order (one zero)
showing a double pole at the origin (one due to the VCO and one due to the integrating loop lter) and a zero at s = 1/T2 (solid line in g. 2.11). The closed loop transfer function becomes (using the notation of the PT2 approximation, appendix F) T (s) = N (2 /n s + 1) 2 (s2 /n ) + (2 /n )s + 1 (2.3.3)
Once more we use the nal value theorem (2.2.9) to estimate the settling behaviour at the PLL output:
lim h(t) = =
s0 s0
lim s
T (s) ; sk
k = 0, 1, 2, . . .
lim s1k
N 2 s2 /n + 2( /n )s + 1
December 20, 2005
Christian M nker u
28
j KO : 0
n (2)
Figure 2.13: Root locus diagram for typ II, second order PLL 0 N = for k = 0 for k = 1 for k 2 (pulse response) (step response) (ramp response) (2.3.4)
We notice that the nal values of a type II PLL are exactly the same as with a type I PLL a pulse disturbance of the input phase (k = 0) completely disappears at the VCO output, a phase step (k = 1) at the input appears multplied by N at the output and a phase ramp (= frequency step, k = 2) leads to an innitely increasing phase at the VCO i.e. a frequency change. This doesnt come as such a big surprise as every PLL passes phase changes with a low-pass characteristic (and maybe an amplication) from the input to the output. So, wheres the big difference between type I and type II PLLs? Well see that the phase error at the input behaves in a very different way from the type II PLL: H ,II (s) = 1
2 T (s) s2 /n = 2 2 N s /n + 2( /n )s + 1
(2.3.5)
Using our stimulus signals re f = c/sk and the nal value theorem (2.2.9) once more for pulse, step and ramp input (k = 0, 1, 2) we get the settling at the PLL input: lim e (t) = = lim se (s) lim s1k
2 s2 /n ; 2 s2 /n + 2( /n )s + 1
s0
s0
k = 0, 1, 2, . . .
Due to the double integrator, a Type II PLL also manages to get the phase error back to zero when a phase ramp (=frequency step) is applied.
0 for 0 for = 0 for
k=0 k=1 k=2
2.3.2
Frequency Response
The magnitude of the steady state response is

29
N |T (s)| = ???
Step Response 1.5 =0.3 =2 Amplitude 1 =1 =1 =0.7 0.5 =0.7 =0.5 =0.3
(2.3.7)
=2
5 Time / Settling Time ( t)

n
=0.5
10
15
Bode Magnitude Diagram 5 Magnitude (dB) 0 5 10 15 20 1 10

0
20
dB
/ de
=2 =1 =0.5 =0.3
=0.7
10 Frequency ( / )
n
10
Figure 2.14: Step Response and Frequency Response of Type II, 2nd Order PLL
again, using the abbreviations
n =
and
KO (CP) resp. n = NC2
KO R2 (Integrator) NT2 R1
(2.3.8)
R2 2
KOC2 R2 (CP) resp. = N 2
KOC2 (Integrator) NR1
(2.3.9)
the -3dB bandwidth of this loop is
B3dB [Hz] =
n 2
2 2 + 1 +
(2 2 + 1)2 + 1
(2.3.10) (2.3.11)
= 2.1
n 2
for = 0.707
which is approximately twice as large as with a Type I PLL with the same and n . The noise bandwidth is Bn = KR2 + 1/T2 K(R2 /R1 ) + 1/T2 (CP) resp. Bn = (Integrator) 4 4
(2.3.12)
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December 20, 2005
30
2.3.3
Type II, third order PLL
Another pole is introduced e.g. for improved reference spurious rejection by adding another capacitor in parallel to R2C2 of the CP loop lter. The transfer function of the loop lter becomes F(s) = 1 1 + sT2 s 1 + sT1 (2.3.13)
2.3.4
Dual Path Loop Filters
The rather large loop lter capacitances of conventional integrating loop lters make the integration on a chip impractical and expensive. Dual path loop lters [CS98] allow reducing the total capacitance by splitting up the loop lter. One lter path contains a low-pass RP ,CP and a charge-pump, the second one consists of an integrator and a second charge-pump with reduced current. This allows reducing the integrator capacitance by the same amount as the charge pump current. The signals of both paths are summed up and put through a post-lter if needed. Potential issues: noise due to reduced current and capacitance, mismatch between charge pumps causes errors in loop gain and bandwidth
Figure 2.15: Dual Path Loop Filter
2.4 Comparison of Type I and Type II PLLs

The most important distinction is whether the PLL has an averaging or an integrating loop lter, i.e. whether the PLL is of Type I or Type II: Type I PLL loop lters show no integrating behaviour (non-integrating or averaging loop lter). They have no pole at the origin, their transimpedance is resistive at low frequencies. This means, the DC component of the output voltage is only determined by the duty cycle
2.5 Loop Filter Impedance
31
and the pulse amplitude of the input signal. The PD output has to pulse all the time to provide the tuning voltage for the VCO. Type II PLL loop lters include an integrator creating a pole at the origin (integrating loop lter). Therefore, the transimpedance at low frequencies is capacitive. The output voltage depends on the history of the input signal - in locked state, only the non-idealities of PD / CP create pulses and a ripple on the VCO control voltage. The phase detector usually has a tri-state output. The order of a PLL can be increased by using higher order loop lters. The higher order poles may only become effective at frequencies above fc (or must be compensated by zeroes), otherwise the loop will become instable. The benets of higher order PLLs are a sharper roll off of |C( j )| outside the loop bandwidth and hence a better noise / spurious performance. In control applications, higher order PLLs permit better tracking of input signals. The drawbacks are an increased sensitivity to component variations, a higher component count and of course the more difcult dimensioning.
2.4.1
Type I PLLs (Averaging Loop Filter)
The averaging loop lter in Type I PLLs (g. 2.5) averages the output of the phase detector (PD). This has some consequences: The PD must deliver voltage pulses into the loop lter because the VCO expects a tuning voltage. If the PD/CP has a current output, this current must rst be converted into a voltage in a loop lter resistor (g. 2.5). The pulse width at the output of the PD is proportional to the phase error at the input. As the output voltage of averaging loop lters is proportional to the pulse width, Type I PLLs always have a static phase error in lock. This phase error depends on the VCO frequency (VCO control voltage is determined by the pulse width) and on the PD output voltage (or PD/CP output current). This leads to a major drawback of Type I PLLs: variations of the loop gain e.g. by thermal drift of the VCO characteristic cause a phase drift that may be unacceptable for precision applications. The product of CP current and load resistor may be larger than the supply voltage without clipping the signal. This is because the CP drives current into the load resistor with a capacitor in parallel which swallows a part of the charge. As long as the duty cycle does not become too large, the loop lter voltage will not reach the supply. The PD/CP are active for a much longer part of the reference period than they would be in a Type II PLL. This favours injection of bias noise or other disturbances into the loop lter. The linearity of a Type I PD/CP in general is better then its Type II counterpart because the ill-dened turn-on and turn-off phases of the CP are short in relation to the total turn-on time. The open loop transfer function T (s) only contains one integrator - the VCO. This allows a bigger variety of loop lter structures than in Type II PLLs where the transfer function must have a zero to compensate for the second integrator.

As seen in the last section, the loop lter has a lot of inuence on the dynamic behaviour of the PLL. Unfortunately, the math on the way is quite ugly. Before moving to the spectral
32
performance of PLLs, i.e. spurious sideband and noise behaviour, it would be nice to have some handy approximations for the loop lter. The calculations in the frequency domain can be ugly enough without the complexities of higher-order loop lters. Fortunately, it is sufcient to look at the circuit well inside or far outside the PLL passband for most cases. In these two ranges, loop lters can be approximated very nicely by their input impedance ZLF,i and transimpedance ZLF , i.e. the ratio of output voltage and input current. The rst step is to split the loop lter impedance into the input impedance ZLF,i and the post-lter creating the roll-off at higher frequencies. For phase detectors with current output (only these will be regarded here), the loop lter input impedance acts as a transimpedance (current in, voltage out). The post lter modies this impedance by its attenuation |APF ( f )|: |ZLF ( f )| = |ZLF,i | |APF ( f )| (2.5.1)
This simplied analysis is only valid if the post-lter does not interact too much the input impedance, i.e. when the post-lter does not shift the corner frequencies f1 , f2 too much.
2.5.1
Averaging Loop Filter
In the simplest case (no zeros), the loop lter core is a simple one-pole low-pass (see g. 2.5) which looks like a resistor R1 at low and like a capacitor C1 at high frequencies (g. 2.16). Higher frequencies are attenuated with a 1/ f or -20dB / dec. characteristic.
Loop Filter Impedance for Averaging Loop Filter (no zero)
ZLF,i ( j ) = R1 =
R1 1 = 1 + j R1C1 1 + j T1 R1 for f f1 1/ j C1 for f f1
(2.5.2) (2.5.3)
with
. T1 = 1/2 f1 = R1C1
|Z LF,i (f)| R1
0 90 f1 fc f ref log f
Figure 2.16: Impedance of Averaging Loop Filter (1 pole, no zero) A zero in the lter (see g. 2.9) makes things slightly more complicated - at low frequencies the impedance is also resisitive, R1 , around f1 (pole) the impedance starts dropping and becomes capacitive. At f2 (zero) the phase shift turns up towards zero and the input resistance becomes resistive again, R1 ||R2 this time (g. 2.17). This means, higher frequencies are attenuated by only a limited amount R2 /(R1 + R2 ). This effect produces a strong ripple on the loop lter voltage and usually must be compensated by higher order post-lters.
33
Loop Filter Impedance for Averaging Loop Filter with zero

1 + j R2C2 1 + j (R1 + R2 )C2 1 + j T2 = R1 1 + j T1 R1 for f f1 = R1 ||R2 for f f2 < . T1 = 1/2 f1 = (R1 + R2 )C2
ZLF,i ( j ) = R1
(2.5.4) (2.5.5)
with
. T2 = 1/2 f2 = R2C2 ;
|Z LF,i (f)| R1 R1||R2 f1 fc f2 f ref
0 90 log f
Figure 2.17: Input Impedance of Averaging Loop Filter (1 pole and 1 zero) (2.5.5) and g. 2.16 show that ZLF has only one pole at s1 = 1/T1 and a zero at s2 = 1/T2 . This leads to a mainly resistive behaviour of the transimpedance, with ZLF R1 at low frequencies and ZLF R1 ||R2 at high frequencies.
2.5.2
Integrating Loop Filter
Integrating loop lters have a mainly capacitive behaviour, i.e. they integrate the output current from the charge pump and convert it into the VCO control voltage. The transimpedance ZLF,i ( j ) of an integrating three element / second order loop lter (see g. 2.12) is given by:
Loop Filter Impedance for Integrating Loop Filter

1 + j R2C2 j (C1 +C2 ) 2 R2C1C2 1 + j R2C2 1 j C1 C1 +C2 + j R2C2 1 1 + j T2 j bC1 1 + j T1 1 j C1
C1
ZLF,i ( j ) = = = =
. C1 +C2 with b = C1
(2.5.6) (2.5.7)
with
34
. T2 = 1/2 f2 = R2C2 ;
>
C1C2 . R2C2 = R2 T1 = 1/2 f1 = b C1 +C2
(2.5.6) shows that ZLF,i ( j ) has one pole at the origin, one pole at 1 = 1/T1 and a zero at 2 = 1/T2 3 . The zero is always between the two poles. This means, ZLF,i ( j ) is always capacitive, except in the frequency range between 2 and 1 .
C1 is the equivalent loop lter input capacitance:
C1
1 + j T1 bC1 = bC1 1 + j T2 C1 +C2 C1 ff2 C1 for for for
1 + 2 T12 1 + 2 T22 f1 , f2 f f1 f1 , f2
= bC1
1 + ( f / f1 )2 1 + ( f / f2 )2
f f2 f
(2.5.8)
|Z LF,i (f)|
C*(f) 1 C1+C2
90 f2 fc f1 f ref log f
C1 f2 fc f1 f ref log f
Figure 2.18: Loop Filter Impedance / Effective Capacitance of Integrating Loop Filter (2.5.8) and g. 2.18 show that at very high frequencies only C1 and at low frequencies the sum of C1 +C2 is effective.
2.6 Post-Filter and Higher Order PLLs

PLLs using three-element loop-lters - especially those with averaging loop-lters - have reference spurious sidebands that are too high for many applications. An additional RC lowpass (post lter) creates an extra pole at s3 = 1/T3 1/R3C3 , giving a third order loop lter (see g. 2.12), that attenuates these sidebands: ZLF (s) = 1 + sT2 1 sbC1 (1 + sT1 )(1 + sT3 ) (2.6.1)
It is assumed that the additional pole does not interact strongly with the pole at 1/2 f2 , i.e. T1 T1 , T2 T2 . In this case, phase margin and lock-in time are not deteriorated and the spectrum of the error signal ve (t) is additionally attenuated by the RC low-pass consisting of R3 and C3 : |APF,3 ( f )| =
3 Note
1 1+
f f3 2
f3 f
for
f3
that the position of the pole and the zero have changed their places compared to the integrating lter.
Christian M nker u
December 20, 2005
2.6 Post-Filter and Higher Order PLLs
35
(20dB/dec.) - see also table 2.1. If the superposition principle is valid (i.e. for a low modulation index), the spurious sidebands sk of the VCO are attenuated by the same amount |A3 ( f )|. Especially the reference frequency fre f needs to be attentuated by R3C3 , therefore f3 must be lower than fre f . For stability reasons, f3 must be signicantly higher than f1 .
f3 / f |APF,3 ( f )| |APF,3 ( f )| (dB20)
0.2 0.98 -0.2
0.5 0.89 -1
1 0.71 -3
1.73 0.5 -6
2 0.45 -7
3 0.32 -10
4 0.24 -12
5 0.20 -14
7 0.14 -17
10 0.1 -20
Table 2.1: Attenuation of RC Lowpass Filter
2.6.1
Attenuation of Reference Frequency
The loop lter converts input current pulses i(t) into an output voltage ve (t). This input current has signicant spectral components at the reference frequency that need to be suppressed. Shape and spectrum of the current pulses look different for an integrating or an averaging loop lter (g. 2.19): For an integrating loop lter, the pulses are very narrow with a width of TABL or less. The amplitude of the spectral lines is quite low (low pulse energy due to narrow width) but stays constant up to high frequencies (1/TABL ). For an averaging lter, the loop lter voltage is equal to the average value of the pulses. Therefore, their pulse width (and hence energy) has to be much higher, but the amplitude of the spectral lines drops much faster (rst zero at 1/TPW M ). In general (section 6.5), the spectrum of a rectangular pulse train is given by (6.5.7) ck = 2m sin k = 2m sinc(k ); k k = 1, 2, . . . where = Tw /Tre f
For details see section 6.5.

s(t)
(w/T )
ref
S(f) TPWM

(a): Nonintegrating loop filter
(b): Integrating loop filter
Figure 2.19: Spectra of Pulses for (Non) Integrating Loop Filter
E XAMPLE 1: Harmonics of short vs. long CP pulses

A charge-pump produces pulses of m = 1 mA at a reference frequency of fre f = 200 kHz (Tre f = 5 s). The pulse width is TPW M = 2 s (averaging loop lter)
TABL
Tref
f t 1/TPWM 2/TPWM
(w/T )
ref
f t 1/Tref 1/TABL
36
resp. TABL = 2ns (integrating loop lter): Duty Cycle :
av
= TPW M /Tre f = 0.4 = TABL /Tre f = 4 104 = mTPW M = 2nAs (wint = 2pAs) = 2mav sinc(av ) = 0.6mA = 2mint sinc(int ) = 80 A = 60 A; c101,int = 80 A
int Pulse Weight : wav Fundamental : c1,av c1,int 101st Harmonic : c101,av
The energy content of very short pulses can be larger than the energy content of wide pulses at higher order harmonics. In praxis, this is usually no problem because higher order harmonics are attenuated heavily by the loop lter. However, when the charge pump is not properly isolated from the rest of the chip, these higher harmonics may contaminate the chip via the supplies, bondwires or some other form of capacitive coupling.
Usually, fre f f1 , f2 so that the above approximations for ZLF can be used. In this case, the complex loop lter impedance Z(s) can be approximated by the loop lter capacitor C1 (integrating LF or averaging LF without zero) or by the resistance R1 ||R2 (averaging LF with zero) (see above): ve (t) = ie (t) Z 1 C1
t
ie ( )d for fre f
f1
(2.6.2)
However, as soon as post-lters are used, the above integral becomes painful. Fortunately, it is much easier to calculate the voltage error at the output of the loop lter in the frequency domain: Ve ( j ) = Ie ( j ) ZLF ( j ) (2.6.3)
Due to the mainly resistive behaviour of the averaging lter, the reference feedthrough and reference spurious sidebands are much worse than with an integrating loop lter with the same bandwidth.
Christian M nker u
December 20, 2005
Chapter 3
PLL Building Blocks

If builders built buildings the way programmers wrote programs, the rst woodpecker to come along would destroy civilizations. Anonymous
Overview: This chapter gives you an overview over basic building blocks of an PLL like phase detector (PD), charge pump (CP), divider or VCO.
3.1 Overview 3.2 Phase Detector

There are different types of phase detectors with different phase and frequency behaviour. [Bes98] has categorized them as type 1 ... type 4 (table 3.1), but it seems these categories are not used outside of Germany. Nevertheless, [Bes98] gives a good overview.
All phase detectors produce an output signal of some sort that is proportional to the phase difference at their inputs (thats where the name comes from ...). The phase detector gain PD type Modus Tristate PD FD Multiplier (Type 1) continous yes EXOR (Type 2) sampled yes EXOR + FD sampled yes yes JK-Flip-Flop (Type 3) sampled yes (yes) Tristate PFD (Type 4) sampled yes yes yes
Table 3.1: Overview of Phase Detector Types Suitable for Frequency Synthesis 37
38
PLL Building Blocks
K is the ratio of a change of averaged output voltage and a change in phase error, it is only dened for identical input frequencies at both inputs, otherwise the phase error is different with each period: K = vout e (3.2.1)
When the PD works together with a charge pump (current output), K is usually dened as K = iout e (3.2.2)
There are continous or analog PDs (Type 1) which control the loop all the time and sampling or digital PDs (all the others) which are only updated once or twice per reference period. Type 4 PDs are quiet when the PLL is in lock, while the others produce pulses. Due to this three-state behaviour, type 4 PDs are well suited for driving an integrating loop lter. Type 1 and 2 PDs struggle helplessly when the frequencies at both inputs are not identical1 . The other PDs can handle any frequency difference at their inputs.
3.2.1
Analog Multiplier (Type 1 PD)
Analog multipliers are the oldest phase detectors. They have some advantages concerning noise suppression, however, they require analog inputs and cannot be used together with a divider (digital output!) in the feedback path. Therefore, they are not suitable for frequency synthesis and will not be regarded here. For more details, see [Gar79, pp. 106 - 120]: Here, multiplying PDs are analyzed in detail, with focus on noise and lock-in behaviour. Only suitable for analog (not clipped) signals of same frequency fvco = fre f . In locked state e = 0 and the output voltage ud pulses with twice the input frequency.
1 ud = (umax umin )/2 when e = 2 or when fvco = fre f
K =
umax umin 4
Ref ud VCO 4quadrant multiplier
Figure 3.1: Multiplier symbol
1 Due to second order effects, Type 1 and 2 PDs also can handle a frequency difference although only in a very limited range.
Christian M nker u
December 20, 2005
3.2 Phase Detector
39
ud u max
u min 2 0 /2 2 e
Figure 3.2: Average multiplier output signal ud as function of phase error e

ud u max
fdiv > fref fdiv < fref
locked
u min
Figure 3.3: Average multiplier output signal ud as function of frequency error fe
3.2.2
EXOR (Type 2 PD)
An EXOR is the most simple implementation of a digital phase detector. It can be regarded as a clipping version of the analog multiplier. Therefore, some of its properties are quite similiar to the multiplier. In most cases, an EXOR is used together with an averaging loop lter (Type I PLL), because the output is simply a pulse width modulated voltage with an average value proportional to the input phase difference. This is accomplished either by switching a current source that drives a load resistor or by simply using the output voltage of the EXOR itself. A big disadvantage of the simple EXOR PD is that it does not work when the frequencies at its input are different: in this case, the duty cycle at the output varies all the time. Also, it can cannot differentiate whether the divider phase is early or late by | |. However, the early point ( = . . . 0) is unstable in a closed loop: when e.g. | | becomes smaller, the duty cycle becomes smaller as well. The resulting loop lter voltage reduction slows down the VCO2 , reducing | | even further although the system should try to compensate the disturbance. Therefore, the divider phase is always late in a locked loop with EXOR PD, i.e. = 0 . . . and the PD slope is always positive, ud / e > 0. As a consequence, the phase difference between its inputs in locked state depends on the operating conditions: The VCO needs a certain tuning voltage for a certain target frequency. The control loop action of the PLL will generate the corresponing phase difference. This means, the phase error will depend on the target frequency and the VCO characteristics - a change of e.g. the VCO gain causes a phase drift. Due to the simple structure, the EXOR PD can be designed with an excellent phase noise behaviour. Drawbacks are that it cant be used as a frequency detector and its sensitivity to
2 Assuming
the VCO has a positive voltage-frequency characteristic
Christian M nker u
December 20, 2005
40
PLL Building Blocks
2 Ref Div Q
t
Figure 3.4: Timing diagram for EXOR PD with identical frequency at its inputs
Ref Div Q t
Figure 3.5: Timing diagram for EXOR PD with different frequencies at its inputs
duty cycle variations. Tor some applications, the undened static phase error can also be a problem.
Only phase sensitive, not suited for signals with different frequency fre f = fdiv . In locked state e = 0 and the output voltage ud pulses with twice the input frequency. The average output voltage depends on the duty cycle of the signals. The next two equations are only valid for duty cycles of 50%:
1 ud = (umax umin )/2 when e = 2 or fre f = fdiv
K =
umax umin
Ref
Q Div
Figure 3.6: EXOR schematic
Christian M nker u
December 20, 2005
3.2 Phase Detector
41
ud
gio Sta ble Re
u max
Repeat
Un
sta ble
u min 2 0 /2 2 e
Figure 3.7: EXOR average output signal ud as function of phase error e

ud u max
fdiv > fref fdiv < fref
Figure 3.8: Average EXOR output signal ud as function of frequency error fe
Re gio n
Repeat
locked
u min
3.2.3
EXOR + FD (Perrott)
This phase detector behaves like an EXOR (Type 2 PD) when the loop is in lock, i.e. it produces pulses with a duty cycle proportional to the phase error. Therefore, most of the descriptions for the EXOR are also true for this type of phase detector. For a detailed description see [Per97, pp. 126 - 129]. In contrast to the EXOR, the following features have been added: The divide by two ip ops at the inputs extend its phase sensitivity range to 0 . . . 2 and make it insensitive to variations of the duty cycle. Its additional frequency detector turns the EXOR into a phase-frequency detector (PFD). They can distinguish between the stable and the unstable region of the EXOR operating range: when the EXOR output is C = 0 at the rising edge of REF and C = 1 at the rising edge of DIV, the current operation is in the stable region (0 < e < 2 ). In other cases, the frequency detector becomes active, pulling Slo or Shi low. Phase and frequency sensitive for arbitrary frequency differences. In locked state e = 0, the output voltage ud pulses with the input frequency (not with the double input frequency) - due to the frequency dividers, this is different to an ordinary EXOR! Also due to the frequency dividers, this PD is not sensitive to duty cycle variations of its input signals. K = umax umin 2
Christian M nker u
December 20, 2005
42
PLL Building Blocks
Ref
D Q
Ref/2
DFF
Q
DFF
R Q
S hi
&
C
=1
D Q D S Q
&
S lo
Q
DFF
Q
Div/2
DFF
R
Div
Divider /2
XOR
Frequency Detector
Figure 3.9: EXOR+FD schematic

u max
FD Mode fdiv > fref
ud
PD Mode div < ref
u min 4 2 0 2
FD Mode fdiv < fref
Figure 3.10: Average EXOR+FD output signal ud as function of phase error e
3.2.4
JK Flip-Flop (Type 3 PD)
The JK Flip-Flop has the peculiar property that it works as a phase detector and also as a frequency detector - but only when the input frequencies are sufciently different. When the input frequencies are nearly identical, the output voltage runs with the frequency difference, making lock impossible. Therefore, this type of PD is not suitable standalone for frequency synthesis but it can be used together with other detectors to aid frequency acquisition. Phase and frequency sensitive, but not for frequencies which are nearly identical fre f fdiv . In contrast to an EXOR, this PD is not sensitive to variations of the duty cycle of its input signals because it operates on the edges of the input signals. In locked state: e = 0, pulsed output voltage.
K =
umax umin 2 Non-inverting and inverting output available - they are not UP and DOWN outputs!
3.2.5
Tristate PFD (Type 4 PD)
This has been the classical PD for integrated frequency synthesizers in the last 20 years (and still is). It ts well with the classical Up-Down-Chargepump which itself is very well suited
3.2 Phase Detector
43
ud u max
fdiv > fref
fdiv < fref
PD Mode
u min
fe
Figure 3.11: Average EXOR+FD output signal ud as function of frequency error fe

Ref Div Ref/2 Div/2 C S lo S hi Q
Figure 3.12: Signals in the EXOR+ PD when fre f > fdiv for integration in CMOS technologies. It is phase and frequency sensitive with an unlimited lock-in range. Its three state output ts nicely with integrating loop lters and charge pumps with very short turn-on cycles. These short turn-on times make it easier to achieve good noise performance, additionally, the integrating characteristic gives good suppression of inband VCO noise. Phase and frequency sensitive Up / down voltage outputs with quiet state (up and down outputs high-ohmic) in locked state (e = 0), therefore suitable for charge pumps / integrating loop lters. K = umax umin 4
Sensitive to missing edges because the PD has memory and tries to correct the missed edge. This makes type 4 PDs unsuitable for clock and data recovery purposes.
3.2.6
Hogges Phase Detector
[LB92], [Lee98]
3.2.7
(Modied) Triwave Phase Detector
[LB92], [Lee98]
44
PLL Building Blocks
2 Ref Div Ref/2 Div/2 C S hi S lo Q
Figure 3.13: Signals in the EXOR+ PD when fre f = fdiv (div < re f )
Ref Q
Q Div
Figure 3.14: JK Flip-op schematic (neg. edge triggered)
3.3 Charge Pumps

3.3.1 3.3.2 Single Ended Designs The Dead Zone and How to Get Around It
An old problem with charge pump designs is the dead zone: when a type II PLL is in or near lock, only very short pulses are needed to keep the loop locked. However, the speed of the PD logic or the CP may not be sufcient to fully turn on the current sources. The resulting phase error transfer characteristic has a at part around = 0, i.e. K is reduced or even zero in the main operating point of the PLL. The consequence is a strong deviation of loop gain and loop bandwidth from the target value that cannot be explained from static CP current measurements. This a purely dynamic effect that also depends on temperature and process variations. In really bad cases the dead zone can cause the PLL phase to drift around the locked value because the loop is effectively open (K ) around = 0. The result is a tremendously increased phase noise / jitter. Obviously, its best to avoid the dead zone altogether, a very effective solution is to increase the latency time of the PFD in the reset path (g. 3.17). This extra delay creates a minimum
3.3 Charge Pumps
45
ud u max
repeat
u min 2 0 2 e
Figure 3.15: Average JK Flip-op output signal ud as function of phase error e

ud u max
undefined
fdiv > fref
undefined
fdiv < fref
PD Mode
u min
Figure 3.16: Average JK Flip-op output signal ud as function of frequency error fe pulse width (anti-backlash, ABL) of the Up/Down pulses. At = 0, the pulses cancel each other out, small phase errors increase the length of one of the pulses in a very linear way. The minimum pulse length should not be excessively long because the transfer of amplitude noise components from the charge pumps is proportional to the pulse length. When the Up/Down current sources are not perfectly matched, the mismatch creates spurious sidebands, increasing with the pulse width (6.5). Another solution to get around the dead zone problem is to add a small DC offset current (trickle charge) to the CP output (g. xxx). When the offset current is sufciently large, the PFD / CP combination always works in one quadrant in locked state, i.e. only one current source is active. This not only eliminates the dead zone, it also avoids non-linearities due to different up/down - currents ( K ). Reference frequency spurious sidebands resulting from the offset current (6.4) usually forbid the use of this concept in integer PLLs - the reference frequency is too close to the loop bandwidth to achieve a sufcient suppression. However, for fractional-N PLLs the case is different: the reference frequency is much higher and PLLs distribute the energy of the reference spur over a wider frequency band anyway. Most importantly, is that PLLs are very sensitive to non-linearities, yielding strange spurious sidebands. Operating the CP only in one quadrant removes these sidebands.
3.3.3
Charge Pumps and Two-State Phase Detectors
Although the three-state PFD is a charge pumps best friend, two-state PFDs or PDs like the EXOR can also be combined with a charge pump / integrating loop lter combination: The EXOR output switches e.g. the current sink, the inverted output switches the current source (g. 3.20). Or, the EXOR switches e.g. the current sink, the current source is always on, with half the current owing continously into the loop lter (g. 3.21). In average, the net current
46
PLL Building Blocks
"1" Ref
DFF
R Q
UP TABL
"1" Div
DFF
R Q
DOWN
Figure 3.17: Tristate PFD schematic

i max FD Mode
fdiv > fref
id
PD Mode
div < ref
FD Mode i min 4 2 0 2
fdiv < fref
4 e
Figure 3.18: Average Tristate PFD output signal id as function of phase error e owing into an integrating loop lter must be zero. Therefore, the control loop action of the PLL forces sink and source current to be switched on for exactly the same duration (50%) per cycle. The resulting input phase difference is /2 (if current sink and source have the same current magnitude I0 and if the duty cyle of the input signals is 50%). The same is true for the unipolar charge pump if the switched current is exactly twice as large as the constant current. A major disadvantage of this concept is that CP current is owing all the time, coupling noise into the loop lter.
3.4 Loop Filter

See section
3.5 Divider
Programmable dividers for RF frequency synthesizers usually are constructed from an RF prescaler and some programmable, lower frequency control / counter blocks. The reason for this is that all divider cells run with the full input frequency in a fully synchronous counter. This consumes a lot of power and is hard to design for high frequencies. A xed prescaler by P reduces the maximum input frequency to the programmable divider by a factor of P but it has a major disadvantage: the minimum frequency step increases by a factor of P. Prescalers built from dual modulus dividers (DMD) or multi modulus dividers (MMD) offer a way out of this dilemma: The division ratio (= modulus) of a DMD prescaler can be switched between 2N and 2N + 1; an MMD offers a wider range of division ratios, e.g. 2N , 2N + 1, 2N + 2, . . .. During the division cycle, the prescaler modulus is altered in such a way that the desired total
3.5 Divider
47
ud u max
fdiv > fref
fdiv < fref
PD Mode
u min
fe
Figure 3.19: Average Tristate PFD output signal ud as function of frequency error fe
I0 to VCO Ref
=1
Div Exor
I0
Figure 3.20: EXOR with bidirectional charge pump and integrating loop lter division ratio is achieved. This is described in the next two sections, [VFL+ 00] and [Per97] give a more detailled description of various divider architectures.
3.5.1
Dual Modulus Prescaler
At the heart of all DMD / MMD Prescalers is a divider cell whose division ratio can be switched between 2 and 3 (g. 3.22), depending on the logic level at the P input. When P = 0, the enable signal EN = 1 always enables the divider ip-op D FF1 , turning it into a simple 2 toggle ip-op: D1 = Q (g. 3.23). When P = 1, the phase shift ip-op DFF2 delays the Q signal of the divider DFF1 by one input cycle, pulling EN = 0 for one clock cycle. Thus one clock edge is swallowed by the divider ip-op D FF1 , creating a modulus 3 divider. This path is the critical timing path: The D1 input has to go low before the clock edge to be swallowed (slack in g. 3.23). For reasons that will be explained later, it makes sense to expand this basic 2/3 cell to a higher modulus, e.g. to 8/9. The principle is the same as in the 2/3 cell: here, every ninth pulse is swallowed. Simply adding an asynchronous 4 divider is not enough - you would end up with a 8/12 divider. A little extra decoding logic (g. 3.24) guarantees that the P input of the 2/3 cell goes high only when P = 1, Q23 = 0, Q4 = 0 and Q8 = 0 which happens once during each divide cycle. This pulse swallowing gives a total division ratio of 9. There is an upper limit to the number of asychronous divider stages for a given input frequency: when the time the clock edge needs to ripple through the asynchronous divider is approximately equal to the input period, the divider will fail. At higher frequencies, the prescaler may operate correctly again - with one clock cycle latency in the asynchronous divider! This failure is easily overlooked when sweeping the input frequency in large steps.
48
PLL Building Blocks
I0 to VCO Ref
=1
Div EXOR
2I0
Figure 3.21: EXOR with unidirectional charge pump and integrating loop lter
Divider /2 with enable
D
&
critical path
DFF1
Q
out
Fin
2/3
=>
Q EN
P
Fin P
Fout
&
DFF2
Q
Phase Shift P
P=0 => /2 P=1 => /3
Figure 3.22: Basic 2/3 divider cell
How can we design a fully programmable counter from such a DMD prescaler which can only be switched between two division ratios? The trick can be done with additional backward counters which are clocked with the output frequency of the prescaler (g. 3.25). With each output pulse, the A- and the B counter are initialized and start counting backwards with the output pulses of the prescaler. As long as A > 0, the P + 1 mode is active, for the rest of the time the prescaler divides by P. When the B-counter also has reached 0, an output pulse is generated and A- and B-counter are initialized again. During one output cycle, the input signal has been divided P for A time and P + 1 for B A times. The resulting division ratio of such a divider is (3.5.1):
Division Ratio of a Dual-Modulus Divider

N = B A P + A P + 1 = BP + A; B>A (3.5.1)
The corresponding signals are shown in g. 3.26 where P = 4, B = 5 and A = 3. The prescaler ratio P limits the lowest division ratio: B has to be higher than A for proper operation, which is quite obvious from the principle of operation. But B also has to be
3.5 Divider
49
2 F in F out QP P EN D1
P Switch Swallow
Swallow
P Switch
Slack
Figure 3.23: Signals in a 2 / 3 divider cell

Async. Divider /4 F Fin
Fin P
2/3
Fout
out
Q23
TFF
TFF
P23 Q4
1
critical path
Q8
P=0 => /8 P=1 => /9
Figure 3.24: An 8/9 dual modulus prescaler higher than P, otherwise there will be gaps in the achievable division ratios N. Assume for example P = 32 and B = 30. The highest division ratio will be 30 32 + 29 = 989 (3.5.1). The lowest division ratio for the next higher value of B = 31 is 31 32 + 0 = 992, i.e. the division ratios N = 990 or N = 991 cannot be reached with this architecture. In general, the minimum division ratio that can be set with a prescaler P without gaps is
Minimum Division Ratio of Dual-Modulus Divider

B P N P2 (3.5.2)
3.5.2
Multi Modulus Divider
A multi-modulus divider uses a different controlling mechanism: it usually consists of a chain of 2/3 cells (g. 3.27). Simply cascading some dual-modulus divider cells does not do the job as can be seen easily: a division ratio like N = 129 cannot be constructed from a product of 2s and 3s as it is a prime number! What we want is a construction that adds one extra cycle per output period if the modulus control Pi = 1. This can be achieved with extra control input and output pins Min and Mout (g. 3.28). The modulus enable input Min enables the P input pin, the modulus enable output Mout synchronizes the Min input and passes it on to Min of the previous divider stage. This daisy chain connection ensures that each divider stage swallows a maximum of one pulse per divide cycle (depending on the level at Pi ). The
50
PLL Building Blocks
DMD Prescaler Fin
Programmable Counter
P / P+1
Fin P Fout
BCounter
Q Reload B
Fout
B A
P=0 => P P=1 => P+1 Reload A
&
N=BP+A
ACounter
Figure 3.25: Dual-modulus divider

N=BP+A
P F in P out A QA B QB = Fout B=1 B=5 A=0 A=3 A=2 A>0 B=4 B>1 B=3 B=2 B=1 A=1 A=0 A=3 A>0 B=5 B>1 t P+1 P P+1
Figure 3.26: Signals in a dual-modulus divider resulting division ratio is:
Division Ratio of Multi-Modulus Divider

N = 2n + pn1 2n1 + . . . + p1 2 + p0 (3.5.3)
RFin
Fin
2/3
Fout M in P Fin
2/3
Fout Fin M out M in P
2/3
Fout Fin M out M in P
2/3
Fout M out M in P
DIV out
P0
P1
Pn2
Pn1
Figure 3.27: Multi-modulus divider made from a Chain of 2/3 divider cells Fig. 3.28 shows an improved 2/3 divider cell with modulus enable input. Speed is improved further by shifting the P - NAND into D-FF2 (between the Master and the Slave stage) to shorten the critical path. Synchronizing the programming word guarantees a xed timing relationship between programming word and divided clock. This is important if the division
3.6 VCO
51
ratio is switched dynamically like in Sigma-Delta Fractional-N synthesizers.

Divider /2 with enable
1
EN Fin
D1
Fout
D Q
DFF1
Q
2/3
critical path
Fin
Fout
M in
Q D
=>
DFF2
Q
&
D2
M out M in P
M out
Phase Shift
M_in = 0 => /2 M_in = 1 => P enabled
&
P = 0 => /2 P = 1 => /3
Figure 3.28: Improved 2/3 divider cell with modulus enable
3.5.3
High-Speed Flip Flops
The core cell for high-speed dual- and multi modulus divider blocks is of course a high speed ip-op. Depending on the available technology and the required operations speed, there are various circuit architectures: Current Mode Logic This design style is copied from high-speed bipolar circuits:
"Master" "Slave" Q Q D D Clk Clk Bias
Figure 3.29: D-Flip-Flop in current mode logic
3.5.4
Synchronization
One point to note with Dual- and Multimode - Dividers is their latency: a constant delay in an integer PLL introduces a constant phase error which is usually compensated for in the PLL. In fractional-N PLLs, the divider delay can depend on the division ratio - this variable delay / phase error introduces non-linearities showing up as spurious sidebands!
3.6 VCO
52
PLL Building Blocks
Christian M nker u
December 20, 2005
Chapter 4
Fractional-N PLLs
Better to light a candle than to curse the darkness. Chinese Proverb
In principle, it is possible to achieve any wanted frequency resolution with a PLL by just making the reference frequency small enough. But, as explained in chapter 2, a low reference frequency demands an even lower loop bandwidth for stability reasons. And a narrow loop bandwidth means sluggish transient response and bulky loop lter capacitors which is not acceptable for most applications. Besides that, a low reference and high target frequency require a high frequency division ratio which degrades the noise performance of the PLL (see section 10.1). For these reasons it would be nice to have a high reference frequency and a ne frequency resolution at the same time by using a fractional division ratio. A frequency of e.g. f0 = 900.1 MHz could be synthesized with a reference frequency of fre f = 1 MHz and a division ratio of N = 900.1 instead of using 100 kHz and N = 9001. Of course, it is not possible to divide a frequency by a non-integer value1 . But we can get away with a little cheating: if 9 out of 10 times the frequency is divided by 900 and once by 901, the division ratio average over 10 cycles will indeed be 900.1. And if we do it fast enough, no one will notice: The PD will try to correct the phase error due to the periodic switching of the division ratio but the loop lter is too slow to follow each excursion of the PD output. Hence, loop lter output and VCO will settle at the desired average frequency f0 . Such a PLL is called Fractional-N PLL. As usual, there is no free lunch: the drawbacks of Fractional-N PLLs are spurious sidebands created by periodic switching of division ratio increased circuit complexity increased sensitivity to component mismatch with some implementations In contrast to the PLLs described so far, the division ratio N(t) now is time dependent. In spite of the low-pass characteristic, the resulting VCO frequency will still contain some of the modulation of N(t): fVCO (s) = fre f N(s)T (s)
1 At
(4.0.1)
least not when using straight-forward digital techniques.
53
54
Fractional-N PLLs
This behavior determines spurious sidebands, phase noise and settling - it will be analyzed in the rest of the chapter. In addition to the functional blocks described in the last chapters, a Fractional-N PLL contains some new blocks (see gure 4.1): A divider that allows switching the division ratio between two (Dual-Modulus Divider) or more (Multi-Modulus Divider) different values. In contrast to the ordinary programming of the division ratio, this switching must be synchronized to the input signal (fast!!). A logic block controlling the periodic switching of division ratio. This block generally is some sort of counter / accumulator, it can be realized in many different ways. Some implementations will be described below. Optionally, some circuitry to compensate for the inherent spurious sidebands. The average output frequency f0 depends on the number NF of (N + 1) cycles per fractional modulus cycle Tmod . One fractional modulus cycle consists of Fmod reference clock cycles: Tmod = Fmod Tre f . Fmod is called the fractional modulus of the PLL, dening the minimum fractional frequency step fmod = fre f /Fmod . Fmod can be as low as 5 or several orders of magnitude larger, NF is in the range 0 . . . Fmod 1. The average output frequency is f0, f rac = (NI + NF /Fmod ) fre f = NI .F fre f where .F is the short form for the fractional part. The frequency deviation from a normal, integer PLL is therefore f0, f rac = NF fre f NF = Fmod Fmod Tre f (4.0.2)
E XAMPLE 2: Minimum frequency step of integer and fractional-N PLL

An Integer-N PLL with N = 900 and fre f = 1MHz produces a VCO output frequency of f0,int = 900MHz with a minimum frequency step of fre f = 1MHz. When a Fractional-N PLL is used with Fmod = 5 and NF = 1, the division ratio is 4 times N = 900 and once N+1 = 901 in Fmod = 5 reference clock cycles. This gives an average division ratio of 900.2 and an average VCO output frequency of f0, f rac = 900.2 MHz. The minimum frequency step is fmod = fre f /Fmod = 200kHz.
RF out PFD
f
Reference Frequency
Loop Filter
VCO N / N+1
Freq. Word
Integer Part Fractional Part
N mod CO
Accu
Figure 4.1: Frequency synthesizer using fractional-n techniques

4.1 First Order Fractional-N PLLs
55
Fmod = 3 NI = 10 REF NI f ref VCO N = 10 N = 10 N + 1 = 11 NI = 10 NI = 10
DIV PD/CP (initial) PD/CP (final)
N=10.333
Figure 4.2: Timing diagram of 1st order fractional-N PLL Fractional-N PLLs achieve the same frequency resolution as an integer-N PLL with a reference frequency that is higher by a factor of Fmod . The higher reference frequency lowers the noise oor by 10 log Fmod . However, due to the periodic switching of division ratios, there is a ripple on the VCO control voltage that is periodic with Tmod , producing spurious frequencies. Fractional-N PLLs with no further compensation of this periodic error are called rst order, PLLs using an analog compensation mechanism are called second order and PLLs that dither the error (Sigma-Delta-Modulator) are called third order.
4.1 First Order Fractional-N PLLs

All fractional-N PLL use the concept of averaging the frequency over a number of Fmod reference periods to achieve a fractional division ratio. The periodicity Fmod (also called modulus length) determines the frequency resolution of the PLL: f = fre f /Fmod (4.1.1)
This can be easily seen from an example: when the division ratio is Fmod 1 times NI and once NI + 1 during Fmod cycles, the resulting average division ratio will be: N= (Fmod 1) NI + NI + 1 = NI + 1/Fmod Fmod
The periodic switching of the division ratio is triggered by the phase accumulator, an accumulator with modulus Fmod that adds up NF every reference cycle. Each time an overow occurs, the division ratio is switched from N to (N + 1) for one reference cycle. Lets assume the PLL is locked at the fractional frequency f0 = NI .F fre f . Fig. 4.2 shows an example for a modulus of Fmod = 3, NI = 10 and NF = 1, giving an average division ratio of N = NI .F = 10 1/3. During the N parts of the modulus cycle the divided VCO signal arrives a little too early at the phase detector because the VCO is faster than the virtual signal f0,int = NI fre f (there is no such signal in the PLL) by f f rac (see 4.0.2).
56
Fractional-N PLLs
Ref. Cycle Modulus Cycle NF = 1: Accu Div.

0 2 t=0 0 2 t= 3 5
#1
#2 1 N
1 5
50 N +1
5 5
#3 #1 Tmod 2 N
2 5
#4 3 N
3 5 1 5
#5
4 N
4 5 2 5 3 5
... #2 Tmod 50 ... N +1 ... #6

5 5
Average
1 N+5 2 5
NF = 3: Accu Div. Ratio

0 2 t=0 0 2 t= 3 5
50 N +1
5 5
2 5
1 5 3 N
3 5 1 5
0 61 N +1
6 5 4 5 1 5
4 N
4 5 2 5
72 N +1
7 5 5 5
50 N +1
5 5 3 5
2 5
... ... ... ... ... ...
0 N+3 5
2 5
2 5
1 5
2 5
2 5
Table 4.1: Operation of Phase Accumulator (Fmod = 5)
4.2 Higher Order Fractional-N PLLs

In [RCK93] several methods for constructing a fractional-N frequency synthesizer are compared to a synthesizer based on Fractional-N Synthesis which is described here for the rst time. Although the concept of Delta-Sigma-Modulation had been used in the design of Analog-to-Digital Converters (ADCs) and Digital-to-Analog Converters for quite a while back in 1993, this article was the rst to apply that concept to the domain of frequency synthesis, triggering the development of many new circuits and applications. The methods used at that time to achieve fractional-N frequency synthesis were pulse swallowing (i.e. simple rst order fractional-N PLL) phase interpolation where the phase error is partially compensated by a DAC at the loop lter input Wheatley random jittering where a random number is added at the accumulator input Each method has major drawbacks: The rst on generates massive fractional spurs as we have seen, the second reduces these spurs at least partially but requires precision analog components and the last one reduces the fractional spurs at the cost of an increased noise oor. Therefore, lets rst take a look at sampling, oversampling and delta-sigma-modulation:
4.2.1
Sampling and Quantization
An analog signal needs to be discretized in time (sampled) and amplitude (quantized) to bring it to the digital domain. Nyquist was the rst to nd out that the sampling rate fS needs to be at least twice as high as the signal bandwidth fB to reconstruct the original signal without losses. The reason for this is that sampling creates images of the original signal around multiples of fS . If fB > fS /2, the images overlap, folding back frequency components above fS /2 into the base-band. These components are called aliases as a component at f1 cannot be distuingished from a component at f1 fS /2. The resulting distortion or increased noise cannot be removed. For this reason, the signal needs to be band-limited with an anti-aliasing lter to fB fS /2. It can be shown (and nearly every book on communication theory does it ...) that proper2 sampling is a procedure (at least in theory) from which the original signal
2f S
> 2 fB
Christian M nker u
December 20, 2005
57
can be recovered without losses. A low-pass with fB fLP fs /2 removes the images of the orginal signal around k fS , acting as a reconstruction lter. Quantization is another story - the innite amplitude resolution of the analog signal is reduced to a discrete number of levels which inevitably creates distortions and noise. In general, it is very difcult to predict the level of distortion as it depends not only on the quantization step size but also on the signal amplitude and statistics. Fortunately, many real world signals have a Gaussian amplitude probability density function which allows an easy calculation:
Figure 4.3: Quantization
Figure 4.4: Spectral density of quantization noise
Figure 4.5: Spectral density of quantization noise with oversampling If the signal has a Gaussian amplitude distribution, the same will be true for the quantization error qe as well. In this case the power spectral density of the quantization noise Nq ( f ) will be at: q2 2 1 q2 e,rms = (4.2.1) e2 = Nq ( f ) = e = n fS fS 12 fS Beware: This formula is too optimistic for periodic signals - here, quantization noise wont be at, containing harmonics and sub-harmonics that may be several dBs above the noise
58
Fractional-N PLLs
oor! The total baseband quantization noise power depends on the bandwidth fB . In the limit case of Nyquist bandwidth, fB = fS /2: SB,Nq =
fB fB
Nq ( f )d f =
fS /2 fS /2
Nq ( f )d f = q2 e,rms =
2 12
(4.2.2)
Converters operating near this limit are therefore called Nyquist-rate converters. Oversampling When the sampling rate is larger than 2 fB (oversampling), the quantization noise power in the base-band will be less - the part of the quantization noise that is stretched out above fB will be removed by the reconstruction lter (assuming fB = fLP ): SB =
fB fB
Nq ( f )d f =
SB,Nq 2 fB 2 2 fB = SB,Nq = 12 fS fS M
(4.2.3)
where M is the oversampling ratio (OSR) fS /2B. (4.2.3) shows that oversampling reduces the quantization noise in the baseband by 10 log M. The signal-to-noise ratio (SNR) is dened as the ratio of signal power and (baseband) noise power. Lets assume the signal is a sinusoid (happily ignoring that its quantization noise will not have a at spectral density) with an amplitude A which uses the full input range of the quantizer (2A = FSR = 2N ) without clipping. Its signal power will be A2 /2 = 2N 2 /8 SNR = 10 log A2 /2 q2 e,rms (4.2.4)
Another advantage of oversampling is the much relaxed requirements for the anti-aliasing lter - normally, you would use a bulky analog lter with a bandwidth just below the sampling frequency to preserve the full signal bandwidth. In an oversampling architecture, the antialiasing lter just needs to prevent signal components above fS /2 from entering the ADC which is far above the signal bandwidth. Signal and quantization noise between fB and fS /2 can be removed in the digital domain.
4.2.2
Delta Modulation
Delta modulation was originally developed to reduce the bandwidth for data transmission. It is actually the simplest form of differential predictive coding: some known property of the signal is exploited to compress the signal. When the sampling period is much higher than the main frequency components of the signal, bandwidth can be saved by transmitting only the changes of the signal (delta) between samples (g. 4.6 and 4.7). In its simplest form, delta modulation approximates the input signal with a staircase function. The signal is demodulated by integrating the delta samples and converting them back to the analog domain. In contrast to simple oversampling, the feedback in delta modulation forces the output of the modulator to track the lower frequency components of the input signal. Therefore, quantization noise is reduced at low frequencies and pushed to high frequencies where it can be ltered out more easily. Fig. 4.7 shows two potential sources of distortion in delta modulation: steep slopes cannot be tracked by the integrator (slope overload) and very slow changes of the signal can create so called granular noise. Increasing the step size reduces slope overload but increases the granular noise and vice versa.
Christian M nker u
December 20, 2005
59
DeltaModulator
s(t)
+1
DeltaDemodulator
dq(n) s(t)
f
Quantizer
Sampler
DAC
Integrator
LPFilter
Integrator
DAC
Figure 4.6: Delta modulation and demodulation
Input Signal
Granular Noise Slope Overload Distortion
Integrator output
TS
Delta modulated data stream
1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 1 0 1 0 1 0 0 0
Figure 4.7: Delta modulation signal forms
4.2.3
Principle of Sigma-Delta Modulation (SDM)
Putting an integrator in front of the Delta Modulator reduces its distortions - the low-frequency signal components are amplied which makes life easier for the delta modulator because the signal auto-correlation is increased. This combination is called sigma-delta modulator (g. 4.8a). Furthermore, demodulation is simplied as the sigma-delta data stream does not need to be integrated - a DAC (which in its simplest implementation could be just a logic buffer) and a low-pass lter are sufcient. The lter specications can be quite relaxed as the sampling frequency has to be much higher than the signal bandwidth. Implementation is further simplied by moving the integrator behind the comparator, cancelling the integrator in the feedback path (g. 4.8b). Due to this implementation, the SigmaDelta Modulator is also called Delta-Sigma Modulator, however, the transfer functions are identical. Again, due to the feedback loop, quantization noise is concentrated at higher frequencies. Sigma-Delta Modulation is also used in a purely digital architectures: Here, the modulator takes a digital signal with high bit resolution and converts it into a signal with higher sampling rate (oversampling) and lower bit width (g. 4.9a). A very efcient implementation is achieved by swapping quantizer and delay stage (g. 4.9 b+c): the delay stage is drawn into the digital integrator, cancelling the delay in the feedback path. This structure is the classical accumulator (g. 4.10), containing an adder and a register (= delay). The transfer function in the z-domain has a 1 z1 term in the denominator, indicating integrating behaviour; the z1 term in the numerator mirrors the latency time of one sample.
60
Fractional-N PLLs
SigmaDeltaModulator (analog)
s(t)
+1
SigmaDeltaDemodulator
dq(n) s(t)
f
Integrator
Quantizer
Sampler
DAC
LPFilter
a)
Integrator
DAC
s(t)
+1
dq(n)
1 f
s(t)
Integrator
Quantizer
Sampler
DAC
LPFilter
b)
DAC
Figure 4.8: Analog-to-Digital Converter using sigma-delta modulation
Digital accumulators bring the quantizer for free - the carry overow bit can be regarded as MSB, signalling the upper half of the signal range. Another implementation for the integrator with less latency is shown in g. 4.11 - note that there is no z1 term in the numerator. Exactly as with the analog integrator, its digital counterpart can overow / saturate (depending on the implementation). In the digital domain, there is a simple remedy is much simpler: increase the word length of the accumulator to achieve a wider range. So far, weve only used a handwaving approach, declaring that the quantization of the DSM stream dq (n) is high-pass shaped. In order to look at things a little more closely, we replace the accumulator by its transfer function (g. 4.12). To simplify things even further, we substitute the quantizer by adding the quantization noise en to the original signal. We have not made any assumptions on the spectral shape of the quantization noise yet. The digital output stream is dq (z) = (s(z) dq (z)) = s(z) z1 + en (z) 1 z1 1+
= s(z)z1 + en (z) 1 z1
noise shaping
z1 + en (z) 1 z1
z1 1 z1
(4.2.5)
The resulting bit stream contains the input signal, delayed by one sample (Hs (z) = z1 ), plus the quantization noise en , shaped with Hn = 1 z1 . Hn is the transfer function of a differentiator which suppresses slow changes of en (i.e. low frequencies) by taking the difference between two consecutive samples. The frequency response of this time-discrete transfer function is calculated by replacing the discrete frequency variable z by e j Ts : Hn e j Ts = =
Christian M nker u
1 e j Ts = |1 cos Ts j sin Ts | (1 cos Ts )2 + sin2 Ts

December 20, 2005
61
Modulator s(n)
+1
Demodulator
z1
Delay
dq (n)
dig
f
s(n)
z 1
Quantizer
Filter / Downsampler
a)
Accumulator
s(n)
z 1
z1
+1 1
dq (n)
Quantizer
b)
Accumulator
s(n)
c)
z1
+1 1
dq (n)
Quantizer Accumulator
Figure 4.9: Digital delta-sigma modulation

s(n+1) s I(n+1) s I(n)
z 1
z 1
sI (n) s(n)
s I(n)
s(n+1) s I(n+1)
z1 1 z1
z 1
Figure 4.10: Digital integrator (one sample delay)
= =
2 2 cos Ts = 2 sin
4 sin2
Ts 2
(4.2.6)
Ts f = 2 sin 2 fS
(4.2.6) shows that the quantization noise at the SDM output is indeed high-pass shaped in the frequency range 0 . . . fS /4. At fS /2 the noise transfer function becomes zero again, it repeats with a period of fS /2. The total noise power depends on bandwidth of interest fB :
+ fB fB
2 n ( fB ) =
2 Hn ( f ) Se ( f ) d f
= =
+ fB
2 sin
fB
f fS
2 e df fS + fB fB
December 20, 2005
2 4e f 2 f fS sin fS 2 4 fS
Christian M nker u
62
Fractional-N PLLs
Digital Integrator (no delay)

s(n+1) s I(n+1)
s I(n)
z 1
sI (n) s(n)
1 1 z1
Figure 4.11: Digital integrator (no delay)

s(n) z1 1 z1
Accumulator
+1 1
dq (n)
Quantizer
s(n)
en (n) dq (n)
z1 1 z1
Accumulator Quantizer
s(n)
z1
en (n) (1z1)
dq (n)
Noiseshaping
Figure 4.12: Digital delta-sigma modulation - equivalent represenation for quantization noise
2 2e 2 fB 2 fB sin fS fS
(4.2.7)
x applying the identities sin2 x +cos2 x = 1 and 1cos x = 2 sin2 2 . The interpretation of (4.2.7) is easier when regarding two extreme cases - the noise power over the whole baseband interval 0 . . . fS /2 and within a more practical bandwidth fB fS /2:
Full baseband bandwidth: fB = fS /2: In this case, the sin(. . .) part in (4.2.7) becomes zero and the total noise power is:
2 2 n ( fS /2) = 2e
(4.2.8)
The result is the same as (xxx) which means the noise has only been shifted from low frequencies to higher frequencies (noise shaping), but the total noise power has not been reduced. However, the quantized noise can be ltered out more effectively: Narrow signal bandwidth: fB fS /2: In order to get a useful result, the sine function is approximated by x x3 /6 (Taylor series):
2 n ( fB
fS /2)
2 fB fB 1 2e 2 2 + Ts Ts 6
2 fB fS
2 2 e 2 fB 3 fS
(4.2.9)
Here, oversampling improves the SNR by 30 log fB / fS , compared to a meager 10 log fB / fS for a system without noise shaping (4.2.3).
63
4.2.4
Different Architectures for Sigma-Delta Modulators
A plethora of different structures and architectures has evolved since the beginnings of the sigma-delta modulator. [NSE97] gives a good overview, here, only a few examples will be shown:
+1 1
x(n)
z1
z1
xd(n)
Quantizer
Figure 4.13: Second order digital sigma-delta modulator The SDM in g. 4.13 has a latency of one clock cycle, here, the most signicant bit is stripped by the quantizer and passed on to the output. It is scaled and fed back into the modulator.
D(n)
+1 1
x(n)
x2 z1
z1
xd(n)
Quantizer D(n) MSB(n)
Figure 4.14: Second order digital sigma-delta modulator The SDM in g. 4.14 has a latency of zero clock cycles which has advantages for some applications. The quantizer simply strips off the most signicant bit MSB(n), the rest, i.e. the truncation error D(n) - MSB, is fed back into the modulator. Its transfer function is given by H(z) = z1 2 z1 It is stable for an input range of xxx.
4.2.5
Performance Comparison
The single-loop quantizers have two important drawbacks: due to the limited input range there are issues with instabilities and they also susceptible to tones. On the other hand, a drawback of cascaded quantizers (MASH) is the requirement for a multi-bit DAC resp. multi-modulus prescaler. These multi-bit converters are more prone to non-linearities than their one-bit counterparts. The noise shaping properties of these two types are also different [Rhee2000]: MASH quantizers have a higher corner frequency for the noise transfer function but create more quantization noise at higher frequencies. This may be a problem for some wideband applications. Other Applications of SDM Multipliers / Attenuators: A digital multiplier for a multi-bit signal has a large hardware complexity - so why not convert the multi-bit signal to an oversampled one-bit stream? Multiplication of a one bit signal with a constant c is implemented as a multiplexor, switching between c and +c (g. xxx).
Christian M nker u
December 20, 2005
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Fractional-N PLLs
Christian M nker u
December 20, 2005
Chapter 5
PLL Modeling and Simulation

All models are wrong; some models are useful. W. Edwards Denning, Statistician, 1900-1986
The simulation of PLLs is a challenging task due to the large range of time constants in a typical loop. A frequency synthesizer for wireless applications may e.g. have an output frequency of 4 GHz (T = 250 ps), a reference frequency of 26 MHz and a loop lter corner frequency of 100 kHz ( = 15.9 s). In order to verify spectral purity, the loop lter voltage has to calculated with a precision of a few V. Classical mixed-signal simulation can be very time consuming, a faster method is to apply the event-driven approach well-known from digital simulation. This approach is well suited to the growing digital complexity of frequency synthesizers and clock and data recovery circuitry. The analog building blocks in the PLL have to be described in a format suitable for event-driven simulation. This will be described in the next sections:
5.1 Loop Filter

In most PLLs, the loop lter is a continuous-time, continuous-valued element (g. 5.1). In order to simulate the lter in a digital environment which is time-discrete and discrete valued, it has to be modeled as a digital lter. This can be done by translating its transfer function from the s-domain into the z-domain using the bilinear transform [Proakis, pp. 628-630]. The transformation gives the transfer function for a sampled lter with continuous-valued coefcients which is exactly what you need for modeling purposes: in VHDL or Verilog, the coefcients can be dened as real constants with almost arbitrary resolution. If you want to implement such a lter on silicon for an all digital PLL, you need to quantize the coefcients and input values as well. The trade-off between word length (i.e. resolution) and silicon resources (i.e. required area / maximum speed) can be very tricky and is not described here.
5.1.1
Bilinear Transform
The general transfer function of a lter in the s-domain is given by (factored or summation form): 65
66
to VCO VPD= ICPR1 I CP= VPD / R1 R1 R2 R3
C1 R1
C2
C3
PD (voltage mode)
PD/CP
(current mode)
3rd pole 2nd pole 1st pole
Figure 5.1: Non-Integrating Loop Filters
H(s) =
k=1 N
s sk s sl
k=0 N
sk sk ; sl sl MN (5.1.1)
l=1
l=0
where sk are the zeros and sl the poles of the lter. The z-domain is used to describe dicrete-time processes. The so called bilinear transform can be used to map the s-domain onto the z-domain:
Bilinear Transform
s 2 TS z1 z+1 = 2 TS 1 z1 1 + z1 (5.1.2)
where TS is the sampling period of the discrete-time domain. This conformal mapping maps the j axis onto the unit circle in the z-domain, the left half plane is mapped into the inner part of the circle, the right half plane onto its outer part. Applying this transform gives the transfer function for a corresponding discrete-time (or digital) lter:
M
H(z) =
1 + ak zk
k=1
k=0 N
bk zk ; M N (5.1.3)
The number of poles N (the order of the lter) is the same as as in the continous-time representation but the number of zeros M can be different. (5.1.3) describes the general transfer function of a lter in the z-domain. This lter can be realized effectively as a so called IIR (innite impulse response) structure. (5.1.3) can be realized as a cascade of two systems H(z) = H1 (z)H2 (z) (5.1.4)
where H1 (z) contains all the zeros and is an FIR system, H2 (z) describes an IIR system, containing all the poles of H(z):
5.1 Loop Filter
67
vin(n)
H1(z)
b0
H 2 (z) z -1
b1 -a 1
out
(n)
z -1
z -1
b2 -a 2 -a N-1
z -1
b M-1
z -1
bM
-a N
z -1
Figure 5.2: Realization of an IIR lter in direct form I
. H1 (z) = . H2 (z) =
k=0
bk zk
1
(5.1.5) (5.1.6)
1 + N ak zk k=1
When H1 (z) is placed before H2 (z) in the signal path, the realization will look like g. 5.2, it is called direct form I. Placing H2 (z) before H1 (z) gives a structure called direct form II (g. 5.3) that is more efcient because it needs less delays (i.e. registers).
v (n)
in
H 2 (z) z -1
-a 1 -a 2
H1(z)
b0 b1 b M-1
out
(n)
z -1
-a N-1 bM
-a N
z -1
Figure 5.3: Realization of an IIR lter in direct form II The transformation procedure will be demonstrated in detail for a simple RC lowpass:
5.1.2
1st Order Low Pass
A rst order RC lowpass with the transfer function

68
vout (s) 1 = vin (s) 1 + sC1 R1 can be transformed into a digital lter using the bilinear transform: H(z) = = 1 + k11 = vout (n) 1 = 2C1 R1 vin (n) 1 + TS 1
1z1 1+z1 z1 z+1
(5.1.7)
. 2C1 R1 with k11 = TS
1 + z1 1 + k11 + z1 (1 k11 ) 1 + z1 1 + a11 z1
= K1
. with K1 =
1 . and a11 = K1 (1 k11 ) 1 + k11
(5.1.8)
This low pass can be easily realized using a direct form II structure (g. 5.4).
vin(n)
K
H 2 (z) z
-a 1
-1
H1(z)
b0 = 1 b1 = 1
vout (n)
Figure 5.4: IIR implementation of 1st order RC low pass This structure can be translated into VHDL or Verilog quite easily, where z1 is the delay of one sample interval Ts :
5.1.3
2nd Order Low Pass
A second order low pass with the transfer equation 1 vout (s) = 2 +k s+1 vin (s) k22 s 21 with k21 = R1C1 +R1C2 +R2C2 and k22 = R1 R2C1C2 (5.1.9)
is mapped onto the z-plane in a similar way as the 1st order low pass: H(z) = = = vout (n) = vin (n) k22 1
z1 2 z1 + k21 z+1 z+1 2
+1
(z + 1)
k22 (z 1)2 + k21 (z 1) (z + 1) + (z + 1)2
z2 + 2z + 1 z2 (k22 + k21 + 1) + z (2 2k22 ) + k22 k21 + 1 z2 + 2z1 + 1 a22 z2 + a21 z1 + 1 (5.1.10)
= K2
with K2 and
Christian M nker u
a22
1 2 2 , k21 = k21 , k22 = k22 k22 + k21 + 1 TS TS = K2 (k22 k21 + 1) , a21 = K2 (2k22 + 2) =
December 20, 2005
5.1 Loop Filter
69
5.1.4
Third Order Low Pass
A third order low pass with the transfer equation vout (s) vin (s) k32 and k31 1 k33 s3 + k32 s2 + k31 s + 1
with k33 = R1 R2 R3C1C2C3 ,
= C1C2 R1 R2 +C1C3 R1 R2 +C1C3 R1 R3 +C2C3 R1 R3 +C2C3 R2 R3 = R1C2 + R2C2 + R1C3 + R2C3 + R3C3 + R1C1
is transformed into a digital lter exactly as in the previous sections: H(z) = K3 b33 z2 + b32 z2 + b31 z1 + 1 a33 z3 + a32 z2 + a31 z1 + 1 (5.1.11)
with K3 a33 a31
= K3 (3k33 k32 + k31 + 3) and b33 = 1, b32 = b31 = 3
1 2 3 2 2 , k33 = k33 , k32 = k32 , k33 + k32 + k31 + 1 TS TS = K3 (k33 + k32 k31 + 1) , a32 = 3K3 (k33 k32 k31 + 3) , =
k31 = k31
2 TS
5.1.5
Integrating Loop Filters
Integrating loop lters for PLLs are usually implemented together with a charge pump and a tristate phase detector. They have a pole at the origin and at least one zero in the transfer function to keep the loop stable (g. 5.5). Their transfer function can be converted to the z-Domain using the same method as described
a: Charge Pump b: Active Integrator
2nd order C1 R3 PD/CP C2 C1 R2 3rd order 2nd order 1st order PD C3 to VCO 1st order R1 C2 R2
+
R3 3rd order
to VCO
C3
Figure 5.5: Integrating Loop Filters above: vout (s) = xxx vin (s) (5.1.12)
5.1.6
Loop Filter Modeling in VHDL
The following listing shows the basic implementation of a non-integrating IIR lter in VHDL which is more or less self-explanatory: Common d e c l a r a t i o n s
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c o n s t a n t TS
: r e a l : = r e a l ( TS 2 / f s ) 5 . 0 e 16; 1 / 2 s a m p l i n g i n t e r v a l
c o n s t a n t TSS : r e a l : = TS TS ; TS 2 c o n s t a n t TSSS : r e a l : = TS TS TS ; TS 3 f i r s t o r d e r f i l t e r c o n s t a n t s c o n s t a n t k11 : r e a l : = R1 C1 / TS ; c o n s t a n t K1 : r e a l : = 1 . 0 / ( k11 + 1 . 0 ) ; c o n s t a n t a11 : r e a l : = (k11 + 1 . 0 ) K1 ; c o n s t a n t b11 : r e a l : = 1 . 0 ; s e c o n d o r d e r f i l t e r c o n s t a n t s c o n s t a n t k22 : r e a l : = R1 R2 C1 C2 / TSS ; c o n s t a n t k21 : r e a l : = ( R1C1 + R1C2 + R2C2 ) / TS ; c o n s t a n t K2 : r e a l := 1 . 0 / ( k22 + k21 + 1 . 0 ) ;
c o n s t a n t a22 : r e a l : = ( k22 k21 + 1 . 0 ) K2 ; c o n s t a n t a21 : r e a l : = ( 2 . 0 k22 + 2 . 0 ) K2 ; c o n s t a n t b22 : r e a l : = 1 . 0 ; c o n s t a n t b21 : r e a l : = 2 . 0 ; t h i r d o r d e r f i l t e r c o n s t a n t s c o n s t a n t k33 : r e a l : = C1 C2 C3 R1 R2 R3 / TSSS ; c o n s t a n t k32 : r e a l : = ( C1C2R1R2+C1C3R1R2+C1C3R1R3 + C2C3R1R3 + C2C3R2R3 ) / TSS ; c o n s t a n t k31 : r e a l : = ( R1C2+R2C2+R1C3+R2C3+R3C3+R1C1 ) / TS ; c o n s t a n t K3 : r e a l : = 1 . 0 / ( k33 + k32 + k31 + 1 . 0 ) ; c o n s t a n t a33 : r e a l : = ( k33 + k32 k31 + 1 . 0 ) K3 ; c o n s t a n t a32 : r e a l : = ( 3 . 0 k33 k32 k31 + 3 . 0 ) K3 ; c o n s t a n t a31 : r e a l : = ( 3.0 k33 k32 + k31 + 3 . 0 ) K3 ; c o n s t a n t b33 : r e a l : = 1 . 0 ; c o n s t a n t b32 : r e a l : = 3 . 0 ; c o n s t a n t b31 : r e a l : = 3 . 0 ; IIR : process ( s c l k ) begin i f s c l k e v e n t then B a s i c I I R f i l t e r
F i l t e r D e f i n i t i o n : uncomment t h e n e e d e d p a r t F i r s t Order F i l t e r ( no z e r o )
5.1 Loop Filter
71
mem1 <= CPval K1 a11 mem1 ; v t u n e <= CPval K1 a11 mem1 + b11 mem1 ; S e c o n d Order F i l t e r ( no z e r o ) mem2 <= mem1 ; mem1 <= CPval K2 a21 mem1 a22 mem2 ; v t u n e <= CPval K2 a21 mem1 a22 mem2 + b21 mem1 + b22 mem2 ; T h i r d Order F i l t e r ( no z e r o ) mem2 ; mem1 ; CPval K3 a31 mem1 a32 mem2 a33 mem3 ; CPval K3 a31 mem1 a32 mem2 a33 mem3 + b31 mem1 + b32 mem2 + b33 mem3 ; end i f ; e v e n t end p r o c e s s I I R ; The lter calculation is performed each time the clock signal s_clk changes (s_clkevent), i.e. twice per clock period. This clock is a kind of ticker, it is dened in yet another process (also not shown). The clock frequency should be 10x ... 20x higher than the maximum input frequency. Choosing a higher oversampling ratio improves the accuracy somewhat, however, a lot of events are generated which slow down simulation. CPval is the state of the charge-pump (current multiplied with the input resistor of the lter) or of the phase detector (voltage output). CPval is calculated in an extra process, here, nonlinearities of the charge-pump etc. can be incorporated if needed. mem1 etc. are the registers (z1 in the block diagrams). Values are shifted from mem1 to mem2 to mem3, the calculations are performed from top to bottom and from right to left. The sampling principle of the lter can be major problem in a PLL - this is true for an alldigital PLL as well as for a behavioral simulation using a digital lter model. The reason for this is that the lter has to run on a xed sampling period TS 1 while the charge pump can basically switch at any time. This means, the lter will notice a change at the charge pump output only with a delay of TS /2 in average. This is equivalent to the phase detector / charge pump having an average timing error of TS /2 which has an disastrous effect for many systems unless you choose a very small sampling period. Youll see some kind of beat frequency effect as the PWM signal of phase detector interferes with the sampling period. At least for behavioral modelling there is a solution: measure the time between the switching of the phase detector / charge pump and the next sampling clock event and relate it to the sampling period (fractional period). Then scale the lter input with this value - et voil ! a This means, you translate the timing error into an amplitude error which can be handled by the lter: I I R f i l t e r w i t h c o r r e c t i o n o f s a m p l i n g e r r o r
1 Ok,
mem3 mem2 mem1 vtune
<= <= <= <=
it is possible to use non-equidistant sampling, but youll be in REALLY deep water ...
Christian M nker u
December 20, 2005
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IIR : process ( s c l k , CP i ) variable TS frac v : real ; f r a c t i o n a l t i m e s t e p : e v e n t d e l t a t i m e r e l a t i v e t o s a m p l i n g p e r i o d
variable T last v : time ; t i m e o f l a s t c a l c u l a t i o n variable f r a c f la g : b o o l e a n ; f r a c t i o n a l c y c l e ? v a r i a b l e f r a c f l a g d : b o o l e a n ; f r a c t i o n a l c y c l e ( p r e v i o u s ) ? begin i f s c l k e v e n t or CP i e v e n t t h e n i f ( now T l a s t v < T S 2 t ) f r a c t i o n a l c y c l e : t i m e i s l e s s t h a n TS : T s f r a c v : = r e a l ( ( now T fracflag := t r u e ; i f CP i = 0 then CPval <= T s f r a c v CP else CPval <= ( 1 . 0 T s f r a c end i f ; CP i else n o r m a l c y c l e i f CP i = 1 then CPval <= CP DC c ; else CPval <= 0 . 0 ; end i f ; CP i fracflag d := f r a c f l a g ; fracflag := f a l s e ; end i f ; t i m e s t e p i f not f r a c f l a g d then T l a s t v : = NOW; don t s t o r e t i m e s t e p i f t h e l a s t one was a f r a c t i o n a l one o t h e r w i s e t h i s c y c l e would be c a l c u l a t e d t w i c e . . . end i f ; i f n o t f r a c f l a g end i f ; e v e n t end p r o c e s s I I R ; then since last event l a s t v ) / f s ) / r e a l ( ( TS 2t ) / f s ) ; CP h a s j u s t s w i t c h e d o f f DC c ; CP h a s j u s t s w i t c h e d on v ) CP DC c ;
s t o r e l a s t f r a c f l a g r e s e t f r a c f l a g
5.1.7
Loop Filter Modeling Using Exponential Functions
Alternatively, the Laplace Transform can be used to calculate the step response of a lter:
5.2 VCO Modeling
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5.2 VCO Modeling

The efciency of VCO is increased tremendously by ignoring the amplitude information and regarding only the zero crossings. The following simple VHDL model calculates the ideal VCO period in fs. The result is scaled with a scaling factor fres which can be used to improve the resolution (see below). Last cycles truncation error is added to the current period to avoid accumulation of the error as this would give a period error of ca. 0.5fs (see section 5.3). B e h a v i o r a l VCO model ( e x c e r p t ) ... b e g i n p r o c e s s FREQ GEN v c o o u t <= 0 ; p e r i o d t <= 300 p s f r e s ; p e r i o d e r r v := 0 . 0 ; VCOLoop : l o o p <= t r a n s p o r t 1 a f t e r VCODelay , 0 a f t e r p e r i o d t / 2 + VCODelay ; wait for p e r i o d t ; vco out period v := f r e s / ( ( f 0 + kvco v t u n e i ) 1 . 0 e 15) + period err v ; p e r i o d i n f s
p e r i o d t <= ( p e r i o d v ) f s ;
c a l c u l a t e t r u n c a t i o n e r r o r : p e r i o d e r r v := period v r e a l ( ( period v f s ) / f s ) ; c a l c u l a t e d e v i a t i o n f r o m t a r g e t f r e q u e n c y : delta f <= 1 . 0 e15 / p e r i o d i d v f r e s f t a r g ; end l o o p VCOLoop ; end p r o c e s s FREQ GEN ; v c o o <= v c o o u t ;
5.3 Accuracy Limitation of Sampled / Quasi-Analog Models

The sampled nature of a digital simulator puts a limit to the achievable simulation accuracy. Lets have a look at the consequences:
5.3.1
Amplitude Quantization
Real numbers in VHDL are represented with double accuracy (64 bits) according to ANSI/IEEE Std 754-1985 (1 sign bit [S], 11 bits for the exponent [EXP], 52 bits [m] for the mantissa). The value of such a real number is calculated from: VALUE = (1)S 2EXP1023 1. mmm . . . m
52 bits
74
The 52 bits m of the mantissa (the fraction) have been normalized to have an integer part of 1, representing values in the range 1 . . . 2 252 . As the normalized mantissa always has an integer part of 1, it can be omitted in the binary representation (hidden bit normalization), increasing the accuracy by one bit. The resulting accuracy of the fraction is
= 252 2.2 1016 ,

corresponding to approximately 16 decimal digits of accuracy. The 11 bits for the exponent are biased with -1023, so the range of values is 21023 . . . 221024 . In the decimal system, this corresponds to 1.1 10308 . . . 3.6 10308 . The gap between a number x and the next representation depends on the exponent, it is x = 2EXP1023 . This numerical range and accuracy is equivalent to analog simulators like Matlab or Spice (which usually use the same binary representation), it should be more than sufcient for most requirements.
5.3.2
Timing Quantization
In VHDL, events are timed using a 64 bit integer variable. The minimum timestep is T = 1 fs, the corresponding maximum time event takes place after 263 fs 2 1/2 hrs. This quantization creates a timing error Terr,q < T : if timing events are derived from calculations in real format (see VCO model), the truncation will create the event a fraction of a fs earlier than calculated: Tqu = Tid . For autonomous (oscillating) systems, this timing error translates into a frequency error ferr :
Frequency error due to timing quantization

ferr = fqu fid = 1 + Terr,q /Tid Terr,q 1 1 T 1 = 2 < 2 Tid Terr,q Tid Tid Tid Tid Tid (5.3.1)
The average timing error can be brought to zero, giving a correct average frequency, e.g. by summing up the error and correcting it in the next cycle. However, this correction will create additional jitter with a uniform distribution in the range T /2 . . .+T /2 with an RMS timing error of T /(2 3). Usually, its spectrum is white up to the signal frequency (cyclostationary noise). In a rst order approximation2 , this jitter is white PM noise (driven blocks) or FM noise (autonomous blocks).
E XAMPLE 3: Timing quantization error

A VCO model runs with a frequency near 4.0 GHz, corresponding to a period of 250 ps. During the generation of the timing event, the fractional part of the period (in fs) is truncated. This means, the period is always a little short - on average3 by T /2 = 0.5fs. The resulting frequency error ferr is (5.3.1) ferr
2 assuming 3 Only
1 fs T = = 8 kHz 2 2 (250 ps)2 2Tvco,id
the error is uncorrelated a crude approximation, the actual error depends on the period duration: when the VCO e.g. runs with exactly 4 GHz, there will be no truncation error.
Christian M nker u
December 20, 2005
5.4 Noise Modeling The resulting jitter is in the range of 0.5fs, with a sigma of T /(2 3) 0.29 fs. Referred to Tvco = 250 ps, the unit interval jitter is JUI,rms 1.2 106 . This jitter is white FM noise with a PSD of ca. -134 dBc (1Hz) at 1 MHz offset.
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5.4 Noise Modeling

5.4.1 Event Driven Approach
In event-driven languages like Verilog or VHDL, phase noise can only be represented in the time domain i.e. as jitter. Therefore, the rst step has to be to transfer phase noise specications from the frequency into the time domain. This is not an easy task and is described for some special cases in chapter 9.
Randon Number Generation A random number source with a well dened characteristic is needed to model random processes. Most programming languages offer some sort of pseudo-random number generator but its quality may be not sufcient for high-resolution simulations. Next, a simple modulus arithmetic algorithm is described that produces pseudo-random sequences with a length of 23 1 2 and is suitable for 32 bit integer arithmetic. The random seeds may be odd or even. . x(n) = 75 x(n 1) mod (231 1) (5.4.1)
PROCEDURE u n i d i s t PURPOSE : G e n e r a t e an u n i f o r m l y d i s t r i b u t e d number stream in t h e range [ 0 , 1 ) A l g o r i t h m t a k e n f r o m : The A r t o f Computer S y s t e m s P e r f o r m a n c e A n a l y s i s , R . J a i n 1991 ( p . 4 4 3 ) h t t p : / / www . d e e p c h i p . com / p o s t s / 0 1 2 6 . h t m l Mark G o n z a l e s o f I n t e l Usage ( s e e d 1 v and r a n d 1 v a r e o v e r w r i t t e n i n e a c h s t e p ) : v a r i a b l e s e e d 1 v : i n t e g e r := 1 2 3 ; i n i t i a l s e e d v a r i a b l e r a n d 1 v : r e a l ; o u t p u t . . . u n i d i s t ( s e e d 1 v , r a n d 1 v ) ;
Christian M nker u
December 20, 2005
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procedure u n i d i s t ( variable seed : inout i n t e g e r ; variable X : out real ) is constant constant constant constant constant variable variable variable a : integer m : integer q : integer r : integer : real m real seed div q : integer seed mod q : i n t e g e r : integer new seed := := := := := ; ; ; 16807; 2147483647; 127773; 2836; r e a l (M) ; = = m m 75 231 1 DIV a MOD a
begin s e e d d i v q := seed / q ;
t r u n c a t i n g i n t . d i v i s i o n m o d u l u s s e e d m o d q : = s e e d mod q ; new seed := a seed mod q r s e e d d i v q ;
i f ( new seed > 0) then seed := new seed ; e l s e s e e d : = n e w s e e d + m; end i f ; X := r e a l ( seed ) / m real ; end u n i d i s t ; An alternative in VHDL would be to use RAND() / GET_RAND_MAX() from the MATH_REAL package to get a uniformly distributed pseudo-random number. Use SRAND(seed) to seed a new random stream. However, sequence length is unknown, which might create false periodicities. The superposition of many microscopic uniform processes results in a macroscopic process with gaussian distribution (central limit theorem). Therefore, one way to generate a gaussian distributed random process is to generate some uniformly distributed samples and calculate their average. For most applications, superposition of ten samples should be enough to obtain one sample of a Gaussian process. One drawback of this approach is that the effective sequence length of the resulting Gaussian process is only one tenth of the uniform process, another one is of course the increased computational effort. Another aproach is described in [PM96], where two uncorrelated uniform processes x1 (n), x2 (n) are transformed into two uncorrelated gaussian processes xn,1 (n), xn,2 (n). First, one of the processes is transformed into a random process xR,1 (n) with Rayleigh distribution: xR,1 (n) := 2 log 1 1 x1 (n) (5.4.2)
Two processes with Gaussian (normal) distribution (m = 0, = 1) can be derived from xR,1 (n) and x2 (n): xn,1 (n) = cos(2 x2 (n)) xR,1 (n) xn,2 (n) = sin(2 x2 (n)) xR,1 (n) (5.4.3) (5.4.4)
The average value and standard deviation of xn,1 (n), xn,2 (n) is easily changed by adding an offset m resp. scaling with a factor . The computational effort for calculating the transcenChristian M nker u Phase Noise and Spurious Sidebands in Frequency Synthesizers v3.2 December 20, 2005
5.4 Noise Modeling
77
dental functions sqrt(), log(), sin() and cos() is quite high but at least the sequence length is not reduced. PROCEDURE n o r m d i s t Usage : s e e d and norm m u s t be v a r i a b l e s , n o t c o n s t a n t s ! ... n o r m d i s t ( s e e d 1 v , s e e d 2 v , s i g m a 1 c , m c1 , norm1 v , s i g m a 2 c , m c2 , norm2 v ) ; procedure n o r m d i s t ( variable seed1 : inout i n t e g e r ; variable seed2 : inout i n t e g e r ; c o n s t a n t sigma1 : in r e a l ; c o n s t a n t m1 : in r e a l ; v a r i a b l e norm1 : o u t real ; c o n s t a n t sigma2 : in r e a l ; c o n s t a n t m2 : in r e a l ; v a r i a b l e norm2 : o u t real ) is S e e d f o r 1 s t r n d number S e e d f o r 2 nd r n d number Sigma 1 Avg . 1 n o r m a l l y d i s t r i b u t e d Sigma 2 Avg . 2 n o r m a l l y d i s t r i b u t e d o u t p u t v a r i a b l e
c o n s t a n t TWO PI c : r e a l : = 2 . 0 MATH PI ; variable rrand : r e a l := 0 . 0 ; R a y l e i g h d i s t r i b u t e d random numb . i n t h e r a n g e [ 0 , 1 ) variable rand1 : r e a l ; u n i f o r m l y d i s t r i b u t e d variable rand2 : r e a l ; random v a r i a b l e s begin u n i d i s t ( seed1 , rand1 ) ; u n i d i s t ( seed2 , rand2 ) ; R a y l e i g h d i s t r i b . norm1 : = m1 + s i g m a 1 COS( TWO PI c r a n d 2 ) r r a n d ; norm2 : = m2 + s i g m a 2 SIN ( TWO PI c r a n d 2 ) r r a n d ; end n o r m d i s t ; White Noise In the simplest case, phase noise has a white spectrum and a gaussian distribution. It is specied by a single gure in the frequency domain because the power spectral density (PSD) is constant over frequency. Correspondingly, in the time domain the jitter is completely described by its standard deviation . In spite of its simplicity, this noise / jitter model describes many real-world systems with sufcient accuracy. The reason for this is that added white gaussian noise is such an omnipresent phenomenon that it was even awarded an own acronym (AWGN). AWGN is translated into timing error (or jitter) by nearly every signal
r r a n d : = SQRT ( 2 . 0 LOG ( 1 . 0 / ( 1 . 0 r a n d 1 ) ) ) ;
78
processing stage. How can white phase noise be modeled in e.g. VHDL? First well look at non-autonomous blocks like a logic gate or a buffer. These blocks process an event at their inputs and pass it on to the output with a certain latency. This latency depends on the slew rate at the input, the speed of the actual circuit etc. The latency varies in a random fashion due to e.g. thermal noise in the circuit.
5.5 Spectral Estimation of Simulation Results

In contrast to an analog or mixed-signal simulator, there is no easy way to regard simulation results in the frequency domain with a digital simulator. One workaround to this dilemma is described in [Kun98], where the period data of the VCO is written to a text le and analyzed using a MATLAB script. Due to the simplied VCO model, only the VCO period data is available. Spectral data like phase noise and spurious sidebands are contained in the deviations of the zero crossings from ideal times. Summing up the periods yields the output phase of the VCO over time which approximates the ideal VCO phase 2 fvco,id t, a linear slope. However, running a Fourier analysis of this raw phase data is a bad idea because the actual spectral information is smothered by the spectral components of the linear slope, especially at low frequencies4 . A much better resolution is achieved by rst subtracting the linear phase due to the average VCO frequency 2 fvco t which can be extracted easily from the period data. Assuming the PLL is in locked state, the average frequency of the VCO is constant. MATLAB can remove the slope automatically by giving the option detrending for the power spectral density calculation. A basic MATLAB script for analysis of the VCO spectrum looks like this: % Read VCO P e r i o d Data f r o m t e x t f i l e n r e a d = 1; % r e a d a l l s a m p l e s [ v c o p e r i o d s ] = t e x t r e a d ( VCO data . t x t , %f , n r e a d ) ; % C a l c u l a t e # o f s a m p l e s , avg . , max . and s t d . d e v i a t i o n o f p e r i o d s N sample = l e n g t h ( v c o p e r i o d s ) ; % No . o f s a m p l e s T m = mean ( v c o p e r i o d s ) ; % Avg . p e r i o d J m = s t d ( v c o p e r i o d s ) ; % S t d . Dev . o f p e r i o d s s t d d p h i = J m / T m ; % S t d . Dev . o f p h a s e m a x d p h i = max ( abs ( v c o p e r i o d s T m ) ) / T m ; % Max . Dev . o f p h a s e n f f t = 32768; % = 215 winLength = n f f t ; o v e r l a p = f i x ( n f f t / 2 ) ; % 50% O v e r l a p winNBW = 1 . 5 ; rbw=winNBW / ( T m n f f t ) ; % C a l c u l a t e v e c t o r with c u m u l a t i v e phase c u m p h i v c o = 2 p i cumsum ( v c o p e r i o d s ) / T m ; % Remove t h e l i n e a r p a r t o f t h e VCO p h a s e and e s t i m a t e % i t s Power S p e c t r a l D e n s i t y
4A
constant slope in the time domain has a PSD increasing with 60dB / dec towards zero
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December 20, 2005
5.5 Spectral Estimation of Simulation Results
79
[ Sphi VCO , f ] = p s d ( c u m p h i v c o , n f f t , 1 / T m , winLength , o v e r l a p , l i n e a r ) ; N f = length ( f ) ; % A p p l y c o r r e c t s c a l i n g ( 2 D e l t a T / NFFT ) ? ? Sphi VCO = winNBW Sphi VCO / n f f t ; % F i n d maximum and c o r r e s p o n d i n g f r e q u e n c y [ MaxSphi2 VCO , Maxfs2 ] = max ( Sphi VCO ) ; figure (1); clf ; s e m i l o g x ( f ( 2 : N f ) , 10 l o g 1 0 ( S p h i 2 ( 2 : N f ) ) ) ; h o l d on ; x l a b e l ( F r e q u e n c y ( Hz ) ) ; y l a b e l ( S {\ p h i } ( dB [ 1 Hz ] ) ) ; t i t l e ( VCO PSD , . . . f o n t s i z e , 12 , f o n t w e i g h t , bold ) ; The actual estimation of the power spectral density of the dicrete-time VCO phase data is performed using Welchs averaged, modied periodogram method. This method reduces the variance in the spectral estimate at the cost of reduced frequency resolution. [ P XX , f ] = p s d (X, N FFT , Fs , N WINDOW, N OVERLAP , l i n e a r ) ; The time discrete data X is split into sections of length N_FFT, overlapping by N_OVERLAP. An overlap of NFFT/2 (50%) usually gives good results. Each segment is detrended, i.e. the constant linear slope is removed before it is windowed with a Hanning window of length N_WINDOW = N_FFT. The magnitude squared DFTs with length N_FFT of each segment are averaged and stored in the vector P_XX with length NFFT/2. The parameter Fs is only needed to generate the second vector f with the properly scaled frequency data for the x-axis of the PSD - plots. It has the same length as P_XX. Other windowing functions are possible as well, e.g. KAISER(512,5) for a Kaiser window with order 5 and with length 512. Additionally, the condence interval for the PSD can be stored as well by [ P XX , P xxc , f ] = p s d (X, N FFT , Fs , N WINDOW, N OVERLAP , p , l i n e a r ) ; where p is a scalar (range 0 . . . 1, default 0.95) and P_xxc is a matrix with 2 rows containing the p * 100% condence interval for P_xx.
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Part II
Spurious Sidebands
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Chapter 6
Reference Frequency Feedthrough

Musik wird st rend oft empfunden, o dieweil sie mit Ger usch verbunden. a Wilhelm Busch
Overview: In this chapter, the mechanisms of spurious sideband creation are explained using the example of disturbances on the loop lter voltage. After a little modulation theory, the effects of sinusoidal and general periodic disturbances are analyzed. The important cases of DC currents owing into the loop lter and of short error pulses are presented in detail.
6.1 FM / PM Modulation Basics

Spurious sidebands are created by a disturbing signal that somehow interferes with the carrier, creating additional tones besides the carrier. A little modulation theory is needed before diving into the more practical issues of spurious estimation and avoidance. In this chapter, modulation of the VCO tuning voltage by the reference frequency will serve as an example for a disturbing signal because it is a common problem (g. 6.1) and can be analysed in a relative painless way. When e.g. up- and down-pulses are not perfectly synchronized or otherwise mismatched, a net error current ie (t) ows into the loop lter that is periodic with the reference frequency fre f . It is converted by the loop lter impedance ZLF (s) into a voltage error ve (t) of the VCO control voltage (see chapter 2.5.2). At the VCO output, they can be observed as spurious sidebands around the carrier frequency f0 (see g. 1.1) with offsets of k fre f ; k = 1, 2, . . .. In order to analyze the effect of these disturbances, a little modulation theory is needed: The PLL is assumed to be in locked state with a static VCO control voltage VCT RL . The ideal VCO output frequency 0 has a constant part - the base frequency B at zero control voltage - and a tuned part ctrl = 2 KvcoVCT RL . The tuning sensitivity of the VCO describes the relation between a change in control voltage and the resulting change in output frequency. It is given . by Kvco = f0 / vctrl . Kvco is always somewhat dependent on the DC value of the control voltage, Vctrl , but this will be ignored here. In addition to these static components, a small 83
84
f sys
f ref 1 R Reference Divider
PD + CP
Loop Filter f ref

f ref
VCO
f VCO
LODivider 1 D
f out
F(s)
fref
NDivider
f ref = fVCO / N
1 N
Figure 6.1: Spurious generation due to reference frequency leakage

Charge Pump Phase Detector
ref div PD
down i dn up ie i up
Loop Filter
V ctrl + ve
VCO
F(s)
Divider
div= vco N
1 N
vco, vco
Figure 6.2: Block schematic of a PLL
error voltage ve (t) sits on top of VCT RL (|ve | VCT RL , see Fig. 1.1), causing an unwanted frequency modulation of e (t) = 2 Kvco ve (t). The output signal of the VCO is given by:
svco (t) = A cos (Bt + CT RLt + e(t) t) = A cos (0t + e(t) t) = A cos (0t + 2 Kvco ve(t) t) (6.1.1)
showing that ve (t) causes a frequency modulation. The effect of ve (t) can be analyzed more easily when it is given as a phase modulation1 . Frequency modulation is transformed into phase modulation by integrating the modulation signal: e (t) =
t
e ( ) d = 2 Kvco
ve ( ) d
(6.1.2)
Using (6.1.2), the frequency modulation of the VCO (6.1.1) can be expressed as a phase modulation:
1 The reason for this is the term cos(. . . v (t)t . . .) that cannot be expanded using Bessel functions as described in e the appendix.
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December 20, 2005
6.2 Sinusoidal Disturbance of Tuning Voltage
85
svco (t) = A cos (0t + e(t) t) = A cos 0t +

t
e ( ) d
t
= A cos 0t + 2 Kvco = A cos (0t + e (t))
ve ( ) d
(6.1.3)
In the next sections, some typical disturbances of the VCO control voltage caused by reference frequency feedthrough are analysed.
6.2 Sinusoidal Disturbance of Tuning Voltage

We rst look at the case of a sinusoidal modulation signal ve (t) = m cos 1t with amplitude m and frequency f1 : This disturbance can be caused e.g. by e.g. a signal coupling capacitively onto the control voltage or by charge pump pulses, heavily ltered by the loop lter. Using (6.1.2), the phase of the modulating signal is calculated as: (t) = 2 Kvco =
t
m cos 1 d
mKvco sin 1t f1 = sin 1t where
= mKvco / f1
(6.2.1)
(see appendix G.5 about the integration), is called modulation index. In a proper PLL design, disturbances and hence the modulation index are small, in this case the output spectrum can be approximated using the Low Modulation Index Approximation (D.1.3) described in appendix D:
Low Modulation Index Approximation
svco (t) = A cos (0t + sin 1t) cos (0t + 1t) + cos 0t cos (0t 1t) A 2 2
(6.2.2)
The resulting VCO output signal has two new components at f0 f1 with relative levels of: s1 mKvco dBc = 20 log 2 2 f1 2 (6.2.3)
(6.2.3) shows that the modulation effect decreases with the modulation frequency - this is a consequence of the integrating behaviour of the VCO concerning its control signal. The exact spectrum of the VCO output signal is given in the appendix D: (D.1.1) shows that the output signal has additional sideband spurs at k f1 (k = 2, 3, . . .) around the carrier, created by the non-linearity of frequency modulation. In contrast to that, the low-modulation index FM approximation (6.2.2) predicts only sidebands at f1 which is only approximately correct for low modulating indices. Note: Spurious levels in this paper are always given relative to the carrier amplitude A, sometimes with the pseudo-unit dBc (c : carrier). As most spurs are symmetrical with respect
86
to the carrier, usually no difference is being made between lower and upper sidebands, i.e. s+1 = s1 = s1 .
|S 0 (f)|
2 A 0 /2 2 2 A 0 /8 2 A 0 /4 2 2 A 0 /16
|S 00 (f)| A 0 N0 /8
2
A 0 N0 /4
f0f n f 0
f0+f n
f0
f0+f n Double sided
f0
f0+f n
Single sided
Figure 6.3: Comparison of single and double sided notation In this paper, spectra are given in engineering notation, i.e. using only positive frequencies (unless noted otherwise)2 - see also appendix A on this topic. Spectra of real-valued (real life) signals are always symmetric with respect to the 0 Hz point. Engineering spectra are denoted with a single index, mathematical spectra with a double index: S0 ( f ) = 2S00 ( f ) for f 0 This denition ensures that energy / power of engineering and mathematical spectra are the same.
E XAMPLE 4: Spurs caused by a sinusoidal disturbance

The VCO control voltage (Kvco =50MHz/V) is disturbed by a sinusoidal signal with the frequency f1 = 200kHz and amplitude m = 1mV. What does the output spectrum look like? The disturbance causes a frequency modulation of the VCO with a modulation index of = mKvco / f1 = 0.25, producing the rst sideband spurs ( f0 f1 ) at 20 log( /2) = 18dB below the carrier (6.2.3). Due to the nonlinearity of frequency modulation there are also higher order harmonics not predicted by (6.2.2): The exact calculation (D.1.1) gives second order sideband spurs ( f0 2 f1 ) with levels of 20 log( 2 /8) = 42dBc. This means, a modulation index of 0.25 is not low. In order to keep second (and higher) order harmonics below e.g. -100dBc, a modulation index less than = 8 10100/20 = 0.009 is necessary. Using the data above, this corresponds to a maximum amplitude of m = f1 /Kvco = 36 V, producing rst order spurs of 20 log( /2) = 41dBc. Obviously, the VCO input is a very sensitive node in the system!
Note: A low-modulation index FM spectrum is identical to the spectrum of a double side band (DSB) AM signal with an AM modulation index AM = m/A < 1 except for the phase reversal of the lower sideband. However, power spectrum and occupied bandwidth are the same. FM with a high modulation index (e.g. FM radio) has a lot of excess bandwidth due to higher order harmonics. Therefore, low-modulation index FM is also called Narrowband FM:
2 Not
to be confused with positive / negative offset frequencies from the carrier!
Christian M nker u
December 20, 2005
6.3 Periodic Disturbances of Tuning Voltage
87
sAM (t) = A +
AM AM cos (0t 1t) + cos 0t + cos (0t + 1t) 2 2
6.3 Periodic Disturbances of Tuning Voltage

In most cases, disturbances of the loop lter voltage will not be sinusoidal because many signals on-chip are switched signals with a high harmonic content. However, the procedure for calculating the effect of these disturbances is quite similiar to last section: A periodic signal ve (t) with the fundamental frequency f1 can be decomposed into an innite Fourier series (see appendix A): ve (t) =
k=1
ck cos (k1t + k )
where ck is the amplitude of the k-th harmonic and k is its phase. It has been assumed that ve (t) is DC-free (c0 = 0) because a locked PLL compensates static and slow3 changes of the VCO output frequency 0 . The spurious sidebands created by such a signal can be calculated in a similiar fashion as for sinusoidal disturbances: each harmonic of the modulating signal is upconverted around the carrier separately (g. 6.4).
|S mod (f)| |S (f)| vco |S vco,mod (f)|
x
f fref 2fref f0 f
=
f f0f ref f0 f0+f ref
Figure 6.4: Periodic Disturbance of Control Voltage However, this is only allowed for low modulation indices where frequency modulation behaves in a nearly linear way and superposition can be applied. At the VCO output, the amplitude of the k-th harmonic is attenuated by 1/k f1 due to the integrating behaviour of the VCO: svco (t) = A cos 0t + where
k (cos (0t + (k1t + k )) cos (0t (k1t + k ))) k=1 2

Kvco ck k f1 (6.3.1)
k =
is the modulation index for the k-th harmonic. A periodic disturbance of the VCO control voltage with fourier coefcients ck produces spurious sidebands with relative levels sk of
Spurious Sidebands Caused by Periodic Disturbance

sk
3 frequencies
k Kvco ck = 2 2k f1
; k = 1, 2, . . .
(6.3.2)
within the loop bandwidth.
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December 20, 2005
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(6.3.2) allows an easy simulation / calculation of the spurious sidebands of a locked PLL: Run a transient simulation of the PLL long enough until it is in locked state. Run a Fourier analysis on the VCO control voltage waveform. This gives the ck s. Multiply ck by Kvco /(2k fre f ) to obtain the relative amplitude of the k-th spurious sideband. In contrast to that, it is nearly impossible to obtain this result directly from the VCOs phase with a harmonic balance or periodic steady-state analysis, especially when analyzing a frequency synthesizer with a high ratio between VCO and reference frequency: many reference cycles are needed before the PLL is locked and the phase error is low enough to start a fourier analysis. In periodic steady state analysis, the simulation needs to cover at least one cycle of the lowest frequency in the circuit (reference frequency in this case) which takes a lot of computing time as many VCO cycles have to be simulated in the same time. Achieving a locked state in a periodic steady state analysis is therefore impossible with the average computing power available today.
6.4 Sidebands Induced By DC Leakage Current

When a DC error current ie (t) = IL ows into an integrating loop lter (Type II PLL)4 , the output voltage ve (t) will be a ramp (see g. 6.5), reset by the PD/CP every Tre f . A DC leakage current can be caused e.g. by lossy capacitors in the loop lter or ESD damage of the charge pump output. At the reference frequency, the loop lter can be approximated by the equivalent loop lter capacitance C1 (see section 2.5.2) which is approximately equal to the anti-ripple capacitor C1 :
icp (t) IL t Tw
I cp
ve(t) m t Trise Tref
Figure 6.5: Disturbance Caused by DC Leakage Current IL IL t C1
ve (t) =
for
0 t < Tre f
In a closed loop, ve (t) is reduced to zero at the end of each reference cycle (t = Tre f ) by a short charge pump pulse of opposite polarity. If IL ICP , the charge pump pulse is very
4 Type I PLLs are relatively immune to this kind of disturbance because they dont integrate the leakage current here, a DC current merely generates an constant offset that is compensated by the loop.
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December 20, 2005
6.4 Sidebands Induced By DC Leakage Current
89
short and the rise time of the voltage ramp is Trise Tre f , i.e. ve (t) can be approximated by a periodic sawtooth function saw(t) with an amplitude m of m IL Tre f C1 t Tre f 1 2 (6.4.1)
As usually, the DC part (m/2) of ve (t) is suppressed by the locked loop: ve (t) = m saw (6.4.2)
where saw(t) is the periodic sawtooth function with period and amplitude of 1. This requires that the sum of the charges due to IL and ICP is zero over each period: Icp Tw = IL Tre f Tw IL Tre f ck = forTw Tre f
The Fourier coefcients of sawtooth function ve (t) are: m ; k=1,2,... k The level of the VCO output spurious sidebands can be calculated using (6.3.2) with f1 = fre f :
Spurious Sidebands Caused by DC Leakage Current

sk = Kvco m Kvco IL = 2 2f 2 k re f 2 C1 k2 fre f ; k = 1, 2, . . . (6.4.3)
(6.4.3) allows to estimate quickly the effect of design changes, e.g. how much spurious sidebands are reduced by increasing the reference frequency or the loop lter capacitance. Or, how much the leakage current requirements can be relaxed while maintaining the same spurious performance. (6.4.3) also shows once more that a high Kvco makes the system more sensitive to leakage currents into the loop lter (and to modulation effects in general) and should be avoided if possible.
E XAMPLE 5: Spurs due to DC leakage current

An integrating loop lter with the following elements (see g. 2.11) C2 = 5.6nF, R2 = 3.3k C1 = 390pF C3 = 120pF, R3 = 8.2k T2 = 18.5 s ( f2 = 8.6kHz), b = 15.4 T1 = T2 /b = 1.2 s ( f1 = 132kHz) T3 = 1 s ( f3 = 162kHz - post-lter)
is used in a PLL with reference frequency fre f = 200kHz and Kvco = 80MHz/V, the DC leakage current is IL = 80nA. As fre f f2 , the equivalent loop lter capacitance is C1 C1 . The amplitude of the resulting sawtooth voltage (6.4.1) on the loop lter voltage is m 1mV. With this data, the spurious sidebands without a post-lter can be calculated (6.4.3). The attenuation of the post-lter |A3 ( f )| is calculated separately (see section 2.6): Sideband No. Offset Frequency [kHz] Spurious (no post-lter) Spurious [dBc] (no post-lter) |A3 ( f )| [dB] (post-lter) Spurious [dBc] (w/ post-lter)
Christian M nker u
1 200 0.065 -24 -2 -26
2 400 0.016 -36 -8 -44
3 600 0.0073 -43 -12 -55
5 1000 0.0023 -52 -16 -68

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Note: Alternatively, the spurious sidebands can also be calculated by multiplying the Fourier transform of the error current icp (t) with the loop lter transfer function. Although this way is more complicated than analyzing the sawtooth error voltage directly, this method has advantages with more complex error currents like the ones of fractional-N PLLs (chapter 8): t Tw
icp (t)
IL Icp rect 2ICP Tw Tre f

k=
(t kTre f )
f 1 Tw k Tre f
Icp ( f )
k=1
sinc
f k Tre f
kTw Tre f
2IL
k=1
for f
because sinc
kTw Tre f
for kTw
Tre f
The frequency spectrum of the loop lter error voltage Ve ( f ) is calculated by Ve ( f ) = Icp ( f ) ZLF ( f ) 2IL
k=1
k Tre f
1
2 C1 k fre f
Ve k fre f
IL C1 k fre f
(6.4.4)
Using (6.3.2) once more to calculate the spurious response, gives the same result as (6.4.3): sk KvcoVe k fre f Kvco IL = 2 2k fre f 2 C1 k2 fre f
6.5 Narrow Pulses on the Tuning Voltage

Often, the disturbances of the VCO control voltage are short pulses v p (t) (Fig. 6.6) with a repetition rate equal to the reference frequency fre f . Their pulse width Tw usually is much shorter than the pulse period Tre f = 1/ fre f . A very narrow pulse can be approximated by a dirac pulse v p (t) w (t) Vp ( f ) w where w=
+Tre f /2 Tre f /2
(6.5.1)
v p (t)dt Vp ( f ) for
1/Tw
(6.5.2)
w is the area or weight of the pulse. A dirac pulse with weight w has a at spectrum with a spectral amplitude density of w. For real life narrow pulses this is only approximately true as long as f 1/Tw (g. 6.6).
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December 20, 2005
91
vp(t) w m w=mTw
V (f) p
Vp(f) = w sinc fTw
t
Tr m w=m(Tw + Tr ) w 1/Tw 2/Tw sinc fTr
t
1/Tw w 2m Tw (w) w=(w) w Vp(f) = w w=mTw Vp(f) = w sinc2 fTw /2 2/Tw 2/Tw 1/Tr
Figure 6.6: Spectra of Single Short Pulses v p (t) Periodic short pulses are expressed mathematically by folding a single pulse v p (t) with a periodic dirac function (t/Tre f ). In the frequency domain, this corresponds to multiplying the Fourier transformed pulse Vp ( f ) with the periodic dirac frequency function fre f ( f / fre f ) (6.5.3), i.e. the spectrum of the single pulse Vp ( f ) (dashed line in gure 6.7) is the envelope of the periodic dirac frequency function:
ve (t)
m (w/Tref )
V (f) e
t
(w/Tref ) 2m 1/Tw 2/Tw 3/Tw
t
Tw (w) Tref (w) Tw (w/Tref ) 2/Tw
t
f ref
Figure 6.7: Spectra of Periodic Short Pulses ve (t)
ve (t) = v p (t)
n=
(t nTre f )
Vp ( f ) Tre f n=
n Tre f
(6.5.3)
(for the denition of the periodic dirac function see (A.4.5) and (A.4.6)). If the pulses are very narrow, they can be approximated by periodic dirac pulses with a constant weight w: ve (t) w
Christian M nker u
n=
(t nTre f )
w Tre f
n=
n Tre f
(6.5.4)
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Such a pulse train has spectral lines at multiples of fre f with constant fourier coefcients of ck = 2w/Tre f . Using (6.3.1), the resulting VCO output signal becomes: svco (t) A cos 0t Kvco w cos k k=1
0 kre f t
(6.5.5)
This leads to a really simple formula for the magnitude of sidebands produced by short pulses:
Spurious Sidebands Caused by Short Disturbances

sk wKvco k ; k = 1, 2, . . . (6.5.6)
i.e. the spurious levels created by short pulses5 on the VCO control voltage are independent of the actual pulse shape and the reference frequency, they are only determined by the pulse weight w and the VCO tuning sensitivity Kvco . The following examples illustrate this result: A rectangular pulse train with an amplitude m, a pulse width Tw and a repetition period of Tre f has a duty cycle = Tw /Tre f and pulse weights of w = mTw (see Fig. 6.7). Its fourier (magnitude) coefcients are: ck = 2m sin k = 2m sinc(k ) ; k k = 1, 2, . . . (6.5.7)
This means, the pulse spectrum has lines at k fre f , modulated by a sinc(x) function with the rst zero at fre f / = 1/Tw (see Fig. 6.7). For narrow pulses, 1 and sinc(k ) 1, i.e. the rst few coefents have a constant magnitude of ck 2m = 2w/Tre f , the DC content of the pulse train is m . When this pulse train modulates a VCO, spurious sidebands result. Their relative amplitudes sk are calculated with (6.3.2) and (6.5.7): sk = wKvco m Kvco m Kvco sinc(k ) = k fre f k fre f k for k 1/ (6.5.8)
E XAMPLE 6: Short rectangular pulses

Narrow rectangular pules with a width of Tw = 3ns, an amplitude of m = 13mV and a repition frequency of fre f = 200kHz disturb a VCO with a gain of KVCO = 50MHz/V. What is the amplitude of the spurious sidebands? = 3ns 200kHz = 6 104 , w = mTw = 39pVs s1 = 2 103 -54dBc s2 = 1 103 -60dBc ... The rst zero of the sinc(x) function is at 1/Tw = 333MHz, which means the approximation is valid up to at least 1/(10Tw ) 30 MHz - far above the reference
5 Short
meaning Tw
Tre f /k, where Tre f /k is the period of the k-th harmonic of fre f .
Christian M nker u
December 20, 2005
93
frequency.
In praxis, triangular pulses are more common, usually mismatches of up- and down current source create short current pulses that produce a triangular error voltage when integrated by the loop lter: A triangular pulse train with an amplitude m, a pulse width Tw and a repetition period of Tre f has a duty cycle = Tw /Tre f and pulse weights of w = mTw /2 (see Fig. 6.7). Its fourier (magnitude) coefcients are: ck = m sin k /2 k /2
2
= m sinc2 (k /2) ;
k = 1, 2, . . .
(6.5.9)
The pulse spectrum is similiar to the spectrum of the rectangular pulse train: spectral lines at k fre f are modulated by a sinc2 (x) function with the rst zero at 2 fre f / = 2/Tw (see Fig. 6.7). For 1, the rst few coefents have a constant magnitude of ck m (the sinc2 (x) function is 1). The DC content is m /2. Similiar to (6.5.8), the spurious levels at the VCO output are:
sk =
m Kvco m Kvco wKvco sinc2 (k /2) = 2k fre f 2k fre f k
for
1/
(6.5.10)
E XAMPLE 7: Short triangular pulses

Tw = 4nS, fre f = 200kHz, KVCO = 40MHz/V, m = 1mV = 4ns 200kHz = 8 104 , w = mTw /2 = 2pVs s1 = 8 105 -82dBc s2 = 4 105 -88dBc ... The rst zero of the sinc2 (x) function is at 2/Tw = 666MHz.
Both examples demonstrate that it is sufcient to calculate the weight of the disturbance pulses when the pulses are short enough. This allows to estimate the magnitude of spurious sidebands at the VCO output without doing a Fourier analysis. The effect of static mismatch of the charge pump currents is analysed next: In locked state, the total charge Qup + Qdown that is pumped into an integrating loop lter during one reference cycle by iup and idown needs to be zero - otherwise the average VCO control voltage and hence the carrier frequency would drift. Most phase detectors / charge pumps produce pulses in locked state with a certain minimum length - the so called Anti-Backlash (ABL)Length TABL - to avoid deadzone effects. When one of the currents is lower than the other by ie , the corresponding pulse will be longer by te to compensate for the current mismatch: If e.g. the Down-Current is idn = i1 and the Up-current is iup = i1 ie , the difference of the pulse durations te will be:
94
icp (t) idn iup
i e (t)
ve (t)
te
t T ABL
Figure 6.8: Mismatch of Charge Pump Currents
Qup + Qdown (i1 ie ) (TABL + te ) i1 TABL ie TABL te
= 0 = 0 = te (i1 ie ) ie = TABL i1 ie ie TABL i1
(6.5.11)
The weight of the error pulses is calculated separately for the two time steps te and TABL (g. 6.8): First, the error current is ie = iup = i1 ie for a period of te , then ie = iup + idn = ie for a period of TABL . The error voltage is equal to the error current integrated in C1 , which is simply a voltage ramp. The resulting pulse has the shape of a triangle with a steep rise. The weight, i.e. the area of the pulse, is calculated graphically:
= =
te ie TABL TABL ie TABL + 2 C1 2 C1 2 i TABL e ie 1+ 2C1 i1 ie
(6.5.12)
(6.5.12) shows the strong inuence of TABL on the spurious performance. The spurious level at the output of the VCO is easily calculated from the pulse weight using (6.5.6), i.e. sk = wKvco /k.
E XAMPLE 8: Spurious sidebands due to charge-pump mismatch

6.6 The Magical Mystery Spur: Dividing Spurious Sidebands
95
tABL = 4nS, i1 = 4mA, ie = 0.5mA, C1 = 1nF, KVCO = 40MHz/V te = 0.57ns, w = 4.6pVs s1 = 1.8 104 -75dBc s2 = 9.1 105 -81dBc ...
6.6 The Magical Mystery Spur: Dividing Spurious Sidebands

One of the mysteries in the design of frequency synthesizers is the relationship between spurious sidebands and frequency dividers: Measurements show that a frequency divider by N divides the carrier frequency by N (obviously ...), reduces the level of spurious sidebands by 20 log N dB (less obvious) and leaves their distance from the carrier unchanged (magic!). Why is that so? Some books try to explain these effects in the frequency domain, but this approach is somewhat dubious because frequency division is non-time invariant and highly nonlinear. A frequency divider always includes clipping / limiting (digital circuits!), therefore, we only need to deal with phase / frequency modulation. If the input signal to the divider is amplitude modulated, this modulation is converted to phase modulation in the rst limiting stage.
fFM (t)
f0 + f3 f0 + f2 f0 + f1 f0 a) 1/f m1
SFM(f)
t f0
+f m1 +2f m1
f0 + f
+f m2
+f m1
fc b) 1/f m2 1/f m1
t f0
+f m1 +f m2
Figure 6.9: Instant Frequency and Spectra of Divided, FM Modulated Signals It is important to distinguish the different terms used in frequency modulation: Carrier Frequency: the average frequency f0 of zero transitions of s(t) Modulation Frequency: the frequency fm of the modulating signal which creates the spurious sidebands. As shown in the sections above, modulating a carrier with frequency f0 with a weak sinusoidal signal with frequency fm creates spurious sidebands at f0 fm .
96
Frequency Deviation: the instantaneous frequency deviation f of the carrier created by the modulation signal. Modulation Index: the quotient of modulation frequency and frequency deviation = f / fm . The modulation index is inuenced by the amplitude m of the modulation signal or the sensitivity of the modulator (usually the VCO). However, it does not depend on the modulation frequency: increasing fm raises f by the same amount. Deviation Ratio: the modulation index for the highest modulation frequency Bandwidth: nearly all of the power of a frequency modulated signal lies in a bandwidth of f0 , B. As an empirical rule of the thumb (Carsons Rule), the bandwidth is f0 , B 2( f + fm ) = ( + 1) fm .
E XAMPLE 9: Applications for Frequency Modulation

FM-Radio (UKW) uses pre-emphasis to improve the signal-to-noise ratio by boosting high frequencies before modulation6 . This is done with a simple RChighpass ( = 70 s, fB = 2.3kHz): f0 = 100 MHz, fm = 20 . . . 15, 000 Hz, at 20kHz the modulation index is limited to a maximum of 5 to restrain the bandwidth: max = 5(15kHz) f0 , B 2(5 + 1) 15kHz = 180kHz. Channel spacing in UKW - Radio is 200 kHz which explains the choice of max . GSM Mobile Phones:
6 Remember:
FM attenuates high frequencies
Christian M nker u
December 20, 2005
Chapter 7
Other Sources of Spurious Sidebands

Inside every large problem is a small problem struggling to get out. Hoares Law of Large Problems
Overview: This chapter shows different causes for the generation of spurious sidebands and their effects. Knowing the mechanism of sideband generation helps to identify their sources.
Often the PLL designer is confronted with the problem of nasty spurious sidebands without knowing their source(s). The way amplitude and frequency of these sidebands change with the PLL frequency can help to track down their cause and eliminate them. In the following chapter, some possible causes for spurious sideband generation and their characteristics are shown. A rst rough separation can be made by the way the spurs move in the spectrum when the PLL frequency is changed. The names -, - and -spurs have been coined for three very distinctive kinds of sidebands, allowing a quick classication:
Classication of spurious sidebands

-Spur: A sideband whose offset depends on the output frequency fout . It has one xed component at n fsys (g. 7.1). -Spur: A sideband whose offset depends on the VCO frequency fVCO . There is no xed component at the divided output (g. 7.4). -Spur: A sideband with a constant offset from the carrier, it moves with the carrier and has no xed component (g. 7.6).
Some general points:
97
98
In systems where the VCO-Frequency is also the output frequency, - and - spurs are identical. Most sidebands come in symmetric pairs around the carrier: FM / PM modulation is symmetric around the carrier anyway1 , additive disturbances (AM) are converted to PM / FM in every limiting or otherwise non-linear stage. Strong (> 30 dBc) spurious sidebands also create higher order sidebands with lower amplitudes at k times the offset due to non-linearities of PM / FM. The source of disturbances can be tracked by varying supply voltages, reference currents etc. If e.g. the CP is the source, sideband amplitudes rise with CP current, if some logic block creates the noise, increasing its supply voltage will do the same.
7.1 Spurious Sidebands Depending on the Output Frequency ( -Spurs)

When the RF output frequency fout interferes with the reference frequency or the system frequency or their harmonics, a characteristic sort of spurious sidebands is generated, dened as - spurs (g. 7.1).
35*26MHz (fixed)
fout
f f
fs = f out n f sys
fout
s
2 fout
910
910.2 MHz
Figure 7.1: Characteristic behaviour of alpha spurs
Spurious sidebands due to RF output interfering with the system frequency
fs,in j
= n fsys and 2 fout n fsys
fout ( fout n fsys ) ;
n such that
fout n fsys < fsys /2
(7.1.1)
Due to the formation mechanism, the xed spur is unmodulated while the mirror spur has twice the bandwidth of the output signal fout .
7.1.1
RF Leakage Into the System Frequency Path
In the last chapter, examples have been shown for LF signals disturbing the loop lter voltage and thus creating spurious sidebands. Suprisingly, also frequencies far above the loop bandwidth and the system frequency can disturb the PLL output. The mechanism here is downsampling, the interfering signal mixes with multiples of the system frequency and folds signal components down into the baseband (0 f < fsys /2). In general, VCO and output frequency will be no integer multiples of the system frequency because they are derived from a fraction of the system frequency (due to reference divider, fractional-N principle or FM modulation in the mixer stage). The latter two can be especially troublesome, because the output frequency can be so close to a system frequency harmonic that the resulting mixing
1 Except
for complex modulation schemes.
Christian M nker u
December 20, 2005
7.1 Spurious Sidebands Depending on the Output Frequency ( -Spurs)
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product falls within the loop bandwidth. And both VCO and RF output driver produce strong signals that can be heard all over the chip (g. 7.2).
f out ( spur)
f VCO ( spur)
f sys
f sys
1 R
f ref
Loop Filter PD + CP
f vco f ref
Reference Divider
F(s) VCO
1 D LO Divider
f out
NDivider
f ref = fvco / N
1 N
Figure 7.2: Downsampling of RF components into the system frequency path
The mechanism is described in detail in the appendix (C.1). In a nutshell, the spectrum of the intruding signal SRF ( f ) is mixed down with a suitable harmonic of the system frequency n fsys . n must be chosen such that the resulting frequency difference | fRF n fsys | < fsys /2. The most likely place for this to happen is the system frequency path. Here, the edges are sharp enough and the frequency is high enough to produce harmonics that reach well into the RF region. There are two sensitive spots along this path where analog and digital worlds meet: the input of the system frequency amplier where an external sinusoidal signal is converted into the fast-switching system clock. The other one is the charge pump where a DC reference current is scaled up and chopped with the system/reference frequency. If an RF signal couples onto the sinusoidal input signal, the charge pump reference current or on the supplies of these blocks, it can be easily converted down to the baseband - see example 10. The resulting spectrum shows one spur at n fsys and one mirrored around the carrier with an identical offset. Shifting the carrier therefore results in one stationary spur and one moving with twice the frequency shift of the carrier (g. 7.1). Additionally, there may also be spurs at multiples of the offset due to the non-linearities of frequency modulation. The sharper the edges in the system frequency path are, the higher will be the amplitude of the harmonics. This means, very high frequency components can be downsampled into the base band. On the other hand, the circuit becomes much more robust against low frequency injection and inherent noise because the region of high gain / high sensitivity is passed in a very short time. This effect is usually dominant, therefore the system / reference path is constructed with high speed gates. However, the system can be made robust against RF injection by low-pass ltering the sinusoidal system signal and the bias lines. Once the high frequency signal has been folded into the baseband, it behaves like the low frequency injection described in section 7.3.4. If e.g. a 962.2 MHz signal leaks into the system path with a frequency of 26 MHz, it will mix with the 37th harmonic of the 26 MHz signal (962 MHz), producing a component at 200 kHz. This low frequency component will modulate the system frequency and the PLL output signal like described above.
100
fs = 200kHz
(35 * 26 MHz)
S out
s
Ssample
sample
(undisturbed)
910 910.2 MHz
26
52
78 MHz
SPD
f f f
SLF
Loop Filter Characteristic f
f
0.4 26 MHz
0.2
0.4
26 MHz
0.2
SVCO
(w/ spurs) f f f f
35*26MHz (fixed)
Sout
f
s
:4
s
(w/ spurs) f
s
3640.8 MHz
910
910.2 MHz
Figure 7.3: Downsampling of TX output (910.2 MHz) by the system frequency (26MHz)
E XAMPLE 10: Spurs caused by downsampling

An RF signal of 910.01 MHz couples onto the biasing path of a charge pump, creating an RF current with an amplitude of 1 A at the charge pump output. The DC current of the charge pump is 1 mA, it switches with a reference frequency of 26 MHz and a duty cycle of 0.3. The 35th harmonic of the reference frequency is at 910 MHz, mixing the RF signal down to 10 kHz. There is usually no loop lter attenuation at that frequency and the signal will directly modulate the VCO. At the RF output, this gives two spurs, one at 910.0 MHz and one at 910.02 MHz with amplitudes of ck = 1 A sinc(35 ) = 0.03 A. Assuming a load resistor of 1k and a VCO steepness of 60 MHz/V, it will create sidebands with an amplitude of sk = 0.03 A 1k KVCO /(2 10kHz) = 0.09 = 21 dBc (!!)
-spurs: leakage of RF output signal into system / reference path

Mechanism: Frequency Offset: The RF output frequency is downsampled by the system / reference frequency. Equal to the difference of RF frequency and nearest harm spurs: system / reference frequency harmonicsonic of reference / system frequency Attenuated with loop lter characteristic Fractional and integer mode.
Amplitude: PLL Mode:
Christian M nker u
December 20, 2005
7.2 Spurious Sidebands Depending on the VCO Frequency ( -Spurs)
101
Note: When the carrier is modulated, s(t) = A cos (0t + mod (t)t), the down-converted signal has the same modulation: sLF (t) = A cos (s (t) + mod (t)t). When this signal is multiplied with the modulated carrier in the PLL, you will get one unmodulated sideband and one sideband with twice the modulation depth: sout (t) = A cos (0t + mod (t)t) 1 + A cos (st + mod (t)t)
modulated carrier sLF : downconverted signal
= A cos (0t + mod (t)t) +
AA cos (0t st) + cos (0t + st + 2mod (t)t) 2

unmodulated sideband modulated sideband (2x)
(7.1.2)
Leakage of System Frequency Into the RF path
-Spurs can also be generated the other way round: the system frequency or its harmonics may leak into the RF path (e.g. modulating the TX buffer or the modulator). The resulting sideband picture is the same (?):

When the VCO frequency fVCO interferes with the reference / system frequency or their harmonics, a characteristic sort of spurious sidebands is generated, coined - spurs (g. 7.4).
fs = f VCO n fsys
140*26MHz (fixed)
f VCO
f
s
4 fout
f
s
:4
3 fout
fout
f
s
fout
f
s
8 fout
5 fout
3640 3640.2 MHz
909.85 910.05 MHz
Figure 7.4: Characteristic behaviour of beta spurs for D = 4
Frequency of -Spurs
fVCO ( fVCO n fsys ) ; n such that fVCO n fsys < fsys /2 D D+1 D1 fVCO n fsys and n fsys fVCO (7.2.1) D D
fs,in j,LO
= =
7.2.1
VCO / LO Leakage Into the System / Reference Frequency Path
Similiar to the mechanism described in the last section, the VCO / LO signal instead of the divided signal fout can leak into the system / reference frequency path (g. 7.2). The resulting
102
spuriuos spectrum looks more complicated (7.2). For e.g. D = 4, one spur moves with 5 times the frequency shift fout = fVCO /D of the output frequency, the other one with three times fout in the opposite direction (g. 7.4). These spurs enter the PLL via the reference path, their amplitude is attenuated by the loop lter.
7.2.2
System Frequency Harmonics Spurious
As the system / reference frequency directly inuences in-band phase noise performance, it is driven with a very high slew rate to avoid phase noise degradation. This means, the on-chip signal contains a lot of harmonics that can interact with RF signals on chip. A harmonic near the VCO frequency (the carrier) is amplied by the VCO resonant characteristic by 6 dB/oct (20 dB/dec) when it gets close to the carrier. In a PLL, the loop will attenuate frequencies near the carrier with 20 dB/dec for a type I PLL (non-integrating loop lter) and with 40 dB/dec for a type II PLL (integrating loop lter). As these two effects work against each other, signals close to the VCO frequency will have a constant gain within the loop bandwidth for a non-integrating loop lter. With an integrating loop lter, these signals will be attenuated with 6 dB/oct the closer they get to the carrier. The VCO itself and the VCO buffer act as limiters which convert the additive disturbances into PM modulation at both sides of the carrier. Therefore, such an additive signal always creates its mirror partner at the other side of the carrier.
f sys
f sys
1 R
f ref
Loop Filter PD + CP
f ref
n. f sys
f VCO
Reference Divider
F(s) VCO
1 D
f out
LOBuffer LODivider
NDivider
f ref = fVCO / N
1 N
Figure 7.5: Spurious generation due to system frequency harmonics
This effect is only noticable when the disturbing signal (or one of its harmonics) is very close to the oscillating frequency. Harmonic components of the system frequency near the VCO oscillation frequency are a common example for this case of disturbance. (7.2) shows that at the VCO frequency there is one spur with a xed frequency of n fsys . However, after the division by D, only the offset to the carrier remains unchanged, not the frequency itself. Therefore, both spurs move around in the spectrum (g. 7.4).
E XAMPLE 11: Spurious caused by harmonics of the system frequency

The 37th harmonic of the 26 MHz reference frequency is at 962.0 MHz. A VCO oscillating at 962.2 MHz can amplify this harmonic and produce a spurious sideband at 962.0 MHz. The mirror spurious is created with the same amplitude and
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opposite frequency offset at 962.4 MHz. If the VCO is followed by a divider stage by 4, the VCO needs to be tuned to 4 962.2 MHz = 3848.8 MHz to produce the target frequency. The nearest harmonic of the system frequency is 148 26 MHz = 3848.0 MHz. When this harmonic is amplied by the VCO, sidebands will be produced at an offset of 800 kHz, i.e. at 3848.0 MHz and at 3849.6 MHz. The division by 4 leaves the spurious offset unchanged, so youll end up with spurious sidebands at 962.2 MHz 800 kHz = 959.4 / 963.0 MHz. Due to the division, none of the resulting sidebands at the output is a harmonic of the system frequency which makes it difcult to track down the source of the spurs.
Note: This mixing effect also takes place in every other non-linear circuit blocks like the VCO buffer or divider stages. However, as these blocks have no resonant gain, the resulting modulation will be small under normal circumstances. There will be no frequency dependency of the spurious for disturbed blocks outside the loop.
-spurs: system / reference frequency harmonics

Mechanism: Frequency Offset: Amplitude: Harmonics of the reference / system frequency are injected into the VCO. Equal to the difference of VCO frequency and nearest harmonic of the disturbing signal. Within loop BW: Depends on loop lter type, is amplied by VCO resonance (20 dB /dec.) but attenuated by the loop near the carrier (20 / 40 dB/dec). Outside loop BW: attenuation by 20 dB/dec Fractional and integer mode.
PLL Mode:
7.2.3
Fractional-N Spurs
Due to their operation principle, fractional-N frequency synthesizer generate lots of frequency components that are not harmonically related to the reference frequency: A fractional-N PLL can increase the output frequency in fractional steps of the reference frequency (hence its name ...). This fractional channel resolution is achieved by averaging the division ratio over MOD reference cycles. The resulting VCO frequency is (N + F/MOD) fre f with a minimum step size of fre f /MOD. Therefore, spurious sidebands may pop up at strange, unexpected frequencies. Due to the ne frequency granularity, the VCO can be set to oscillate very close to harmonics of the reference or system frequency, which may lead to the different spurious sidebands described above. Although chapter 8 deals with fractional spurs in detail, heres a quick look at their symptoms - we will see that they behave very similiar to the other -spurs described above. Mechanism: Systematic Fractional Sidebands The cyclical variation of division ratios creates a cyclical systematic phase error at the phase detector. This results in several systematic spurs with a minimum spacing of fre f /MOD (described in detail in chapter 8). More and more of these spurs will disapear in the phase
104
noise oor for synthesizers with a higher modulus because the power per spurious line is reduced. However, there is a strong periodic component at an offset from the carrier of f f rac = F/MOD fre f . This effect is especially strong for short modulus sequences and rst order fractional modulators, it can be simulated / calculated in advance. Due to nonidealities (see below) you will probably see these spurs also with higher order fractional modulators. Mechanism: Modulus Control Disturbances Even with higher order fractional-N modulators, the bit lines from the modulator controlling the multi-modulus divider have a spectral content like the rst order fractional-N modulator. Especially when the modulator is off-chip, the single bit lines can create switching noise which e.g. interacts with the phase detector. Clocking the modulator and toggling its output at times when the PD is insensitive can eliminate this problem (staggered timing). Mechanism: Non-Linearities in Higher Order Modulators Non-linearities in the loop can be troublesome with higher order fractional modulators, they create spurious sidebands with an offset of f f rac . This is especially critical with type II PLLs - here the PD / CP operate with very short pulses and the linearity of charge vs. phase error is mediocre. In order to improve linearity, often a small offset current is injected into the loop lter which increases the minimum on-time of the CP (also good for lab testing). Type I PLLs are much more linear in this respect due to their long turn-on time. In spite of the different mechanisms, the effect of fractional spurs are all similiar:
-spurs: fractional-N synthesizer

Frequency Offset: Equal to the fractional part f f rac , therefore, one sideband always falls on the integer frequency (VCO domain), (weaker) sidebands at other frequency offset can also be created. Is attenuated by loop lter characteristic / loop gain, therefore it depends on the frequency offset. For certain fractional values, the spur is stronger (e.g. min. / max. fractional part, half integer - see chapter 8). Only in fractional mode.
Amplitude:
PLL Mode:
7.3 Spurious Sidebands Tracking the Carrier ( -Spurs)

Spurious sidebands that keep their offset to the carrier when the carrier frequency is changed, are called - spurs (g. 7.6).
f VCO / f out
fs = f sys f f
fs fs
Figure 7.6: Characteristic behaviour of Gamma-spurs
Christian M nker u
December 20, 2005
105
7.3.1
Reference Frequency Modulating the VCO

Loop Filter f ref
f ref
f sys
VCO
f VCO
LODivider 1 D
f out
PD + CP
F(s)
fref
NDivider
f ref = fVCO / N
1 N
Figure 7.7: Spurious generation due to reference frequency leakage Spurs created by reference frequency have been covered in great detail in the last chapter: the reference frequency fre f is the update frequency of the the phase detector which is generated by the reference divider. Here, the system frequency fsys is divided by R: fre f = fsys /R. Fractional-N synthesizers have a high reference frequency to gain noise performance, they often use the system frequency as reference frequency: fre f = fsys , R = 1. The reference frequency is present at the output of R and N divider, at the phase detector and the charge pump2 . This frequency mainly disturbs the VCO via its tuning input or supply voltage (see g. 7.7). Especially the charge pump produces pulses with high energy, emitting disturbances at its supplies and output. These disturbances may cause ripple on the VCO tuning input (improper loop lter design, improper current return path for charge pump current, capacitive coupling across the loop lter) or its supplies (improper supply decoupling). In all these cases, the reference frequency directly modulates the VCO frequency, generating spurious sidebands at an xed offset of k fre f from the carrier at the VCO output (see g. 7.9). The higher spurious frequencies (k > 1) can be produced by the inherent non-linearity of frequency modulation or by harmonics of the disturbance itself (or both). Another possible modulation point is the VCO buffer and distribution (see 7.2.2). In any case, the sidebands move with the VCO frequency, keeping their offsets (g. 7.6). This is also true with an LO-divider D behind the VCO - the frequency offset of the spurious sidebands is still fs = k fre f , however, their amplitude is reduced by 20 log D.
Spurious sidebands due to reference frequency leakage

fs,re f = fVCO k fre f ; D k = 1, 2, . . . (7.3.1)
The amplitude of these sidebands drops with at least 20 dB/dec (6 dB/oct) modulation frequency due to the integrating behaviour of the VCO. For example, the 3rd harmonic of a VCO disturbance is attenuated by 3 6 = 18dB more than the fundamental. The reference frequency is always above the loop bandwidth, but it depends on the coupling path whether the loop characteristic has an inuence on these spurious.
2 Exception:
An EXOR phase detector produces twice the reference frequency at its output (see section 3.2.2).
Christian M nker u
December 20, 2005
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7.3.2
System Frequency Modulating the VCO
fsys 1 R
f ref
fsys Loop Filter PD + CP

f ref
VCO
f VCO
LODivider 1 D LOBuffer
f out
Reference Divider
F(s)
Phase Detector / Charge Pump NDivider

f ref = fVCO / N
1 N
Figure 7.8: Spurious generation due to system frequency leakage
Disturbances related to the system frequency fsys behave in a similiar way as fre f disturbances: The system frequency is applied to the chip via an external crystal or a crystal oscillator module and converted to a logic signal on chip. This system frequency can leak into the output path by directly modulating the VCO via its tuning input or supplies (improper shielding or supply decoupling) - see g. 7.8. Exactly as in the fre f case, the VCO is frequency modulated by a (comparatively) low frequency signal, producing sidebands with an offset of k fsys around the carrier (g. 7.9):
Spurious sidebands due to system frequency leakage

fs,sys = fVCO k fsys ; D k = 1, 2, . . . (7.3.2)
f s = 26MHz Sdist
f f f
SVCO
x
s
(clean)
f
78 MHz 3984 MHz
26
52
SVCO
(w/ spurs) f
s
:2
s
Sout
f f f f
3984 MHz
1992 MHz
Figure 7.9: Reference / system frequency modulating the VCO

107
-spurs: VCO modulation by system / reference frequency

Mechanism: Frequency Offset: Amplitude: PLL Mode: Direct frequency modulation of VCO frequency via tuning input or supplies. Independent of carrier frequency, alway with an offset of k fre f resp. k fsys . Independent of carrier frequency, amplitude is attenuated with 1/ fmod due to integrating VCO behaviour. Both fractional and integer mode.
7.3.3
Reference / System Frequency Modulating the LO Distribution
Other possible modulation points for fre f or fsys are the VCO buffer and distribution, also called LO (Local Oscillator) buffering and the LO divider (g. 7.10): especially when the buffering / divider are realized with single ended circuits to save power, fre f or fsys may cause phase modulation of the (divided) LO signal. The difference to frequency modulation at the VCO itself is that this modulation takes place outside the loop - the spurious amplitude is not attenuated with increasing modulation frequency, which means you may also see spurious component far away from the carrier. Reference and system frequency and their harmonics can create a picket fence of spurs when the decoupling is not done properly. It is hard to distuingish whether the LO buffering or LO divider is affected: in both cases (7.3.1) resp. (7.3.2) describe the spur behaviour.
fref , f sys fref
f sys
Loop Filter PD + CP
f ref
VCO
f VCO
LODivider 1 D
f out
F(s)
fref NDivider
f ref = fVCO / N
1 N
Figure 7.10: Spurious generation due to modulation of LO buffer and divider

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-spurs: PM modulation of LO buffer or divider

Mechanism: Frequency Offset: Amplitude: Phase modulation of LO buffers via supplies or parasitic coupling. Independent of carrier frequency, always with an offset of k fre f resp. k fsys . Independent of carrier and modulation frequency. Other inuences depend on source of disturbance - if the CP is the source, spurious amplitudes rise with CP current, if some logic block creates the noise, increasing its supply voltage will do the same. Both fractional and integer mode.
PLL Mode:
7.3.4
LF Injection into the System Frequency Path
The system frequency path is also a hot spot for disturbances to enter the system: phase modulation of the system frequency with low frequencies (i.e. not much higher than the loop bandwidth) directly modulates the PLL output! Again, improper supply decoupling or capacitive coupling onto the signal path are the most likely causes for this. Divider stages at the output of the reference or N-divider can also be dangerous: divider stages often have a signicant backlash from the output to the input, creating a phase modulation with half the reference frequency. In contrast to that, the reference frequency itself in an Integer-N PLL has no impact on the system frequency path: If it modulates the input of the system frequency amplier, spurious on the system frequency will be created at fsys fre f . Behind the reference divider, they will still have the same offset, i.e. be at fre f fre f = 0 and 2 fre f . The DC component has no effect, the other one is just a harmonic of the reference frequency and is far outside the loop bandwidth. A well designed loop lter should get rid of this component (if not, youll see reference spurious anyway: see 7.3.1). Fractional-N synthesizers operate with frequency components that may be well within the loop bandwidth, thats why they have plenty more options for trouble.
Phase Detector / Charge Pump Loop 1 Filter R f sys f ref PD F(s) + Reference f ref Divider CP fref / 2 NDivider
f ref / 2
VCO
f vco
LODivider 1 D
f out
f sys
1 2
f ref = fvco / N
1 N
Figure 7.11: LF injection into the system frequency path
A disturbance with frequency fdis directly translates into spurious sidebands at the output:
7.4 Intermodulation Effects
109
Spurious sidebands due to low frequency injection into the system frequency
fs,in j = fVCO k fdis ; D k = 1, 2, . . . (7.3.3)
Harmonics of the disturbance signal will also appear at the PLL output (k > 1). The same is true if the disturbance is very strong and non-linearities of the PM start showing. Disturbances within the loop bandwidth are transferred with a at frequency characteristic, outside they are attenuated with the loop characteristic.
-spurs: PM modulation of reference / system frequency

Mechanism: Frequency Offset: Amplitude: PLL Mode: Phase modulation of reference / system path via supplies or parasitic coupling by a LF disturbance. Independent of carrier frequency, alway with an offset of k fdis . Independent of carrier frequency, amplitude is constant as long as fdis is within the loop bandwidth. Fractional mode or other system parts with sub-reference frequencies.
7.4 Intermodulation Effects

A signal processing stage with a non-linear transfer characteristic (i.e. any real circuit :-) ) produces intermodulation distortions. This means, when a signal with two or more frequency components passes through that stage, it will produce harmonics of the input frequencies and other new frequency components. In the appendix C.4, the output signal has been calculated for a signal containing two frequencies which is passed through a stage with linear gain and square and cubic distortion terms. Even in this simple example, the output signal has a DC offset and contains harmonic components (distortion) at 21 and 22 , 31 and 32 . It also contains mixed components (intermodulation) at 1 2 , 21 2 and 1 22 . Single ended stages usually show even and odd order distortions while differential stages have a strong suppression of even order distortions (a2 in this example). Therefore, differential stages have much less DC offset due to intermodulation and generate less components at twice the input frequencies (21 and 22 ) and also less rst order intermodulation (1 2 ). In real systems, the cofcients ak may also be negative.
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Chapter 8
Spurious of Fractional-N PLLs

Better to light a candle than to curse the darkness. Chinese Proverb
8.1 Spurious Sidebands of First Order Fractional-N PLLs

The periodic switching of the division ratio is triggered by the phase accumulator, an accumulator with modulus Fmod that adds up NF every reference cycle. Each time an overow occurs, the division ratio is switched from N to (N + 1) for one reference cycle. Ref. Cycle Modulus Cycle NF = 1: Accu Div.
0 2 t=0 0 2 t= 3 5
#1
#2 1 N
1 5 1 5
50 N +1
5 5
#3 #1 Tmod 2 N
2 5
#4 3 N
3 5 1 5
#5
4 N
4 5 2 5 3 5
... #2 Tmod 50 ... N +1 ... #6

5 5
Average
1 N+ 5 2 5
NF = 3: Accu Div. Ratio

0 2 t=0 0 2 t= 3 5
50 N +1
5 5
2 5
0 61 N +1
6 5 4 5
3 N
3 5 1 5
4 N
4 5 2 5
72 N +1
7 5 5 5
50 N +1
5 5 3 5
2 5
... ... ... ... ... ...
0
3 N+ 5 2 5
2 5
1 5
1 5
2 5
2 5
Table 8.1: Operation of Phase Accumulator (Fmod = 5)
Lets assume the PLL is locked at the fractional frequency f0 = NI .F fre f . Fig. 4.2 shows an example for a modulus of Fmod = 3, NI = 10 and NF = 1, giving an average division ratio of N = NI .F = 10 1/3. During the N parts of the modulus cycle the divided VCO signal arrives a little too early at the phase detector because the VCO is faster than the virtual signal f0,int = NI fre f (there is no such signal in the PLL) by f f rac (see 4.0.2). This constant frequency offset corresponds to a phase deviation of 111
112
0 (t) = 2 f0, f ract =
2 NF t Fmod Tre f
or
0 (kTre f ) =
2 kNF Fmod
On average, the deviation of the VCO phase from NI fre f exceeds 2 every Fmod /NF cycles. Table 4.1 shows that the phase accumulator overows with the same frequency, triggering a (N + 1) cycle each time. This is equivalent to swallowing one VCO cycle or removing an excess phase of 2 . This means, the phase accumulator tracks the phase deviation of the VCO and removes it when it exceeds 2 . The phase deviation at the VCO apears N at the phase detector as a phase error e (t) : e (t) = 2 NF 0 (t) = t N NFmod Tre f for 0 t Tmod (8.1.1)
The phase error is only sampled at multiples of Tre f : e (kTre f ) = 2 kNF NFmod
The phase error at the phase detector corresponds to a timing error of te (kTre f ) = e (kTre f ) kNF kNF Tre f T0 Tre f = 2 Fmod N Fmod (8.1.2)
This periodic timing error at the phase detector produces unwanted error pulses at the charge pump output. For simplicity reasons, we regard the case NF = 1, which is not only most easy to calculate but also gives the worst spurious performance: The phase error at the PD e (t) rises continously during the N period (the VCO clock is early) and is reduced by 2 /N when one VCO period is swallowed during the (N + 1) period. This means e (t) has a sawtooth characteristic with a maximum of 2 /N at t = Tmod = Fmod Tre f (see 8.1.1): pd (t) = 2 t saw N Tmod (8.1.3)
where saw(t) is the periodic sawtooth function with a period and an amplitude of 1. In a locked loop, the DC component is eliminated, therefore the phase error changes from /N to + /N rather than from 0 to 2 /N within Fmod cycles. The timing error of t pd = pd (t) T0 2 (8.1.4)
at the phase detector is sampled with the reference clock period Tre f , i.e. Fmod times per Tmod . Therefore, tPD is stepped through 1 1 1 t pd = T0 , + 2 2 Fmod Mathematical Description When the PLL is locked, sometimes the divided VCO phase will be late and sometimes early compared to the reference clock. The resulting output of the phase detector ve (t) will be a
2 1 T0 , + 2 Fmod
1 T0 , . . . , T0 2
(8.1.5)
8.1 Spurious Sidebands of First Order Fractional-N PLLs
113
pulse train with varying pulse width Tw,k , delay Tk and amplitude ak (for an up/down PD, otherwise ak will be constant). The sequence repeats with a period of Tmod = Fmod Tre f : Fmod 1 t Tk ve (t) = ak rect Tw,k k=0
train of rect pulses
The Fourier transformation of (8.1.6) is performed using the following transformations: Rect Pulse : rect (t/Tw ) Delay : s (t T )
n=
n= (t nTmod ) n=
repeat every Tmod
(8.1.6)
Periodicity : s(t)
n=
(t Tmod )
Tw sinc ( f Tw ) S ( f ) exp ( j2 f T ) 1 n= S( f ) ( f n/Tmod ) Tmod n=
The result is given in (8.1.7) where the rect pulses in the time domain translate to sinc pulses in the frequency domain with a complex factor corresponding to their delay. As this train of rect pulses has a periodicity of Tmod , the spectrum consists of lines every 1/Tmod . The amplitude of the spectral lines is given by the superposition of sinc terms which has to be calculated at f = n/Tmod :
Fmod 1 k=0
Ve ( f ) =
ak Tw,k sinc f Tw,k exp ( j2 f Tk )
1 Tmod
n= n=
n Tmod
superposition of complex weighted sinc pulses
lter at f =n/Tmod
n= n=
Fmod 1 k=0
ak Tw,k nTw,k sinc Tmod Tmod 0
exp j2
nTk Tmod
at f =
n Tmod
else (8.1.7)
The next step is to calculate the delays Tk and pulse widths Tw,k and to multiply the spectrum Ve ( f ) at the CP / PD with the loop lter response. The level of the VCO output spurious sidebands can be calculated using equation 6.3.2 with f1 = fmod :
E XAMPLE 12: Spurious sidebands of rst order fractional-N synthesizer

T0 = 1ns, N = 1000, Kvco = 50MHz/V, Fmod = 5, I pd = 4mA, C1 = 1nF, fmod = 200kHz
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Part III
Phase Noise and Jitter
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Chapter 9

Time is just an illusion. Albert Einstein
Overview: This chapter gives an introduction into the concepts of phase noise and jitter, and how to translate specications between the two domains.
9.1 Jitter
Jitter is dened as that short-term noncumulative variations of the signicant instants of a digital signal from their ideal positions in time (SONET specications ITU-T-G.701). For most engineers, the concept of jitter is understood more easily than the concept of phase noise - the rst one describes undesired uctuation of signal transition times, the second one deviations from the line spectrum of an ideal oscillator in the frequency domain. Both concepts are used to describe regular clock or oscillator signal with only slight non-idealities Phase noise is prevalent when spectral purity is a concern as in wireless communication systems, jitter is the concept of choice for applications dealing with timing accuracy as in clock and data recovery. Although signal theory gives methods to translate jitter into phase noise and vice versa, this is not so easy in praxis: It is necessary to know the full spectral characteristic (including phase information!) resp. autocorrelation data to do so.
9.1.1
Jitter of Driven Systems (PM Jitter)
This sort of jitter can be generated in every digital gate - the delay of a digital stage is determined by the slew rate of the input signal and by the switching threshold of the digital input. When the switching threshold varies due to e.g. thermal noise or disturbances of the supply voltage, the delay is varied slightly, introducing jitter. This kind of jitter can be minimized by stable supply voltages and fast edges of the digital signals although the latter may cause high frequency disturbances. It is also called PM (phase modulation) jitter because the frequency at the output is identical to the input frequency, this kind of jitter is synchronous. Its mean 117
118
value is zero and its variance is bounded. In the following, it is assumed that the disturbing signal has a white spectrum and a Gaussian distribution and that its amplitude is small enough that the circuit responds in a linear way to the noise. In this case, the phase variation of sn (t) will also be white. In a PLL, all blocks except the reference oscillator and the VCO exhibit PM Jitter.
9.1.2
Jitter of Autonomous Systems (FM Jitter)
A free running oscillator is an autonomous system, its output period may vary over time, its jitter is called FM (frequency modulation) jitter. Since the variation of a signal transition does not depend on the one before the jitter is accumulating which means the phase drifts without bound. As with PM jitter, it is assumed that the disturbing signal which produces the jitter has white spectrum, Gaussian distribution and a sufciently small amplitude to permit linear calculation. In praxis, these assumptions are not necessarily correct: on top of the white thermal noise, there is usually icker noise with a 1/f spectrum and often periodic components.
9.2 Jitter Measures

As jitter is a random effect, it can only be characterized using statistical terms. All of the jitter measures below use the standard deviation of some term describing the variation of period length, their dimension is time. Depending on application and metric, sometimes the 1 value is specied, sometimes the 3 and sometimes a min-max value (silently assuming a certain value). Some jitter metrics just specify an integral statistical value while some allow deeper insights in the jitter characteristics because they depend on the measurement duration, some of them depend on the measurement duration:
9.2.1
Cycle Jitter (or Cycle-to-Cycle Jitter)
This is the jitter denition that most people mean when talking about jitter as a single number, it is also called jitter per clock cycle and is independent of the observation time. The cycle jitter Jc measures the variance of the period compared to the average period :
2 Jc = 2 ( ) = lim
1 N (k )2 N k=1
(9.2.1)
Frequency drift is not covered by this metric (because the period average varies over time), it merely describes the magnitude of period uctuations.
9.2.2
Period Jitter
This jitter measure describes the displacement of one clock edge relative to the preceding edge. The period jitter Jp is dened as the standard deviation of the difference between two successive transitions, Tk = tk+1 tk . As it is a measure over one cycle, it cannot distinguish between PM- and FM-Jitter and is independent of the observation time.
2 Jp = 2 (Tk ) = lim
1 N (tk+1 tk )2 N k=1
(9.2.2)
Slow changes like 1/f noise modulation of the period are suppressed by this jitter metric. Period jitter is an important specication for digital timing, since it gives the minimum / maximum duration of a clock cycle which is needed e.g. for sythesis constraints.
9.3 Phase Error
119
9.2.3
Long-Term Jitter
This jitter metric is a generalized version of the period jitter, it measures the standard deviation of the timing difference between a signal transition and the n-th succeeding one. When Jl,n is known for all n, the jitter process can be fully characterized.
2 Jl,n = 2 (tk+n tk ) = lim
1 N (tk+n tk )2 N k=1
(9.2.3)
2 If (9.2.3) looks familiar - thats because Jl,n is a measure for the auto-correlation of the period duration.
9.2.4 9.2.5 9.2.6
Accumulated Jitter Absolute Jitter Allen-Variation
Allen-Variation is a usual time-domain measure for oscillator short-term stability: It measures the rms change in successive frequency measurements for short gate times (milliseconds to seconds) and is important in timing applications. It typically improves as the gate time increases until it becomes a measurement of the long term drift or aging of the oscillator.
9.3 Phase Error

The jitter metrics described above were absolute measures. Often, one is more interested in the variation of edge timing, relative to the period. This measure is called phase error e , it also describes a property in the time domain (in contrast to phase noise, see below). Jitter and phase error are related by:
e [rad] = 2 f0 J
or
where J is one of the jitter metrics described above. Peak jitter translates into peak phase error and RMS jitter into RMS phase error. However, phase error measures rely on a xed period 1/T0 , therefore not all jitter measures can be translated into phase errors. Often, the peak-peak phase error is of interest (e.g. in digital systems where a minimum clock period must be guaranteed). When the error signal is noise with a gaussian distribution,
e [deg] = 360 f0 J
(9.3.1)
= e,RMS
i.e. the standard deviation of the phase error e (t) is equal to the RMS phase error. Now, it can be calculated how often a certain peak phase error is exceeded: For example, the phase error becomes larger than the 3 value (or 3 times the RMS phase error) in 0.3% of the transitions (in average). Mathematically put:
p% = 100% erfc = 100% erfc
e,pk 2e,RMS pk,pk 2e,RMS
(9.3.2) (9.3.3)
This means, there is a p% probability that the phase error becomes larger than a certain peak phase error e,pk . For details about Gaussian distribution and error function see appendix G.1.
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Another measure for the phase error is the Error Vector Magnitude (EVM) used with phase modulation schemes like QPSK. Here, each transmitted value or symbol is regarded as a vector (phase / amplitude space). When the phase of the signal is wrong by e , there is an error vector whose magnitude |E| is a measure for signal integrity (assuming there is no amplitude error): |E|2 = 2R2 2R2 cos e = 2R2 (1 cos e ) 2R2 1 (1 |E| Re [rad]
2 e ) ; 2
cos e 1
2 e 2
(9.3.4)
where the cosine has been approximated by the rst term of a series expansion which is only valid for small phase errors. The relative EVM is given in percent, i.e. the radius has been set to one: 100% e [rad] = 100% e [deg] 180
EV M
(9.3.5) (9.3.6)
9.4 Phase Noise

As mentioned in the introduction, one of the main concerns in PLL design for wireless applications is the noise performance (jitter performance for applications that are rooted more in the time domain rather than the frequency domain). PLLs are mainly used to generate the local oscillator (LO) frequency which is used for downconverting (receive path) the wanted signal from the RF domain into the baseband. Phase noise reduces the sensitivity of the receiver because weak signals are smothered in the LO noise. Additionaly, strong signals at nearby frequencies can be mixed into the signal path, reducing the selectivity. In the transmit path, the LO is used to upconvert the signal from the baseband to the RF domain. Here, LO noise leads to emission of unwanted frequencies which disturbs neighbor channels and may violate limits set by e.g. the ETSI or FCC. Besides, a noisy LO increases the bit error rate of the transmitted data. An ideal oscillator waveform would be noiseless, for the case of a sinusoidal waveform with amplitude A and frequency f0 the signal can be described by s(t) = A cos (2 f0t + ). In the real world, there is always noise, affecting phase and amplitude of the signal: s(t) = An (t) cos (2 f0t + n (t)) (9.4.1)
(9.4.1) shows a signal with random amplitude modulation and phase modulation (phase jitter), An (t) and n (t). While the Fourier transform of an ideal sinusoid shows two dirac pulses at f0 , the noise creates skirts around f0 . The energy of the signal is no longer concentrated at a discrete frequency, it is spread over a larger frequency range. The better the quality of the generated signal is, the narrower this frequency band will be. Initially, the energy of the noise will be distributed equally between amplitude noise An (t) and phase noise n (t). However, every oscillator has an amplitude limiting mechanism (otherwise the amplitude would grow innitely), be it by the non-linearity of the oscillating devices or by a dedicated amplitude control mechanism. In PLLs with digital circuitry (frequency synthesis, clock-and-data
9.4 Phase Noise
121
recovery, ...) the amplitude is limited anyway. In both cases, the amplitude noise contribution can be neglected, reducing the noise power by 3 dB1 : s(t) = A cos (2 f0t + (t)) (9.4.2)
It is assumed that the phase noise n (t) is purely random signal. This is not generally true - n (t) may have periodic content that shows as discrete lines (spurious sidebands) in the frequency spectrum, as shown in chapter 6. [...] The relative noise power (or noise-to-signal ratio) is equal to the RMS phase error e,RMS : N 2 (9.4.3) = (J,RMS 2 f0 )2 = e,RMS [rad] P Using the Wiener-Khinchine Theorem, the relative power of the phase noise can also be calculated in the frequency domain: N =2 P
fmin
L( f ) df
(9.4.4)
where L( f ) is the relative phase noise density in W/Hz at an offset f from the carrier. L( f ) is symmetric around the carrier, but only one side is regarded in (9.4.4). Hence, the factor 2 is needed to get the total phase noise power. Therefore, when the total phase noise power is known, its easy to calculate the RMS phase error:
e,RMS =
2
0
L( f ) df
(9.4.5)
When using PLLs, nearly all the produced noise power is contained in the passband. Therefore, the integration is usually simplied by taking the loop bandwidth as the upper integration limit. Near zero frequency offset from the carrier the noise power becomes very large. However, the minimum frequency of interest depends on the needed time frame: If e.g. the analysis runs over a period of 1ms, the minimum frequency of interest is 1kHz. Lower frequencies do not have an inuence on the measurement.
1 This
is not true for frequencies far from the carrier.
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Chapter 10
Noise In The PLL

There is no carrier, there is only concentrated noise. B.-G. Goldberg
In the chapters 6.3 and in the Appendix A it was shown that periodic disturbances on the VCO control voltage are converted up around the carrier frequency f0 , creating discrete spurious sidebands. Noise on the control voltage, vn (t), has a similiar effect1 The resulting output spectrum of the VCO now contains the noise spectrum Vn ( f ), folded around the carrier, instead of discrete spurious sidebands. Usually, vn (t) has a sufciently low amplitude to use the low-modulation index approximation. The spectrum of the VCO output voltage with broadband noise on the control voltage looks very similiar to (6.3.2) (see D.4):
VCO Spectrum with Noise on the Control Voltage

Svco ( f ) A ( f f0 ) + Kvco Vn (| f f0 |) 2 | f f0 | (10.0.1)
i.e. Vn ( f ) is upconverted around the carrier and multiplied by 1/| f f0 | (-20dB/dec) due to the integrating behaviour of the VCO (g. 10.1). If the bandwidth of vn (t) is larger than BW = f0 /2 there will be additional folding back of noise components with harmonics of the carrier (not shown).
10.1 Noise Transfer Properties of the PLL

The various noise sources inside and outside a PLL are transferred differently to the PLL output. The noise transfer function from all noise sources to the output can be calculated using the model in g. 10.2 [Roh97, p.114]:
1 This can be shown by splitting broadband noise into many narrowband noise signals that can be treated like a sinusoid.
123
124
Noise In The PLL
Vn(f)
|Svco(f)| 1/f
log |S (f)| vco

20dB/dec
fn
f0 fn f 0
f0 +fn
f0 fn f 0
f0 +fn
Figure 10.1: Upconversion of Noise Around the Carrier f0
n,ref
Phase Detector / vn,det Charge Pump

i n,det
Loop Filter
F(s)
vn,LF
VCO
n,0
ref
PD + CP
0+ 0
n,div
Divider
0 N 1 N
0 , 0
Figure 10.2: PLL Block Diagram Showing Various Noise Sources
Phase Noise Components in a PLL
2 2 2 O (s) = C2 (s) re f + div +
v2 n,det
2 K 2 2 v2 + vco (s) n,LF
1 1 + GH(s)
KVCO s
(10.1.1)
2 The resulting phase noise O ( ) is double side band noise, single sideband noise L ( ) is 2 ( ). simply half of O
(10.1.1) has two terms with different behavior: phase noise from the reference clock, re f , from the divider output, div and from the output of the phase detector / charge pump vn,det is low-pass ltered with the closed loop transfer function |T ( j )| (g. 10.3). These three noise components are often (but not quite correctly) called PLL noise, NPLL . Closed loop gain was dened (2.1.16) as: G(s) KF(s) O = = re f 1 + GH(s) s + KF(s)/N
T (s) =
N G( j ) (c / j )
pz
for for
c c
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10.1 Noise Transfer Properties of the PLL
125
This means, inside the loop bandwidth the noise is multiplied by N, outside it is attenuated 1/ f pz where p is the order of the PLL and z is the number of zeros of the loop lter transfer function.
log | T(j ) | N 3dB c

zp
Figure 10.3: Noise Transfer Function for Reference Clock, Divider and PD / CP In contrast to that, phase noise from the VCO, vco is high-pass ltered - inside the loop bandwidth it is attenuated by the open loop gain 1/GH(s) (2.1.15), i.e. low frequencies are attenuated most. Outside the loop bandwidth, the VCO noise is no longer controlled by the loop, its transfer function is simply one (g. 10.4): 1/GH( j ) = N j for c 1 1 KF( j ) = 1 + GH(s) 1 + KF(s)/Ns 1 for c
Inside the loop bandwidth, the higher order poles of the loop lter have no effect - they kick in at frequencies near and above fc . This means for an integrating loop lter that only the pole at the origin (integrator) (and the VCO pole itself, of course) affect the transfer function. The VCO noise transfer function grows with 2 (40 dB/dec) for this kind of loop lter (solid line in 10.4). A non-integrating loop lter has a more or less constant transfer function inside the loop bandwidth and VCO noise is transferred to the output proportional to (20 dB/dec, dashed line in 10.4). Noise from the loop lter, vn,LF , (e.g. from the loop lter resistors) can be treated like phase noise from the output of the VCO, additionally it has to be multiplied with the VCO transfer function KVCO /s.
log 1/ | 1+GH(j 1 (Typ 1)
)|
2 (Typ 2) c
Figure 10.4: Noise Transfer Function for VCO
Next, the contributions of different noise sources will be analysed in more detail:
10.1.1
The Famous PLL Noise Formula
Often, one is only interested in the integral effect of PLL noise. Phase error in a GSM transceiver or the RMS jitter for communication systems are examples for this. Figure xxx shows
126
Noise In The PLL
clearly that nearly all noise power is contained in the passband of the PLL (this becomes even more obvious when using a linear instead of the logarithmic dB scale). Here, the noise is usually dominated by reference clock, divider and CP/PD, scaled with the division factor N, see (2.1.16) and gure 10.3. This allows to simplify the general formula (10.1.1)
Often, things can be simplied even more - in a well designed system the noise performance of the reference path is superior to the actual PLL block, therefore its noise contribution can be neglected. And as the customer doesnt care whether the noise is being produced by the phase detector or the divider, these two terms can be combined into noise referred back to the input of the phase detector, N0,PD . In order to compare the noise performance of different PLLs, it would be great to specify a single gure for the inband phase noise. However, the phase noise at the output not only depends on the division ratio N but also on the reference frequency fre f . A handwaving explanation for this goes like that: in locked state, the input signals of the phase detector both operate on the reference frequency. The amount of jitter on each edge does not depend on the frequency, it is determined by temperature, supply voltage, slew rate and some other design and system parameters. However, the number of jittery edges per second and hence the noise power is proportional to the referency frequency: N0,PD fre f . The leads to the famous PLL inband noise formula:
2 v2 n,det 2 2 O ( ) N 2 re f + div + 2 K
:=N0,PD
for < c
Famous PLL Inband Noise Formula

L0 = LPD
fre f =1 Hz
+ 20 log N + 10 log
fre f 1 Hz
(10.1.2)
When e.g. the reference frequency is doubled, the divider ratio N can be halfed to achieve the same output frequency. This increases the noise due to the phase detector by 10 log 2 = 3dB, but reduces the noise gain of the PLL by 20 log 2 = 6dB, giving a performance improvement of 3 dB. Typical values for the phase noise oor at the phase divider are LPD 220dBc(Hz). See example 13on how to use this formula in praxis.
fre f =1 Hz
= 200 . . .
E XAMPLE 13: Comparison of Inband Phase Noise of different PLLs

The inband phase noise oor L0 of three different PLLs is measured: f0 PLL A PLL B PLL C 1.4 GHz 3.8 GHz 0.9 GHz fre f 200 kHz 400 kHz 26 MHz N 7000 9500 34.62 L0 -81 dBc -75 dBc -93 dBc LPD L0 (1.8GHz) -78.9 dBc -81.4 dBc -87 dBc
fre f =1 Hz
-211 dBc -210.5 dBc -198 dBc
In the table above, (10.1.2) has been used rst to calculate the phase noise at the phase detector for a reference frequency of 1 Hz, LPD fre f =1 Hz . From this
10.2 Noise Contributors in the PLL
127
value, the phase noise at an output frequency of 1800 MHz has been calculated. PLL C has a non-integrating loop lter with relatively long turn-on times of the CP. This leads to a higher noise oor LPD , referenced back to the PD. Still, the inband phase noise L0 is very low due to the low division ratio N.

10.2.1 Divider Noise
For most applications, the noise produced by divider stages does not dominate the total phase noise in a PLL. Well designed TTL and CMOS dividers show a noise oor around -160 . . . 170 dBc/Hz. Due to their lower slew rates, dividers using current mode techniques (ECL, CML) only reach -155 . . . -150 dBc/Hz. The noise level goes up at frequencies near the carrier due to icker noise and modulation effects, but otherwise it is white. The most important property of dividers with relation to noise and spurious sidebands is that dividing the frequency by a factor N also reduces phase noise and spurious sidebands by the same amount (20 log N in dBs). This noise reduction is independent from the physical implementation, i.e. it doesnt matter whether the frequency is divided using a digital divider or an analog mixer. It also works the other way round - when the signal frequency is multiplied using e.g. a PLL, the noise and spurious levels are increased with the multiplication factor. As multiplication and division are non-linear operations, the effect is best explained in the time domain: the absolute jitter of a signal is not reduced by a division by N, however, the period length is increased by the same factor. However, the spacing of spurious sidebands from the carrier is not reduced by frequency division as might be expected: If e.g. a 3.9 GHz signal with spurious sidebands at 200kHzis divided by 2, the divided carrier has a frequency of 1.8 GHz (as expected) but the the sidebands are still spaced by 200kHz. A handwaving explanation for this is: looking at the time domain once more, we see that the position of the edges of the carrier signal are modulated in time (jitter and sidebands). Removing e.g. every other edge (division by 2) does not change the way how the edges move to and fro over time. This is especially true as the spectral components we are interested in have a much lower frequency than the carrier. As this is not very intuitive, the proof in [Roh97, pp. 102 - 105] is repeated here: The spurious signal at the divider input is described as a carrier of frequency 0 modulated by a sine wave of frequency m :2 sin (t) = A cos 0t + f sin m fm (10.2.1)
where f is the peak frequency deviation of the carrier. The quotient p = f / fm is the peak phase deviation, also called modulation index . For low peak phase deviations p 1 (narrowband FM), the low modulation index approximation can be used, expanding the signal into the carrier and the two sidebands: sin (t) A cos 0t + A
Carrier: vc
p (cos(0 + m )t cos(0 m )t) 2

Modulation or Noise: vn
(10.2.2)
This form is very useful to nd the relationship between power spectral density and phase noise of a signal:
2 This
could also be a narrowband noise signal.
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Noise In The PLL
Phase noise L ( fm ) is dened as the noise-to-signal power ratio in a 1 Hz bandwidth per sideband at an offset of fm from the carrier: Lin ( fm ) = v2 ( fm ) n v2 c =
2 2 p ( fm ) rms ( fm ) = 4 2
(10.2.3)
The total noise density is the noise in both sidebands and will be called N
2 N ( fm ) = 2L ( fm ) = rms ( fm )
(10.2.4)
The phase i (t) of the input signal is given by
i (t) = 0t +
its instantaneous frequency by
f sin mt fm
(10.2.5)
i (t) =
f d i (t) = 0 + m cos mt = 0 + (t) dt fm
(10.2.6)
A frequency divider by N divides frequency and phase by N, giving an output phase of
o (t) = i (t)/N =
and an output (fundamental) frequency of
0t p + sin mt N N
(10.2.7)
o (t) = i (t)/N =
d o (t) 0 1 f = + m cos mt = (0 + (t)) dt N N fm N
(10.2.8)
This result does not mean that the distance of the modulating signal from the carrier has been reduced by N - the term (t)/N only means that the amount of frequency modulation is decreased by a factor of N. Narrowband FM approximation has to be used once more to see what happens to the spurious sideband:
sout (t) = A cos
0t p + sin mt N N A p 0t 0 0 + m t cos m t + cos A cos N 2N N N
(10.2.9)
This shows that the sidebands still are a distance of fm from the carrier after a frequency division by N. The phase noise at the output of the (noiseless) divider is: Lout ( fm ) = v2 ( fm ) n v2 c =
2 p ( fm ) = Lin ( fm )/N 2 4N 2
(10.2.10)
The phase noise power of the spurious sidebands (or other noise at the divider input) is reduced by N 2 after a frequency division by N, i.e. by 6 dB for a division by 2 and by 20 dB for a division by 10. So far, a noiseless divider has been assumed. In reality, the divider stages themselves add phase noise which may become dominant for very low noise input signals or long divider chains. In a divider chain, the last divider is the most critical one for noise performance because noise of the preceding divider stages is reduced by the subsequent stages. In a well designed divider, the rst stages are optimized for high switching speed (high input frequency) and the last stages as well (high switching speed = low phase noise).
129
10.2.2
Phase Detector and Charge Pump Noise
For this noise analysis PD and CP are regarded as one block. Phase detector noise usually consists of phase noise from the phase detector itself (switching uncertainty) and current noise from the charge pump or voltage noise from the output buffer. The noise at the output of the phase detector v2 ( f ) is transferred to the VCO output with the transfer function (see n,det eqn. 10.1.1)
2 O (s) C2 ( ) = 2 2 vn,det K
N K
for
2
c c
(10.2.11)
G( ) K
KVCO F( )
zp
for
The same equations apply for transferring current noise from the output of the PD/CP to the output of the VCO - just replace v2 ( f ) by i2 ( f ) and use the corresponding K denition n,CP n,det in A/rad.
Inside the loop bandwidth, the phase detector transfer function is at, it is proportional to the 2 division ratio, N 2 and inversely proportional to the phase detector gain, K . Outside the loop bandwidth, the noise is attenuated with ( fc / f ) pz where p is the order of the PLL and z is the number of zeros in open loop transfer function.
When the charge pump current is doubled, K is doubled as well. This means, the contribution of intrinsic phase detector / charge pump noise to the total PLL in-band noise improves by 6dB. However, the noise current increases as well: Doubling the charge pump current by adding a second uncorrelated noisy source increases the noise current by 2 or 3 dB. This improves the signal-to-noise ratio of the CP current by 3 dB. When the current is doubled noiselessly, e.g. by increasing the ratio of a current mirror (producing no noise of its own), the noise current is doubled as well (+ 6 dB). Here, you dont gain in SNR.
From this, one would expect little or no noise improvement from cranking up the charge pump current. In reality however, the charge pump current often has a huge inuence on PLL phase noise - the explanation is that the charge pump current inuences other PLL parameters as well (see box When the CP current is doubled).
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Noise In The PLL
When the CP current is doubled:

- K is doubled as well which improves in-band PD noise suppression by 6 dB. However, the wider noise bandwidth (see next point) eats up a part of this gain. - loop and noise bandwidth increase by approximately 2 (for a second order system with reasonable damping ). The higher loop bandwidth attenuates VCO in-band noise by 3 dB (Type I PLL) or 6 dB (Type II PLL). At the same time, the higher noise bandwidth emphasises the PD - noise components. It depends on the actual VCO and reference noise parameters whether the total integrated phase noise is reduced or increased. - in a type I PLL, the duty cycle of the CP is halved because the tuning voltage for a given frequency has to stay constant. This means, increasing CP current reduces the on-times of the CP and therefore the amount of current noise fed into the loop lter per reference period. It is shown below that this reduces the charge pump noise contribution by approx. 3 dB. - not much changes in a Type II PLL: here, the CP operates with a very low duty cycle anyhow - in locked state, the CP is active only during the ABL (anti-backlash) pulses. This means, that the CP normally doesnt dominate the total phase noise at the VCO output, here, the PD with its timing uncertainties often is the main noise source.
In praxis, it may be very difcult to estimate whether charge pump, phase detector, VCO or some other noise source dominates the inband phase noise of a PLL. Next, the charge pump noise3 will be regarded in detail: Noise from the CP is switched noise (for details see C.3): every time the charge pump is active, a noise current is transferred into the loop lter. This noise may come e.g. from the bias circuitry, the actual output devices or from substrate coupling. Its (unswitched) small-signal current noise power must be determined rst (e.g. by an AC noise simulation) in order to calculate the resulting switched noise power. As the noise current usually scales with the charge pump current, it makes sense to . 2 dene a Current Noise-to-Signal-Ratio NSRi = i2 /ICP to compare different measurements n / simulations. The switching operation folds the noise around multiples of the switching (=reference) frequency fre f . Spectrum and power of the output noise therefore depend on the pulse width Tw , reference frequency and input noise bandwidth fn . The effective noise power in the baseband (0 . . . fsw /2) at the CP can be calculated as Ni,CP ( f ) = k i2 ( f ) where = n Tw Tre f (10.2.12)
The exponent k is in the range 1 . . . 2; it is determined by pulse width, noise bandwidth etc. (see chapter C.3): k = 1 when the CP noise is white or current has a very wide noise bandwidth compared to the reference frequency, k = 2 when its noise bandwidth is less than fre f /2. This noise power density can be referred back to the PD input by dividing it by the PD gain 2 K (only valid inside the loop bandwidth). Taking half of this value gives the two-sided noise power density S (noise power is split between positive and negative frequencies). S is convenient to use because it has the same numeric value as phase noise L ( f ):
3 The
same calculations can be done for a PD with voltage output.
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131
LPD,iCP ( f ) = S ,PD,iCP ( f ) =
Ni,CP ( f ) k i2 ( f ) = 2 n 2 = 2 2 k SNRi ( f ) 2 2K 2ICP /4
(10.2.13)
Finally, the phase noise value at the VCO output is obtained by multiplying LPD,iCP ( f ) with the divider ratio N 2 :
In-band CP noise contribution

LiCP ( f ) = 2N 2 2 k SNRi ( f ) (10.2.14)
E XAMPLE 14: PLL phase noise due to CP noise

A chargepump drives a current of 1 mA into an averaging loop lter with a rst resistor of 1k and a duty cycle of 1:4 ( = 0.2), giving an average loop lter voltage of 200 mV. The PD/CP has a gain of K = 1mA/2 . The reference frequency is 26 MHz and the VCO output frequency 858 MHz, requiring a division ratio of N = 33. The CP produces a white noise current density of in = 250 pA/ Hz. The resulting Noise-to-Signal Ratio is NSRi = 6.25 1014 /Hz or -132 dBc (Hz). As the noise is white (very wide bandwidth), the noise power must be scaled with (k = 1) or the noise current with . This gives an effective noise current of in,e f f = in 112pA/ Hz. Referred back to the PD, the in-band phase noise is:
2 2 i2 f f /2K = i2 /2K = 2.47 1013 rad2 /Hz n n,e
LPD,icp LPD,icp
= or =
10 log(2 2 ) + NSRi = 6dB 132dBc(1Hz) = 126dBc(1Hz)
At a reference frequency of 1Hz, the PD input phase noise would be: LPD,icp
fre f =1 Hz
= 126dBc(1Hz) 10 log (26 MHz/1Hz) = 200dBc(1Hz)
At the output of the VCO, this noise appears multiplied by N 2 (inband only): Lo,icp = 20 log N + LPD,icp = 20 log N + 10 log(2 2 ) + NSRi = 20 log 33 + 6dB 132dBc(1Hz) = 95.6dBc(1Hz)
In order to achieve a loop lter voltage of 400 mV, the duty cycle must be increased to 2:3, i.e. must be doubled. This increases the phase noise at the output (same calculation as above) by 3 dB to -92.6 dBc (1 Hz). Assume the noise is bandlimited to fre f /2 with a current noise density of now 300 pA/ Hz (NSRi = -130.5 dBc(Hz) ). In this case, noise power is scaled with 2 , giving phase noise results of Lo,icp = -101 dBc (1 Hz) [ = 0.2] and -95 dBc (1 Hz) [ = 0.4]. Here, the phase noise due to the charge pump current grows by 6 dB when the on-time of the charge pump is doubled.
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Noise In The PLL
10.2.3
Reference Noise
Noise from the reference input Lre f ( f ) directly inuences in-band phase noise at the VCO output LO,re f ( f ): LO,re f ( f ) = N 2 Lre f ( f ) for f fp (10.2.15)
E XAMPLE 15: PLL phase noise caused by reference noise

A 26 MHz reference oscillator should contribute less than -100 dBc to the inband phase noise of a PLL operating at 1.9 GHz. What is the maximum phase noise of the reference oscillator? Lre f ( f ) < 100dBc 20 log 1.9GHz/26MHz = 137.3dBc
10.2.4
VCO Noise
Typically, a free running VCO usually has a phase noise characteristic shown in g. 10.5:
L (f m )
30db/dec
20db/dec
1/f Noise
White Noise
Noise Floor
f1
ffl
log fm
Figure 10.5: Open loop VCO phase noise at an offset of fm from the carrier For frequencies above f f l , the output noise is white phase noise, caused e.g. by the output buffer, termination resistor etc. In the frequency range between fc and f f l , the output phase noise is dominated by white noise in the VCO core devices (at spectrum). This noise modulates the carrier, resulting in a -20 dB/dec. characteristic. The icker noise of VCO core devices drops with -10 dB / dec, producing a -30 dB/dec. characteristic at the output.
10.2.5
Noise of Loop Filter Resistors
Noise from the output of the loop lter is transferred to the PLL output with the transfer 2 1, the loop lter noise function n,O (s)/v2 (s). Outside the loop bandwidth, |T (s)| n,LF directly modulates the VCO:
133
2 n,0 (s)
v2 n,LF
1 1 + GH(s)
KVCO s
KVCO s
for
(10.2.16)
Inside the loop bandwidth, |GH( j )|

2 n,O (s)
1, and the transfer function becomes

2
v2 (s) n,LF
KVCO 1 GH( j )
for
The last simplications can be made because inside the loop bandwidth, the transfer function of non-integrating loop lters F(s) 1 (Type I PLL). Integrating loop lters can be approx imated by F(s) 1/sC1 (Type II PLL), where C1 is the equivalent loop lter capacitance . (see xxx). K was dened as K = KVCO K . This means, Type I PLLs simply transfer the loop lter noise to the output (scaled by N/K ) while Type II PLLs attenuate the low frequency components of loop lter noise. Outside the loop bandwidth, both PLLs attenuate the noise with 1/ . The loop lter characteristic also lters the noise of the resistors themselves. This noise spectrum N( ) at the output of the loop lter has to be calculated rst. In praxis, the output noise spectrum of the loop lter will be determined using small-signal noise analysis.
N KVCO 2 KF(s) N( ) 2 K N( ) C1 K
for Type I PLLs

2
(10.2.17) for Type II PLLs
E XAMPLE 16: PLL phase noise due to noisy loop lter resistors
A 2.2k resistor in a non-integrating loop lter may dominate the noise. N = 70, K = 3V/ rad, T=300K. Inside the loop bandwidth, this resistor causes singlesideband (factor 1/2) phase noise L ( f ) of:
L(f) =
1 N 4kT R 2 K
4900 0.91V2 rad2 = 1.92 1013 rad2 /Hz = 127dBc/Hz = 1.82 1017 V2 /Hz assuming that the noise from the VCO is pure phase noise (no amplitude noise).
Example: The noise due to the loop lter resistor R2 in a standard three element integrating loop lter (g. 2.12, R2 = 1k, C1 =1.5 nF, C2 =12 nF) can be calculated as follows: K = 0.5mA/2 rad, Kvco = 40 MHz/V, N = 70, BW??? First, the noise spectrum at the output of the loop lter must be calculated: The noise spectrum of R2 , v2 / f = 4kT R2 is low-pass ltered by C1 and C2 [LR00]: n,R2
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Noise In The PLL
v2 ( f ) = n,LF
C1 C1 +C2 1 4kT R2 b2 1 + ff1
v2 n,R2
C 1 + R2 C11C22 +C 2
2.04 1019V 2 /Hz 1 + ( f /119 kHz)2
(10.2.18)
using the denitions of (2.5.2) . C1 +C2 b= = 9; C1 f1 = 1 C1 +C2 = = 119kHz 2 T1 2 R2C1C2
Inside the loop bandwidth, the spectral noise density at the loop lter output due to R2 is constant, 2.04 1019 V2 /Hz. The closed loop noise transfer function can be approximated by (10.2.17), using the equivalent loop lter capacitance C1 C1 + C2 . The phase noise at the output of the VCO is 1 2 v 2 n,LF
N C1 K 2
LR2 ( f ) =
= 1.02 1019V 2 /Hz (0.075rad s/V f [Hz])2 for f f1
= 5.69 1022 rad2 ( f [Hz])2 = 212dBc/Hz + 20 log f
Outside the loop bandwidth, the noise from the loop lter (10.2.19) directly modulates the VCO (10.2.16). Inserting (10.2.18) into (10.0.1), the VCO power density spectrum for f > f0 + fc (upper sideband) can be calculated: AKvco 2 AKvco 2b
2
2 Svco ( f ) =
Vn2 ( f f0 ) ( f f0 )2 4kT R2 ( f f0 )2 1 +
f f0 f1 2
(10.2.19)
This result directly gives the phase noise L ( f ) per sideband around the carrier at f0 (drop the amplitude A, phase noise is measured in dBc):
2 B f1 ; 2 f1 + f 2
LR2 ( f ) =
f2
. B = 4kT R2
Kvco 2b
= 1.28 104 Hz2 = 5.1 103 rad2 /s2 for f f1
8.41 107 rad2 /s4 = +79.2dBc/Hz 40 log f f4
Example: An R3C3 post lter is added to the loop lter of the last example with R3 = 2.2k and C3 = 47pF. The noise from R3 is high-pass ltered by C1 and C2 . At frequencies above f4 = 1/(2 R3C1 ) = 5 kHz, the noise of R3 is transferred to the loop lter output, attenuated by 0.7: v2 = 2.55 1017 V2 /Hz. Inside the loop bandwidth, the resulting phase noise is n,LF LR3 ( f ) = 1 2 v 2 n,LF
N C1 K 2
1 = 2.55 1017V 2 /Hz (0.075 rad s/V f [Hz])2 2 for f fc
= 7.10 1020 rad2 ( f [Hz])2 = 191dBc/Hz + 20 log f

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135
Obviously, the noise contribution of R3 dominates the total loop lter noise. At 1 kHz, this loop lter has a contribution of -131 dBc/Hz, at 10kHz of -111 dBc/Hz to the total output noise. Compared to the rst example, the integrating loop lter contributes more in-band phase noise. This is certainly not a general result as loop BW, loop lter elements etc. have a strong inuence. But the loop gain drops with -40dB/dec for an integrating loop lter and only with -20dB/dec for a non-integrating one. The total (phase) noise power of the VCO output voltage is calculated by integrating L (s) from fc to (the integration starts outside the loop bandwidth fc ) and doubling the result to account for the lower noise sideband:
fc 2 B f1 df 2+ f2 f1
Pn
= 2 =
f2
2B 2B arctan f f1 arctan
f f1 fc f1
fc
1 1 = 2B + fc f1 using equation (G.5.7).
(10.2.20)
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Noise In The PLL
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December 20, 2005
Part IV
Related Fields
137
Chapter 11
Modulation and Demodulation

11.1 Digital Modulation 11.2 Digital Demodulation
The job of the demodulator is to re-extract the modulation signal m(t) from the instantaneous frequency fi (t). Analog PLLs have been used to demodulate FM signals for quite a long time, but since the 1990s more and more digital architectures have evolved. All demodulator architectures can be derived from the same signal processing principle: Ideal FM Discriminator: The ideal FM discriminator consists of a differentiator followed by an envelope detector. In order to remove AM disturbances, usually the signal is rst sent through a limiter. The harmonics of the resulting square wave are then suppressed with a bandpass lter to obtain a nearly sinusoidal signal again. The center frequency of the bandpass should be equal to the carrier frequency, its bandwith large enough to not distort the modulation. In practical implementations, the above principle can only be approximated: Time Delay / Phase Shift: The differentiation process of the ideal FM discriminator can be approximated by a time delay and subsequent subtraction. A typical application of this principle is phase noise measurement equipment using a variable delay line. For low-performance applications the time delay may be realized using an all-pass lter, the subtraction is performed by an EXOR gate. This detector is also called quadrature or coincidence detector because the phase shift ideally is 90 deg. at the center frequency. Slope Detector: Another approximation to the ideal differentiator is the frequency discriminator which converts frequency deviation from a center frequency into amplitude variation1 . The simplest and oldest implementation exploits the frequency selectivity of an LC - tank tuned to a frequency slightly above the carrier frequency. An FM signal across the tank will be converted to AM by its frequency sensitivity. This technique has severe drawbacks, the most notable being its non-linearity because the voltage across the tank is proportional to the square of the frequency. Distortions increase when the maximum frequency deviation approaches the center frequency of the LC tank. Crystal detectors apply the same principle by using the frequency selectivity of crystals. In its simplest form, one crystal is needed per channel, thats why this kind of receiver was mainly used for walkie-talkies or radio amateur applications with a limited number of channels.
1 Remember that a differentiation in the time domain is equivalent to multiplication by
f in the frequency domain.
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140
Modulation and Demodulation
Zero Crossing Detector: Approximates the instant frequency by counting the number 1 1 of zero crossings within a gating time interval TG where fc TG fB . The deviation from the carrier frequency is the momentary modulation data. This principle is well suited to simple, fully digital demodulators.
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Part V
The Toolbox
141
Appendix A
Fourier and Laplace Analysis and Synthesis

If your only tool is a hammer, you tend to see all problems as a nail. Anonymous
Fourier analysis is a family of mathematical techniques, all based on decomposing signals u into sinusoids (see also [Smi99] and [L k85]). Depending on the signal (periodic or nonperiodic, time-discrete or continous) and the personal avour (complex vs. real notation), there are several methods to translate a signal between time and frequency domain. Real life signals are always real valued (i.e. not complex valued) and can be represented using sinusoids with positive frequencies only (single sided Fourier transform). I call this the engineering form of the Fourier synthesis. For complex signals and for some calculations, it is more convenient to use the mathematical form of the Fourier transform that also includes sinusoids with negative frequencies (double sided Fourier transform). In this case, I use double indices (e.g. ckk ) for coefcients and functions. Attention: the single-sided engineering coefcients / functions have twice the value of the mathematical counterparts! When the signal of interest is periodic (and innite), it can be decomposed into a series of discrete, harmonically related sinusoids. This is called a Fourier series (A.1). When the signal is not periodic, it can be described by a Fourier integral (A.2). When the signal is time-dicrete, i.e. sampled, the discrete Fourier transform or DFT (A.3) is used.
A.1 Fourier Series

A periodical signal ve (t) with period T1 = 1/ f1 = 2 /1 can be decomposed into a sum of harmonic sine / cosine functions with frequencies k f1 (k = 0, 1, 2, . . .), the so called Fourier series. The complex coefcients ckk are called Fourier coefcients: ve (t) = ckk =
k=
ckk e j2k f1 t
T1 0
(A.1.1) (A.1.2)
1 T1
ve (t)e j2k f1 t dt
143
144
(A.1.1) is called Synthesis Equation or Inverse Transform, (A.1.2) is called Analysis Equation or Forward Transform. Real life signals ve (t) are always real valued. In this case, ckk and ckk are complex conjugates, i.e. ckk = c = |ckk |e jkk , c0 is real. (A.1.1) can be rewritten kk . using only positive frequencies ck = 2ckk :
ve (t) = c0 + |ck | cos (k1t + k )

k=1
or where
(A.1.3) (A.1.4)
= a0 + (ak cos k1t + bk sin k1t) a0 = 1 T1 2 ak = T1 2 bk = T1

k=0 T1
0 T1 0 T1 0
ve (t) dt
(DC Part) k = 0, 1, ... (DC and Real Part) k = 1, 2, . . . (Magnitude) (Imaginary Part)
ve (t) cos(k1t) dt, ve (t) sin(k1t) dt, c0 = a0 (Phase)
|ck | =
a2 + b2 0 , k k bk ak
k = arctan
The mathematical form (A.1.1) uses positive and negative frequencies (double sided Fourier series), while (A.1.3) and (A.1.4) use only positive frequencies (single sided Fourier series). The coefcients of (A.1.4) are twice as large, because only the positive side of the spectrum is used. In literature, both single and double sided Fourier transforms can be found. Therefore, equations and coefcients may vary by a factor of two from publication to publication. Here, with a few exceptions, only positive frequencies are used because spectrum analysers dont support negative frequencies yet ...
A.2 Fourier Integral

A non-periodic function vn (t) cannot be decomposed into a Fourier series. Instead, it is possible to calculate the Fourier integral for vn (t), i.e. calculate the frequency spectrum Vnn ( f ) for vn (t):

vn (t) = F1 {Vnn ( f )} = Vnn ( f ) = F {vn (t)} =

Vnn ( f )e j2 f t d f
(A.2.1) (A.2.2)
vn (t)e j2 f t dt
Again, (A.2.2) is called Analysis Function or Forward Transform and (A.2.1) is called Synthesis Function or Inverse Transform. Vnn ( f ) has the dimension amplitude/frequency, therefore it is called amplitude density spectrum. Usually, Vnn ( f ) is complex valued. In general, vn (t) can be a complex valued function, too. For real world, real valued functions vn (t), the frequency spectrum Vnn ( f ) for negative and positive frequencies is conjugate com. plex, i.e. Vnn ( f ) = Vnn ( f ) = Vn ( f )/2 (A.2.1). In this case, (A.2.2) be rewritten using only positive frequencies:
A.3 Discrete / Fast Fourier Transform
145
vn (t) =
a( f ) cos 2 f t + b( f ) sin 2 f t d f

where (Real Part) (Imaginary Part)
(A.2.3) (A.2.4) (A.2.5)
. a( f ) = 2 Re{Vnn ( f )} = 2 . b( f ) = 2 Im{Vnn ( f )} = 2
vn (t) cos 2 f t dt vn (t) sin 2 f t dt
Often, these equations are expressed in = 2 f instead of f . Simply replace f by /2 and d f by d /2 in (A.2.3), (A.2.4) and (A.2.5) to re-write the equations in .
A.3 Discrete / Fast Fourier Transform

The additional noise oor created by a discrete Fourier transform is: 3NDFT ??? (A.3.1) ENBW where NDFT is the number of DFT samples and ENBW is the equivalent noise bandwidth of the window function. For a rectangular window, the ENBW is the same as its bandwidth, for a Hanning window, ENBW = 1.5 f . A 4096 point DFT with an effective noise bandwidth of 10 kHz creates a noise oor NFFFT (dB) = 10 log
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146
A.4 Some Fourier Transformations

The following transformations are two-sided (positive and negative frequencies): Similiarity : a s(bt) t Tw a S |b| f b (A.4.1) (A.4.2) (A.4.3) (A.4.4) (A.4.5)
sin Tw f = Tw sinc ( Tw f ) Tw f 1 f Sinc pulse : sinc ( f0t) rect f0 f0 n 1 Periodic function : (t nT ) T f T n= n= Rect pulse : rect Tw Periodic signal :
n=
Dirac pulse : (t) 1
s(t nT ) = s(t) rect t Tw s(t) s(t)
n= n= n=
(t nT ) (t nT ) (t nT )
S( f ) n fT T n= Tw nTw sinc T T n=
(A.4.6)
Periodic. rect. signal :
n T
(A.4.7) (A.4.8) (A.4.9) (A.4.10) (A.4.11) (A.4.12)
Ideal sampler : Sample & Hold (Zero Order Hold) : rect t
1 T
n=
S f
n T
n=
(t nT )
cos 2 f0t
n sinc ( f ) S f T T n=
1 [ ( f f0 ) + ( f + f0 )] 2 j Sine function : sin 2 f0t [ ( f f0 ) ( f + f0 )] 2 ck Fourier series : ck cos k1t [ ( f k f0 ) + ( f + k f0 )] k=0 k=0 2 Cosine function :
Bandpass transform :
s(t) cos 2 f0t s(t) e j2 f0 t
Freq. shift : Delay :
. 2 T where = T0 t S( f ) 1 + S(0) ( f ) Integrator : s( )d j2 f 2 1 (f) + Step function : (t) 2 j2 f
s(t T ) S( f )e
1 [S( f f0 ) + S( f + f0 )] 2 S( f f0 )
j2 f T
A.4 Some Fourier Transformations
(A.4.13) (A.4.14) (A.4.15)
= S( f )e
j f T0
(A.4.16) (A.4.17)
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Appendix B
Noise
Eine Theorie sollte so einfach sein wie mglich, jedoch nicht einfacher. Albert Einstein
B.1 Statistical Terms

ensemble expectation 1st and 2nd order, variance, mean stationary process: E {vn (t)} = vn (t) cyclostationary process: [Kun98], [PK04]
B.2 Thermal Noise

Thermal noise is a fundamental physical phenomenon that is present in any linear passive resistor. Its amplitude distribution is Gaussian and the spectral density is at. The maximum available noise power of a resistor, i.e. the noise power that can be transferred into a matched load is1 Pn = kT f in W (B.2.1)
where T is the absolute Temperature in Kelvin and k = 1.38 1023 VAs/K is Boltzmans constant. Noise power of a resistor only depends on the temperature and the bandwidth of interest. At room temperature (T= 300K), the available thermal noise power of a resistor over a 1-Hz bandwidth is about 4.1 1021 W or -174dBm. The well-known mean-squared noise voltage (current) per bandwidth f of a resistor R (also called thermal noise spectral density) is easily derived from (B.2.1): v2 / f = 4kT R in V2 /Hz n or
1 using
(B.2.2)
only positive frequencies as usual
149
150
Noise
i2 / f = n
4kT R
in A2 /Hz
(B.2.3)
These values are the open circuit (v2 ) / short circuit (i2 ) values. The thermal noise spectral n n density of a 1k resistor at room temperature is2 / f 16.6 1018 V2 /Hz or -168 dBV. vn Written in rms form, this gives vn / f 4nV/ Hz. The equivalent current spectral den sity is i2 / f 1.64 1024 A2 /Hz or in / f 4pA/ Hz n Since the channel in a MOSFET is basically a controlled channel resistor, rch , it exhibits thermal noise (which is also its dominant source of noise). This noise source is best represented by a noise current generator i2 from drain to source with a value of d,n i2 = n,T 4kT f rch (B.2.4)
where 1/rch is the channel conductance of the MOSFET and is a constant depending on the operation region. In the linear region near VDS = 0, the channel conductance is equal to the drain-source conductance 1/rch = gds (vGS vT ) and = 1. The channel conductance of long devices in the saturation region is gm where gm = 2 ID = (vGS vT ) and W /L Cox . Due to eld effects, has a value of approx. 2/3. This gives the formula for MOS drain noise current density often found in text books 8kT 8kT 2 ID f gm f = 3 3 Referred back to the input, this gives an equivalent noise voltage of i2 (sat.) n,T v2 (sat.) = i2 g2 n,T n,T m 8kT f 3gm (B.2.5)
(B.2.6)
E XAMPLE 17: White drain noise current of a MOSFET in saturation

A MOSFET at room temperature with a gm of 10 mS in saturation creates a noise current of 8kT gm f = 1.1 1024 A2 /Hz i2 (sat.) n,T 3 This is equivalent to an rms current of in / f 10.5pA/ Hz, the noise current produced by a resistor of 145 .
However, in short devices, can be much larger (2 ... 3 or even more). This is caused by hot electrons, producing excess noise. In any case, thermal noise of a MOSFET in saturation increases with ID . Decreasing the bias current of a MOSFET gives worse noise performance: if the bias current is reduced e.g. by a factor of 2, the thermal drain current noise is reduced by 2. However, the load resistor must be increased by factor of 2 in order to get the same voltage signal swing. This increases a the noise voltage by 2, the SNR gets worse by 2. The larger load resistor may also add noise - turn up the current for good noise performance!
B.3 Flicker Noise (1/f Noise)

Additionally, there is also icker noise in many devices (BJTs, resistors, MOSFETs...), which is caused by imperfections in the crystal and the gate oxide interface. The spectral density of
B.4 Shot Noise
151
icker noise drops with 1/ f , its magnitude is described by the empirical constants K f and ( 1). i2 f = n, or, referred to the input: v2 f = i2 f g2 = n, n, m Kf f CoxW L f K f ID 1 f L2 f icker noise (B.3.2) K f g2 f K f ID f m = CoxW L f L2 f (B.3.1)
The total noise of a (long) MOSFET in saturation is given by i2 n = 8kT 3 2 ID f +
(B.3.3)
thermal noise
K f depends on process and temperature, typical values are 1024 . . . 1022 V2 F. The frequency where the icker noise starts to grow larger than the thermal noise is called icker noise corner frequency, for MOSFETs it can be in the range of a few kHz up to several MHz. Bipolar junctions and even resistors also show icker noise, however with much lower corner frequencies (a few ten Hz up to several kHz).
B.4 Shot Noise B.5 Bandlimited Noise

The theoretical spectral power density of white noise, e.g. (B.2.2) or (B.2.3), is at - this would give innite total noise power if the bandwidth of interest was innite. In praxis, signals and noise are always low-pass signals, therefore, the noise power is limited to sensible results (E.4).
R R
+
Vout C
vn /f = 4kTR
Vout C
Figure B.1: Equivalent Circuit for Noise of RC Lowpass
Noise generated by a resistor R is ltered by a capacitor C. The resulting noise across the capacitor appears ltered by a one pole low-pass lter with the time-constant RC = RC. This can be seen easily by splitting the noisy resistor into a noisefree resistor and a noise source with v2 / f = 4kT R (see g. B.1). The resulting output voltage has a spectrum of [GM84, p. n 689], [GT86, p.505ff]: v2 ( f ) v2 ( f ) 1/ j2 fC n,out = n f f R + 1/ j2 fC
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(B.5.1)
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Noise
The total noise power is calculated by integrating the ltered noise spectral density over the whole frequency range using (G.5.6): . d f ; RC = RC 1 + (2 f RC )2 4kT R = arctan 2 f RC 2RC 0 1 . kT = 4kT R = 4kT R fn = 4RC C =
0
Pn
4kT R
(B.5.2)
2 vn,out (f)/ f
4kTR
f 3dB f n
Figure B.2: Noise transfer function and equivalent noise bandwidth where fn = 1/4RC = /2 f3dB is the equivalent brick wall bandwidth giving the same total noise power at the output as the actual transfer function (see g. B.2). The noise power at the input is proportional to R, the -3dB frequency of the RC - lter is proportional to 1/R. Therefore, the output noise power is independent of R and can only be reduced by increasing C. (B.5.2) can also be used to calculate the noise power of an independent noise source ltered by a noisy RC lter - simply add its spectral noise density v2 / f to the 4kT R within the n integral.
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Appendix C
Switching and Sampling

C.1 Switched Signals
When a signal is switched periodically, the switching creates multiple copies of the signal spectrum in the frequency domain (g. C.1). These copies of the original signal spectrum will overlap when the signal bandwidth fBW is larger than half the switching frequency fsw /2 (Nyquist criterium). We will assume that the switching signal m(t) is a perfect rectangular signal with frequency 1/Tsw and pulse width Tw , its duty cycle is = Tw /Tsw . 1 The power of this signal can be calculated easily in the time domain, it is Pm = m2 . The spectrum of m(t) is given by:
m(t)
= = =
k=
rect t Tw
t kTsw Tw
rect
Tw sinc Tw f Tsw
k=
(t kTsw )
f k Tsw = M( f ) (C.1.1)
k=
k=
sinc k . =c
kk
k Tsw
The modulation with m(t) can be described by a multiplication in the time domain which is equivalent to a convolution in the frequency domain (gure C.1):
SS,mod ( f ) = SS ( f ) M 2 ( f ) = SS ( f ) =
k=
( sinc k )2
k (C.1.2) Tsw (C.1.3)
k=
c2 SS ( f k/Tsw ) kk
The resulting spectrum shows multiple copies of the original spectrum at frequencies S( f k fsw ) weighted with the amplitude of the switching signals k-th harmonic. Although the original signal s(t) is a bandpass signal, the modulated signal smod (t) also has components at DC. This process is also called downsampling. At the same time, components may be generated at higher frequencies (upsampling). This effect is often used on purpose for
1 The
results can be adapted to non-rectangular signals if needed.
153
154
m(t)
M (f)
sw
Tw s(t)
Tw
x
t
SS (f)
1/T sw
1/T
2/T
*
f
s mod (t)
=
t
SS,mod (f)
=
f
Figure C.1: Switched Signal
frequency conversion, but fast switching signals ( lots of harmonics) up- or downconvert signals or noise to unexpected frequencies.
C.2 Sampled Signals C.3 Switched (Cyclostationary) Noise

When a wide-band signal (e.g. noise) is switched, the switching creates multiples of the noise spectrum in the frequency domain (g. C.2). These copies of the original noise spectrum will overlap when the noise bandwidth fn is larger than half the switching frequency fsw /2 (Nyquist criterium).
2
m(t) Tsw Tw n(t) 1 Tw t
M (f)
2 nn(f) 1/Tsw
1/T
2/T
N0
*
=
f
nmod (t)
nn,mod (f)
N
0
1/Tsw
Figure C.2: Switched white noise, narrow pulses
The switching signal m(t) is a rectangular signal with frequency 1/Tsw and pulse width Tw ,
C.3 Switched (Cyclostationary) Noise
155
its duty cycle is = Tw /Tsw . The power of this signal can be calculated easily in the time domain, it is Pm = m2 . The switching operation has no gain, so m is set to one.
m(t)
= = =
k=
rect t Tw
t kTsw Tw
rect
Tw sinc Tw f Tsw
k=
(t kTsw )
f k Tsw = M( f ) (C.3.1)
k=
k=
sinc k . =c
kk
k Tsw
The noise signal is modulated (multiplied) with m(t) which is equivalent to a convolution in the frequency domain (gure C.2): nn,mod ( f ) = nn ( f ) M 2 ( f ) = nn ( f ) =
k=
( sinc k )2
k Tsw
(C.3.2)
k=
c2 nn ( f k/Tsw ) kk
= N0
k=
c2 = N0 Pm kk
2
for nn ( f ) = N0
(C.3.3)
m(t)
Tsw 1 T
M (f) 1/T w
n(t)
2 nn(f) 1/Tsw
*
=
f
nmod (t)
nn,mod (f)
N
0
1/Tsw
Figure C.3: Switched white noise, wide pulses
When the noise is white with a at spectral power density N0 , (C.3.2) can be simplied. The remaining sum term in (C.3.3) is the sum of the squared harmonics amplitudes of m(t), i.e. it is equal to the power of the modulation signal (see eqn. E.3.1), Pm = m2 = . The noise power density is simply proportional to the duty cycle of the modulation signal (C.3.3): v2 / f = v2 / f n,out n,in
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where = Tw /T
(C.3.4)
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156
This is a bit suprising, one should expect that the output power is proportional to 2 . A somewhat hand-waving explanation for this is: The amplitude of the harmonics of M 2 ( f ) is proportional to 2 . However, with increasing the rst zero of the sinc2 (x) at 1/Tw moves down in frequency and the high frequency content of M 2 ( f ) is reduced. For white noise with unlimited bandwidth, the resulting total noise power is proportional to .
2
m(t)
Tsw 1 T
M (f)
n(t)
2 nn(f) 1/Tsw
1/T
2/T
*
fn
nmod (t)
nn,mod (f)
1/Tsw
Figure C.4: Switched bandlimited noise, narrow pulses
When the noise has a limited bandwidth Bn , things become more complicated: Every dirac pulse in the frequency domain in (C.3.2) corresponds to a line in the spectrum of the modulation signal (frequency and magnitude). Every spectral line folds noise, i.e. shifts a copy of the noise in frequency and adds it to the total output noise, multiplied by its weight (the magnitude of the corresponding spectral line) (see gure C.4, thin lines in 2 nn,mod are the contributions of each spectral line). This mechanism is explained very well in [GT86, p.508510], though for the case of sample & hold. An integrating loop lter does not sample the noise, therefore, results cannot be compared directly.
m(t)
Tsw 1 T
M (f)
n(t)
nn(f)
N
0
1/Tsw
1/T
2/T
*
fn
nmod (t)
nn,mod (f)
N
2 0
1/Tsw
Figure C.5: Switched bandlimited noise, wide pulses
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C.3 Switched (Cyclostationary) Noise
157
A rule of the thumb can be constructed as follows: Usually, the bandwidth of interest is the base band 0 . . . fsw /2, higher frequencies are ltered out by the loop lter. Due to the switching of the input noise spectrum, copies of the spectrum are generated at higher frequencies. The number of input noise bands folded back into the base band depends on the ratio of the input noise bandwidth Bn and switching frequency fsw : A number of 2Bn / fsw copies of the input noise spectrum is folded back into the base band. The multiplication factor for each noise band is given by ( sinc k )2 . As the sinc2 (x) function drops to zero quite fast, the harmonics beyond 1/Tw will be neglected. This means, a number of (1/Tw )/(1/Tsw ) = 1/ harmonics contribute to noise folding with an constant (very rough approximation) amplitude of 2 , the rest is neglected. This crude approximation allows easy calculation. The total noise power density in the base band is approximately
2 nn,mod
2Bn 1 2 N0 min , fsw N0 2 N0 2Bn / fre f 2 N0
with =
Tw Tsw
(C.3.5) (a) (b) (c)
for 2Bn Tw > 1 for 2Bn Tw < 1 for Bn < fsw /2
The meaning of this is best seen with some extreme cases: White Noise / Very Wide Noise Bandwidth (C.3.6a): When the input noise has very wide input bandwidth, lots of noise is folded back into the baseband (g. C.2). 1/ is smaller than 2Bn / fsw or, regrouped, 2Bn Tw > 1. The resulting noise power density is N0 , as already shown in (C.3.4). Wide Pulses (Type 2 phase detector, C.3.6a): For wide pulses, 1/ usually also is smaller than 2Bn / fsw and 2Bn Tw > 1. When, for example, Tw = 1/2Tsw , = 1/2 (g. C.3), the harmonics of M 2 ( f ) are attenuated quite strongly (p.ex. the harmonic at 2 fsw is completely suppressed, the one at 3 fsw only has a magnitude of (0.21)2 , i.e. there is not much folding back of noise. For this reason, limiting the input noise bandwidth in this case has not much effect on the total output noise power - the output noise density becomes N0 . Very Short Pulses (ABL pulses in locked state, C.3.6b): A Type II PLL (integrating loop lter) in locked state produces only very short pulses (compared to Tsw ). This means, that the frequency of the rst zero of the sinc(x) function is at a very high frequency and the rst harmonics of M( f ) have approximately constant magnitude 2 . The input noise bandwidth directly inuences the output noise spectrum - the wider Bn , the more copies of the input noise are added on top of each other (g. C.4) and the output noise density becomes 2 N0 2Bn / fsw . Very Narrow Noise Bandwidth (C.3.6c): When the noise bandwidth is limited to less than half the switching frequency (this could be realized in a system with a high reference frequency, e.g. a Fractional-N Synthesizer), Bn < fsw /2, every spectral line folds a copy of the noise around itself, but the resulting noise bands do not overlap (g. C.5). The total baseband noise density is simply the input noise density scaled with 2 , i.e. 2 N0 . As a rule of the thumb, the effect of downsampling can be ignored if nn ( f fsw /2) nn ( f ) by at least 10 dB.
E XAMPLE 18: Charge Pump Noise

158
Using the same data as in the last examples, K = 0.5mA/ rad, Kvco = 40 MHz/V, N = 70, fsw = 13MHz. The noise current density is in,CP = 20pA/ Hz into a non-integrating loop lter with Rin = 8.2k / into an integrating loop l ter with C1 = 13.5nF. In locked state, the PLL with non-integrating loop-lter produces pulses at the output with a duty cycle of 50% ( = 0.5). The PLL with integrating loop lter only produces very short anti-deadzone pulses with Tw = TABL = 2ns ( = 0.02). Assuming that the noise is wide bandwidth, the resulting output noise spectral density is determined by the modulation duty cycle . With the non-integrating loop lter, the phase detector noise current density is i2 ( f ) = i2 ( f ) = 2.0 1022 A2 /Hz n,CP n,det and for the integrating loop lter: i2 ( f ) = i2 ( f ) = 8.0 1024 A2 /Hz n,CP n,det The resulting noise current at the phase detector v2 ( f ) has to be multiplied n,det with the noise transfer function (10.2.11), giving an output noise spectrum within the loop bandwidth of 3.88 1011 rad2 /Hz = 104dBc/Hz 1.55 1012 rad2 /Hz = 118dBc/Hz
2 O ( f ) i2 ( f ) n,det
N K
for n.i. LF for int. LF
Outside the loop bandwidth, the output noise spectrum is:
KVCO 2 F( j ) O ( f ) i2 ( f ) n,det j
xxxrad2 /Hz = xxxdBc/Hz xxxrad2 /Hz = xxxdBc/Hz
for n.i. LF for int. LF
The single-sideband phase noise L ( f ) has half the magnitude, i.e. 3dB have to be subtracted from the values above.
C.4 Intermodulation of Two Frequencies

When a signal containing two frequencies is put through a non-linear stage, new frequency components will be generated. This process is called intermodulation. Lets assume a stage with linear gain and square and cubic distortion terms: F(x) = a1 x + a2 x2 + a3 x3 A signal containing the two frequencies f1 and f2 is processed by this stage: x = A1 cos(1t) + A2 cos(2t) The output signal will show many new frequency components:
C.5 Clipped Signals
159
F(x) = a1 (A1 cos 1t + A2 cos 2t) + a2 (A1 cos 1t + A2 cos 2t)2 +

linear gain quadratic distortion 3
a3 (A1 cos 1t + A2 cos 2t)

cubic distortion
= a1 A1 cos 1t + a1 A2 cos 2t + a2 A2 cos2 1t + A2 cos2 2t + 2A1 A2 cos 1t cos 2t + 1 2 a3 A3 cos3 1t + A3 cos3 2t + 3A1 A2 cos2 1t cos 2t + cos 1t cos2 2t 1 2 = a1 A1 cos 1t + a1 A2 cos 2t + a2 2 A (1 + cos 21t) + A2 (1 + cos 22t) + 2A1 A2 (cos (1 2 )t + cos (1 + 2 )t) + 2 2 1 a3 3 A (3 cos 1t + cos 31t) + A3 (3 cos 2t + cos 32t) + 2 4 1 3 a3 A1 A2 [(1 + cos 21t) cos 2t + cos 1t (1 + cos 22t)] 2 3 3 3a3 3 3a3 3 = a1 A1 + a3 A1 A2 + A1 cos 1t + a1 A2 + a3 A1 A2 + A cos 2t + 2 8 2 8 1
original f requencies
a2 2 a3 3 a2 2 A1 + A2 + A1 cos 21t + A2 cos 22t + A1 cos 31t + A3 cos 32t + 2 2 2 2 2 4

DC second harmonic third harmonic
3a3 A1 A2 [cos (21 2 )t + cos (22 1 )t] a2 A1 A2 cos (1 2 )t + 4

1st order mix products 2nd order mix products
(C.4.1)
Even in this simple example the output signal contains new components at DC, 21 and 22 , 31 and 32 , mixed components at 1 2 , 21 2 and 1 22 .
C.5 Clipped Signals

Signal clipping can occur as an unwanted effect when the maximum output swing of a linear stage is exceeded. On the other hand, analog signals often are limited deliberately to eliminate amplitude noise for circuitry that only uses the timing / phase information. Limiting can be approximated by putting the signal through a strongly non-linear function with limiting behaviour like arctan(x) ( /2 . . . /2) or tanh(x) (1 . . . 1). Inspite of clipping, an amplitude disturbance will create some phase or timing error. How large that error is depends on the slew rate of the signal and the amplitude of the disturbance: When a sum of two signals passes through a non-linear stage, there will be intermodulation, i.e. the generation of new frequency components. Clipping is just a special form of a nonlinear stage, therefore the results from the last section can be used:
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Appendix D
FM / PM Signals
Any sufciently advanced technology is indistinguishable from magic. Arthur C. Clarke
- General BlaBla
D.1 Sinusoidal Modulation Signals

A sinusoidal signal of amplitude A and frequency 0 that is phase modulated by another sinusoidal signal of frequency 1 and amplitude can be expanded into an innite sum of u cosine signals, each weighted with a Bessel function (see G.2) [L k85, p. 232-235]. The parameter = f / f1 is called modulation index: sFM (t) = A cos (0t + sin (1t + 1 )) = A
n=
Jn ( ) cos (0t + n (1t + 1 ))
(D.1.1)
This signal has a spectrum that is symmetrical around the carrier with frequency f0 and amplitude J0 ( ) (g. D.1). The spurious sidebands have relative amplitudes of Jn ( ) at offsets from the carrier of n f1 . This means, a modulating signal with a single frequency produces lots of spurious sidebands due to the non-linearity of frequency modulation. (D.1.1) has a magnitude spectrum of |SFM ( f )| = A
n=
|Jn ( )| ( f f0 n f1 )
(D.1.2)
For small modulation signals 1, the higher order Bessel terms decrease rapidly; the rst terms can be approximated by: J0 ( ) 1, J1 ( ) /2, J2 ( ) 2 /8. Often, it is sufcient to look at the zero and 1st order terms, i.e. carrier and rst sidebands, and (D.1.1) can be rewritten as sFM (t) A
cos (0t 1t 1 ) + cos 0t + cos (0t + 1t + 1 ) 2 2

161
(D.1.3)
162
FM / PM Signals
In the frequency domain, this corresponds to
( f f0 + f1 ) + ( f f0 ) + ( f f0 f1 ) (D.1.4) 2 2 This case is called Narrow Band FM Approximation1 or Low Modulation Index Approximation.
|SFM ( f )| = A
fFM (t)
f0 + f3 f0 + f2 f0 + f1 f0 a) 1/f m1
SFM(f)
t f0
+f m1 +2f m1
f0 + f
+f m2
+f m1
fc b) 1/f m2 1/f m1
t f0
+f m1 +f m2
Figure D.1: Instant Frequency and Spectra of FM Modulated Signals Fig. D.1 shows momentary frequency and spectra of signals that have been FM modulated by sinusoids. The upper gure shows what happens when the amplitude of a modulation signal with frequency fm is increased: the instant frequency deviation f is increased by the same amount. For a small modulation amplitude (= low modulation index), the modulation will produce only two sidebands in the spectrum around the carrier at an offset of fm . Their level will increase proportionally with the modulation amplitude. At higher modulation amplitudes this relationship becomes non-linear and higher order sidebands at k fm will appear as predicted by (D.1.1). The lower part of the gure shows the effect of varying the modulation frequency: doubling the modulation frequency at the same modulation amplitude decreases the modulation index: in the spectrum, the sidebands appear at twice the offset with half the level.
D.2 Periodic Modulation Signals

Due to the non-linearities of phase / frequency modulation, Lets rst look at two sinusoids interfering with the tune voltage ve (t) = m1 cos 1t +m2 cos 2t. At the VCO output they create an phase error of
e (t) = 2 Kvco =
m1 cos 1 + m2 cos 2 d
m1 Kvco m2 Kvco sin 1t + sin 2t + 0 f1 f2 = 1 sin 1t + 2 sin 2t + 0 where i = mi Kvco / fi

1 No
(D.2.1)
excess bandwidth compared to amplitude modulation is needed as in the case of high modulation indices
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D.2 Periodic Modulation Signals
163
We see that the integrating behavior of the VCO attenuates the signal with the higher frequency and also creates a phase shift of 90 deg. but there are no distortions. In the frequency domain, things are different: applying a power series approximation, neglecting terms of 3rd order and higher and using some trignometric identities gives the following results svco (t) = A cos (0t + e (t)) = A cos (0t + 1 sin 1t + 2 sin 2t) = A cos(0t) cos (1 sin 1t + 2 sin 2t) A sin(0t) sin (1 sin 1t + 2 sin 2t)
1 A cos(0t) 1 (1 sin 1t + 2 sin 2t)2 2 1 A sin(0t) 1 sin 1t + 2 sin 2t (1 sin 1t + 2 sin 2t)3 6 1 2 2 2 A cos(0t) 1 1 sin 1t + 2 sin2 2t + 21 2 sin 1t sin 2t 2
A sin(0t) (1 sin 1t + 2 sin 2t) 1 2 = A cos(0t) + cos(0t 1t) + cos(0t 2t) 2 2 2 1 2 1 2 cos(0t) (1 cos 21t) + 2 (1 cos 22t) + cos (1t 2t) 4 4 4 = A cos(0t) 1 +
2 2 1 + 2 4
1 2 cos(0t 1t) + cos(0t 2t) 2 2
2 1 2 1 2 cos(0t 21t) + 2 cos(0t 22t) + cos(0t 1t 2t) 8 8 8 (D.2.2)
The result shows a whole bunch of sidebands - the ones at offsets of 1 and 2 are the linear terms, additionally the second harmonic of the modulation tones appears at 21 resp. 22 and there is intermodulation as well, giving sidebands at (1 2 ). Higher order terms do not appear A periodic signal ve (t) with a fundamental frequency f1 can be decomposed into an innite Fourier series: ve (t) = c0 + ck cos (k1t + k )
k=1
where ck is the amplitude of the k-th harmonic and k is its phase. It has been assumed, that ve (t) is DC-free (see page 11), i.e. c0 = 0. ve (t) creates a phase modulation of e (t) = 2 Kvco
t
ve ( ) d = 2 Kvco
= 2 Kvco = =
Kvco ck sin (k1t + k ) k=1 k f 1
ck sin (k1t + k ) +Ck k1 k=1
k=1
ck cos (k1 + k ) d
k=1
k sin (k1t + k )
where
k =
Kvco ck k f1
(D.2.3)
The integration constants Ck have been dropped (see G.5) - they only cause static phase / frequency changes which are compensated by the locked loop. k is the modulation index for
164
FM / PM Signals
the k-th harmonic of the modulation signal. For small periodic modulating signals ( < 0.01), narrowband FM approximation (6.2.2) can be used. This allows superposing the modulating effect of each harmonic2 : svco (t) = A cos (0t + e (t)) = A cos 0t + k sin (k1t + k )
k=1
A cos 0t +

(D.2.4)
i.e. each harmonic of the modulating signal is upconverted around the carrier and attentuated by 1/k f1 due to the integrating behaviour of the VCO. This signal has a magnitude spectrum density of: |SFM ( f )| A ( f f0 ) +
k ( ( f f0 + k f1 )) + ( f f0 k f1 )) k=1 2
(D.2.5)
D.3 Phase / Frequency Shift Keying

Phase / Frequency Shift Keying are special cases of periodical modulation signals - the signal phase resp. frequency are modulated with a rectangular signal. The instant phase / frequency is calculated easily but cannot be measured. The measurement process always takes some kind of averaging and ltering which must be specied in order to interpret the results.
D.4 Statistical Modulation Signals

Similiar to the last section D.2, the modulation with a non-periodic signal vn (t) (e.g. noise) can be analysed in the frequency domain. vn (t) creates a phase modulation of:
n (t) = 2 Kvco
vn ( ) d
The effect of this phase modulation can be calculated with the help of its Fourier integral: Vnn ( f ) Vnn ( f ) = Kvco (D.4.1) j2 f jf It has been assumed, that vn (t) is DC-free, i.e. Vnn ( f ) = 0. The resulting VCO output signal is calculated using the inverse Fourier transforms (A.2.1) and (A.2.3): nn (t) = F 2 Kvco vn ( ) d = 2 Kvco svco (t) = A cos (0t + n (t)) = A cos 0t + F1 {nn ( f )} = A cos 0t + Kvco F1 = A cos 0t + Kvco
t
Vnn ( f ) jf Vnn ( f ) e j2 f t d f jf
t
= A cos 0t + 2 Kvco
Re F

vn ( ) d
cos 2 f t d f (D.4.2)
2 In general, it would not be possible to use this approach - frequency modulation is a non-linear operation, therefore the superposition principle is not valid.
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D.4 Statistical Modulation Signals
165
See also [Gar79, pp. 25-31, 100-105].
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FM / PM Signals
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Appendix E
Signal Energy and Power

E.1 The Basics: Energy
A signal s can be described in the time or in the frequency domain, but the energy of the signal must be the same in both domains: E=
E s2 (t)dt = SS (0) = 0
|SE ( f )|2 d f
(E.1.1)
E (Parsevals Theorem) where SS (0) is the impulse or energy auto correlation function (ACF):
. E SS ( ) =
s(t)s(t + ) dt
(E.1.2)
E u The Fourier transform of SS ( ) is the energy density spectrum |SE ( f )|2 [L k85, p. 82]: E SS ( ) = s( ) s( ) = S ( f ) S( f ) = |SE ( f )|2
(E.1.3)
This equation is the Wiener-Khinchine Theorem for energy signals. It shows that the ACF of a signal can be calculated from the magnitude spectrum of its Fourier transform alone, the phase spectrum is not needed. This is especially important for random processes where the phase spectrum is difcult or impossible to determine (spectrum analyzers only measure the magnitude spectrum) - see next section.
E.2 The Basics: Power

Signals with innite energy (periodic signals or innite statistical processes) must be characterized by their power (squared time average or energy per time) instead of their energy: P = s2 (t) = lim 1 T 2T
T T
s2 (t)dt
(E.2.1)
Here, power is used with the denition of system theory, i.e. the square of a signal. Usually, a real physical power can be obtained by multiplying or dividing this value with a constant. When the signal is e.g. a voltage, divide by the impedance to get the power. The direct Fourier transform of statistical processes is not dened - but it is possible to calculate the Fourier transform of the process ACF (E.2.2)
SS ( ) = s(t)s(t + ) = lim
1 T 2T 167
T T
s(t)s(t + )dt
(E.2.2)
168
SS ( ) is the power auto correlation function (ACF) which is dened per time. Note that the u ACF of energy (E.1.2) and power signals (E.2.2) are dened differently [L k85, p. 131]. The Fourier transform of SS ( ) reveals the spectral properties of the process: SS ( ) SS ( f ) = S2 ( f )
(E.2.3)
SS ( f ) is the power spectral density of the signal/process with the unit power per frequency, it can be measured using e.g. a spectrum analyzer. (E.2.3) is the actual Wiener-Khinchine Theorem, it is very important for calculating / measuring the power of statistical processes. Similiar to Parsevals Theorem (E.1.1), signal power can be calculated in the time domain (E.2.1) or in the frequency domain via its ACF (E.2.4), whatever comes more handy: P = SS (0) =

SS ( f )d f
(E.2.4)
For T1 -periodical signals or T1 -cyclostationary processes, (E.2.1) and (E.2.2) can be simplied: 1 T1 2 P= s (t)dt (E.2.5) T1 0
SS ( ) =
1 T1
T1 0
s(t)s(t + )dt
with 0 T1
(E.2.6)
E.3 Power of a Periodic Signal

The two ways for calculating signal power will be demonstrated once more:
E.3.1
Calculation of Signal Power in the Time Domain

A2 T1 A2 T1
The power of a sinusoidal signal s(t) = A cos 1t is calculated using (E.2.5): P = = =

T1 0
cos2 (1t)dt
T1 0
1 t + sin 21t 2 41
A2 A2 T1 = T1 2 2
as expected. A phase shift in the signal doesnt change the power, therefore this result can be applied to any sinusoidal signal. The power of a general periodic signal with period T1 can be calculated by expanding the signal into a Fourier series s(t) = c0 + ck cos (k1t + k ) using (E.2.5) and (A.4.12): k=1 P = = 1 T1 1 T1
T1 0
= c2 + 0
k=1 T1 c2 cos2 (k1t) dt c2 + 0 k 0 k=1 c2 k
c0 + ck cos (k1t + k )
dt
k=1
(E.3.1)
because the cosine terms in the Fourier series are orthogonal, i.e. for k, l = 0, 1, 2, . . .
E.4 Power of Statistical Processes
169
1 T1
T1 0
cos (k1t + k ) cos (l 1t + l ) dt =
0
1 2
for for
|k| = |l| |k| = |l|
(E.3.2)
When the signal is a pure sinusoid, all Fourier coefcients are zero except for c1 = A. In this case, (E.3.1) again gives a power of A2 /2.
E.3.2
Calculation of Signal Power from the Auto-Correlation Function
The power spectral density of a periodic signal is calculated via its ACF (E.2.6):
SS ( ) =
= =
1 T1 1 T1 1 T1
T1 0 T1 0 T1 0
s(t)s(t + ) dt
with 0 T1 c0 + cl cos (l 1t + l 1 + l )
l=1
c0 + ck cos (k1t + k )
k=1
dt
c2 + c2 cos (k1t + k ) cos (k1t + k1 + k ) 0 k

k=1
dt
= c2 + 0
= c2 + 0
1 T1 k=1 2
c2 k
0
T1
c2 k 2
k=1
cos(k1 )
cos(k1 ) + cos (2k1t + 2k + ) dt

...=cos(...)t ...=0
(E.3.3)
Again, the product of the sum of cosine terms was simplied by using the orthogonality of the cosine functions (E.3.2). The remaining sum of products was further simplied by using the trignonometric theorem (G.3.8). The total power of the signal is easily calculated from its ACF (E.3.3): c2 (E.3.4) P = SS (0) = c2 + k 0 k=1 2 which is identical to (E.3.1).
E.3.3
Calculation of Signal Power in the Frequency Domain

c2 k ( f k f1 ) with f 0 k=1 2
Taking the Fourier transform of the ACF (E.3.3) gives the power spectral density: S2 ( f ) = SS ( f ) = F (SS ( )) = c2 (0) + 0 (E.3.5)
Using Parsevals theorem (E.1.1) with (E.3.5) allows the calculation of the signal power in the frequency domain by integrating S2 ( f ) over the whole frequency range. The result is again identical to (E.3.1).
E.4 Power of Statistical Processes

A statistical process n(t) can be described by its statistical properties (average, standard deviation etc.) or by the power spectral density nn ( f ) of its autocorrelation function nn ( ). The power can be calculated both ways:
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Equation (E.2.1) allows calculating the signal power of a statistical process with gaussian amplitude distribution: Pn = n2 (t) = lim 1 T 2T
T T 2 n2 (t)dt = m2 + n = m2 + var(n(t))
(E.4.1)
where m is the average (DC), n the standard deviation and var the variance of n(t). For the case of time-discrete processes, the formula looks very similiar: Pn = s2 (n) =
N 1 s2 (n) = m2 + n2 = m2 + var(n(t)) N 1 n=1
(E.4.2)
In the frequency domain, the power spectral density of the auto correlation function, nn ( f ), is used to calculate the power: Pn =

nn ( f )d f
(E.4.3)
If the power spectral density of white noise really was constant, nn ( f ) = N0 , its total noise power would be innite. In reality, all processes have a limited bandwidth, even the thermal noise itself is low-pass limited by the atomic motion to ca. 1013 Hz. Note: Another measure is phase noise L ( f ): The concept of phase noise is used for systems with a xed frequency and little amplitude noise contribution, i.e. nearly all the noise power is caused by random phase modulation (t), i.e. Pn = Pn,A + Pn, Pn, . Examples for this are oscillators (amplitude noise is suppressed by regulating or limiting the amplitude) or digital signals (clipped amplitude): s(t) = A cos (0t + (t))
E.5 Power of FM / PM Modulated Signals

The total power of a FM / PM modulated signal can be calculated easily: it is independent of the modulation because the amplitude stays constant. FM / PM modulation smears the power over a broader frequency range or several discrete frequency lines. Usually, one is interested in the spectral power density of this modulation spectrum (wanted or unwanted). The power spectral density of a frequency modulated signal can be calculated like that of a normal periodic signal (E.3.5) for two special cases: for sinusoidal modulation (D.1.1) or for low modulation indices (narrowband case) (D.2.4) when the non-linear frequency modulation can be linearized.
Sinusoidal Modulation When a sinusoidal signal with amplitude m and frequency f1 modulates a VCO with gain Kvco , the resulting FM signal has a modulation index of = Kvco m/ f1 and can be written as (D.1.1): sFM (t) = A with a power spectral density of
k=
Jk ( ) cos (0t + k (1t + 1 ))
E.5 Power of FM / PM Modulated Signals
171
2 SFM ( f ) =
A2 2 J ( ) ( ( f f0 k f1 ) + ( f + f0 + k f1 )) 2 k= k
(E.5.1)
This can be shown by calculating the ACF as in (E.3.3). Again, the cosine functions are orthogonal when integrating over a period of T1 . The total power of this signal is P=
A2 A2 2 A2 2 2 J0 ( ) + A2 Jk ( ) + 2 2 4 k=1 carrier modulation
(E.5.2)
Obviously, this approximation is not quite true: A2 /2 is the power of the unmodulated carrier, some of its power must be shifted to the modulation. Still, the term A2 /4 2 is a useful approximation for the modulation power. Harmonic Signal Modulation with a Low Modulation Index The low-modulation index case looks similiar: when a periodical signal with Fourier coefcients ck and base frequency f1 modulates a VCO, the resulting FM signal (with lowmodulation indices k ) can be written as (D.2.4) sFM (t) A cos 0t + where and has a PSD of A2 2

Kvco ck k f1
k =
2 SFM ( f ) =
( f f0 ) +
2 k ( ( f f0 k f1 ) + ( f + f0 + k f1 )) k=1 2
(E.5.3)
The total power of this signal is: P A2 2 A2 1 A2 + = 2 +2 2 2 k=1 k

carrier modulation
AKvco f1
k=1
kk 2
c2
(E.5.4)
Modulation by Noise Carrier and noise power of a carrier with weak phase modulation can be calculated with the approximations sin( (t)) (t) and cos( (t)) 1 (where is given in rad): s(t) = A cos (0t + (t)) = A cos 0t cos ( (t)) A sin 0t sin ( (t)) A (cos 0t sin(0t) (t)) The power of this signal is: A2 T0 A2 2
T0 0
(E.5.5)
cos2 0t 2 cos 0t sin 0t (t) + sin2 0t 2 (t) dt

T0 /2 =0 T0 0
1+
1 T0
2 (t) dt = PC + PN
(E.5.6)
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where PC = A2 /2 is the power of the carrier and PN is the noise power. The noise to signal ratio is equal to the RMS phase error: 1 PN = PC T0
T0 0 2 2 (t) dt = rms
(E.5.7)
In the frequency domain, phase noise L ( f ) is dened as the relative (i.e. referred to the carrier) spectral power per sideband at an offset f from the carrier, assuming that there is no noise power due to amplitude modulation. In this case, phase noise is dened simply as L(f) = 1 nn ( f ) 2 PC (E.5.8)
where PC is the carrier power and the factor 1/2 comes from using only one sideband.
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Appendix F
Second Order (PT2) Approximation

Suche das einfachste Gesetz, das mit den Fakten harmoniert. Ludwig Wittgenstein
F.1 Basic PT2 System

Many real world control system can be approximated by second order systems, i.e. systems whose transfer function contains two poles. The idea is to ignore the higher poles: As a ruleof-thumb, the response of a third-order system can be approximated by the dominant roots of 1 the second-order system as long as the real part of the dominant roots is less than 10 of the real part of the third root [Dor92, p. 166]. Put into simpler words: the higher order poles have to be so far up in frequency that they do not have signicant inuence on the phase margin etc. The advantage of second order systems is that they can be treated analytically without too much hassle, important characteristics like bandwidth, settling time, amount of peaking etc. can be easily extracted [Dor92, pp. 45 - 52, 161 - 168, 313 - 316]. Therefore, its worth looking at second order systems in greater detail. A general description for a second order system is given by:
C(s) = =
2 n 1 = 2 2 2 + 2 s + 2 s s /n + 2 ( /n ) s + 1 n n 2 n
(F.1.1) (F.1.2)
s + n +
2
2 1 n 2 1 n
+
s + n
2
s + n +
2 1
2 1 n 2 1 n
s + n
2 1
(F.1.3)
(F.1.1) is the s-plane representation of the closed-loop transfer function of a second-order system (two poles, no zero). n (unit: rad/s) is the natural frequency and (dimensionless) is called damping ratio. The meaning of these terms will become clear when looking at the 173
174
=0
j j n
<1
>1 >1 =1
=0
Figure F.1: Root locus plot of C(s) as varies with constant n
transient step response of the system (F.1.4). The characteristic equation (i.e. the denominator of C(s)) is factored (F.1.2) to nd its two roots which are the poles of the system. Applying partial fraction expansion (F.1.3) makes it easier to nd the transient response of the system by applying inverse Laplace transform. for = 0 n sin (nt) n e n t 1 2 nt for 0 < < 1 sin 12 c(t) = (F.1.4) n en t for = 1 n 2 1 t + 2 1 t e n e n for > 1 2 2 1 . where = arccos . The transient behaviour (F.1.4) depends strongly on the damping ratio : Undamped oscillation: = 0 The two poles of C(s), s1,2 = jn , sit on the imaginary axis (g. F.1) and the system oscillates without damping at the frequency n . Underdamped system: 0 < < 1 Increasing the damping ratio gives an underdamped system with conjugate complex poles s1,2 = n n jn 12 for 0 < < 1
Increasing lets the poles wander towards the negative real axis on an arc. In the time domain, this corresponds to an increasingly exponentially damped sinusoidal signal response with a ringing frequency of n 1 2 (g. 2.8). Critically damped system: = 1 For = 1 the two poles meet on the real axis; the impulse response is an exponential decay with one time constant.
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F.2 PT2 System with a Zero
175
Overcritically damped system: > 1 > 1 gives two real poles, s1,2 = n
2 1
for
the system is overdamped; its impulse response is an exponential decay (no ringing) with two time constants. Integrating the impulse response (F.1.4) gives the step response c (t) (F.1.5). Alternatively, C(s) (F.1.1) can be multiplied by 1/s before calculating the inverse Laplace transform. 2 1 sin (nt) 1 e n t 12 e sin 1 2 nt + e
n +
for = 0 for 0 < < 1

2 1 t
c (t) =
(F.1.5)
n 2 1
2 1 t
for 1
[Lee98, p.413 f] collects some useful approximations for second order systems with 0 < < 1.
F.2 PT2 System with a Zero
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Appendix G
Bits and Pieces

G.1 Normal Distribution and Error Function
Signal with normal distribution and its PDF
9 9
m = 5, = 1
8
+3
Probability Density (Bin)
6 Amplitude [V]
1 200
200
400 time (s)
600
800
1 1000
Figure G.1: PDF of random process with Gaussian distribution Many naturally occurring random processes (resistor noise, antenna noise etc.) can be described by a Gaussian amplitude distribution (g. G.1. The Gaussian Distribution or Normal Distribution ps,G (x) describes the probability density function of such a random process s:
(xm)2 1 ps,G (x) = e 2 2 2 2
(G.1.1)
It is completely dened by its mean value m and its standard deviation (see Fig. G.2).
177
178
Bits and Pieces
0.4
0.35
0.3
0.25 ps,G(x)
=1
0.2 =3
0.15
0.1
0.05
m=2
0 10
0 x
10
Figure G.2: Gaussian Distribution for m=2 and = 1 / = 3
The total area under the Gaussian distribution is always 1. Due to symmetry reasons, the area between and m is 1/2. Taking the integral Ps,G (x) of the probability density function ps,G (z) from to x gives the probability that the process s is below the limit x:
x
Ps,G (x) =
ps,G (z) dz = =
x (zm)2 1 e 2 2 dz 2 2 x (zm)2 1 1 + e 2 2 dz 2 2 2 m
(G.1.2) (G.1.3)
This integral cannot be solved in closed form, but the integral of the normalized and centered Gaussian distribution p0,g (x) (m = 0, = 1), the so-called Gaussian Error Integral P0,G (x) can be found in mathematical tables [BS81, pp. 18ff]:
x
P0,G (x) = = =
x z2 1 1 1 e 2 dz = + 2 2 2 x 1 1 + erf 2 2 2
p0,G (z) dz
x z2
dz
(G.1.4)
Alternatively, the so-called Error Function, erf(x), found in books. The Error Function is is twice the Gaussian integral with m = 0 and = 1/ 2 (see Fig. G.3): erf(x) = 2
x 0
ez dz
(G.1.5)
= 2P0,G = 2
2x 1 x5 x7 x3 + 3 1! 5 2! 7 3!
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G.1 Normal Distribution and Error Function
179
0.8
0.6
0.4
0.2 erf(x)
0.2
0.4
0.6
0.8
1 2
1.5
0.5
0 x
0.5
1.5
Figure G.3: Error Function erf(x)
The Complementary Error Function, erfc(x), is quite commonly used to describe the probability of a process to be above or outside a limit x: 2 erfc(x) =
x
ez dz = 1 erf(x)
(G.1.6)
Using the denitions of (G.1.4) and (G.1.5), (G.1.2) can be reformulated: xm xm 1 erfc 2 2
Ps,G (x) = P0,G =
(G.1.7) = xm 1 1 + erf 2 2 2
E XAMPLE 19: Thermal noise at the input of a comparator

A thermal noise voltage with a mean (DC) voltage of m = 450mV and a standard deviation of = 10mV is applied to a comparator. What is the probability for the noise voltage to exceed the comparator threshold of 500mV?
Ps,G (500mV ) =
500mV 450mV 1 1 + erf 2 2 2 10mV 7 = 1 2.9 10
gives the probability for the noise voltage being below the comparator threshold. It can be seen easily that the amplitude of the noise needs to have a value of 5 or more to exceed the threshold of the comparator. This happens with a probability of 2.9 107 (Table G.1), i.e. it exceeds the threshold for less than a second per month.
180
Bits and Pieces
In theory, a random process with Gaussian amplitude distribution will reach any amplitude value once in a while - but you may have to wait very, very long to see that happen ... Therefore, in practical applications, it is often assumed that the amplitude of such a process stays within 3 . This limit is exceeded with a probability of 0.135 % (Table G.1). x 1 Ps,G (x) erf(x)
0.159
2 0.0228
3 1.35 103
4 3.17 105
5 2.87 107
6 9.87 1010
Table G.1: Function Values of Error Integral (m = 0)
G.2 Bessel Functions

Bessel functions are useful for expanding terms like cos(0t + sin 1t) which occur frequently in FM / PM calculations. Bessel functions of the rst kind with order are dened by [BS81, pp. 7ff,440ff]: J (x) =
n=0
(1)n 2 +2n n! ( + n + 1)
x +2n
(G.2.1)
For integer values of , the Gamma function [BS81, pp. 6, 103] is dened by (n + 1) = n!, allowing an easier power series expansion:
J (x)
= e.g.
n=0
(1)n 2 +2n n!( + n)! !

x2n
x +2n
x 2
for |x|
(G.2.2)
J0 (x) J1 (x) J2 (x)
= = =
n=0
(1)n 22n (n!)2 = 1

x2n+1 x2n+2
x2 x4 x6 + +... 4 64 2304 x x3 x5
n=0 n=0
(1)n 22n+1 n!(n + 1)! = 2 16 + 384 . . . (1)n 22n+2 n!(n + 2)! =

x2 x4 x6 + +... 8 96 3072
The power series expansions for the Bessel functions of order 0 and 1 (and the functions themselves) look quite similiar to the sine and cosine functions (G.3.20) and (G.3.21). Some theorems for Bessel functions:
Jn (x) = (1)n Jn (x)
(G.2.3) (G.2.4) (G.2.5) (G.2.6)
n=
Jn (x) = J0 (x) + 2 J2n (x)

n=1
Jn1 (x) + Jn+1 (x) = sin ( sin t) =
2n Jn (x) x
n=
Jn ( ) sin(n t)
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G.3 Trigonometric Theorems and Identities
181
i=0 0.8 i=1 0.6 i=2 i=3 0.4
0.2 J (x)
i
0.2
0.4
0.6 10 8 6 4 2 0 x 2 4 6 8 10
Figure G.4: Bessel Functions 0th to 3rd order
= 2 J2n1 ( ) sin((2n 1) t) cos ( sin t) =
(G.2.7) (G.2.8) (G.2.9) (G.2.10) (G.2.11) (G.2.12)
n=
n=1
Jn ( ) cos(n t)
= J0 ( ) + 2 J2n ( ) cos(2n t)
n=1
cos (0t + sin 1t) = cos (0t + sin (1t + 1 )) = sin (0t + sin 1t) =
n= n= n=
Jn ( ) cos(0t + n1t) Jn ( ) cos (0t + n(1t + 1 )) Jn ( ) sin(0t + n1t)
(G.2.6) and (G.2.8) are the textbook equations from which (G.2.10) and (G.2.12) have been derived using (G.3.12). In (G.2.11) the modulating signal has been phase shifted.
G.3 Trigonometric Theorems and Identities

Sine Function sin
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= cos(
) 2
(G.3.1)
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182
Bits and Pieces
sin sin sin2 sin3

n
= = =
sin = sin ( ) = sin cos cos sin Cosine Function cos( ) = sin( + cos cos cos2 cos3 = = =
1 [cos( ) cos( + )] 2 1 (1 cos 2 ) 2 1 (3 sin sin 3 ) 4
(G.3.2) (G.3.3) (G.3.4) (G.3.5) (G.3.6)
) 2
(G.3.7) (G.3.8) (G.3.9) (G.3.10) (G.3.11) (G.3.12) (G.3.13) (G.3.14)
1 + 2 cos(2 nt) =
n=1
cosn = cos ( ) = cos cos

n=
1 [cos( ) + cos( + )] 2 1 (1 + cos 2 ) 2 1 (3 cos cos 3 ) 4 sin sin
(t n)
arccos( ) = arctan Mixed Sine and Cosine Function sin cos sin cos Euler Identity cos + j sin cos sin = =
1 2
1 [sin( ) + sin( + )] 2 1 sin 2 2 = e j e j + e j = 2 e j e j = 2j x3 x5 + . . . x for |x| 6 120 1;
(G.3.15) (G.3.16)
(G.3.17) (G.3.18) (G.3.19)
Power Series Expansion for Sine and Cosine Functions sin(x) = cos(x) = 1 cos(x) =
n=0 n=0 x2
(1)n (2n + 1)! = x

x2n
x2n+1
1 (G.3.20) (G.3.21) (G.3.22)
(1)n (2n)! = 1
2
x2 x4 + . . . 1 for |x| 2 24 1
x4 x2 +... for |x| 24 2
G.4 Quadratic Equation

The equation ax2 + bx + c = 0 has two solutions - real or complex b b2 4ac x1,2 = 2a
(G.4.1)
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G.5 Differentials and Integrals
183
G.5 Differentials and Integrals

See [BS81, pp. 35ff]. d sin t dt d cos t dt d sin2 t dt sin2 t dt cos2 t dt dx a2 + x2 dx x2 (a2 + x2 ) = cos t = sin t sin t dt = 1 cos t +C 1 cos t dt = sin t +C (G.5.1) (G.5.2) (G.5.3) (G.5.4) (G.5.5) (G.5.6) (G.5.7)
= 2 sin t cos t = sin 2 t t 1 sin 2 t +C 2 4 1 t + = sin 2 t +C 2 4 1 x = arctan +C a a 1 1 x = 2 3 arctan +C a x a a =
Integration of the Sine Function Strictly spoken, the integral
(t) =
=
t 0
cos 1 d cos 1 d + 1 sin 1t 1

t 0
cos 1 d
0
= C+
where C =
cos 1 d
(G.5.8)
does not converge. However, the integral from to zero represents a constant phase C that is bounded between 1 1 C 1 1 (G.5.9)
and can be set to zero for most applications [L k85, p. 234]. u
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184
Bits and Pieces
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Appendix H
Variable and Acronym Denitions

Variable A A0 C(s) D F Fmod F(s) G(s) H(s) KF Meaning Amplitude Carrier Amplitude Output (control theory) Fixed division ratio between VCO and synthesizer output Fractional part of division ratio N, written as N.F Number of reference cycles per modulus cycle Transfer function of loop lter Forward transfer function of process or plant, here, usually the PLL forward path Transfer function of feedback path, here, usually the divider transfer function Loop lter gain constant, unit depends on type of loop lter and PD - can be , 1 or 1 Open loop gain factor VCO gain factor PD gain, unit depends on PD type - can be A / rad or V / rad Main division ratio Number of cycles with N(t) = N + 1 per modulus cycle Integer part of division ratio N Noise power density Power Division ratio of reference divider Resistance Input, stimulus Period or time duration (also look under fxxx instead Txxx ) Closed-loop transfer function Denition C(s) = T (s)R(s) fout = fvco /D F = frac(N) = FNF
mod
Unit V or A V or A 1 1 1 ( KF ) 1 1 1 Hz / V 1 1 1 W/Hz W 1 s
Fmod =
Tmod Tre f
G(s) = KO /s -
KO KVCO K N NF NI N0 P R R R(s) T T (s)
KO = K KF KVCO N = NI + NF NI = int(N) fre f = fsys /R T = 1/ f T (s) = =

C(s) R(s) G(s) 1+G(s)H(s)
185
186
Variable TABL Tmod Tw f f0 f3dB fB fFR fS fc fdiv fm fout fre f fs fvco fs fsys w s s(t) S( f ) t
Meaning Minimum duration of PD / CP - pulses (Anti-BackLash) Modulus period Pulse width Frequency Carrier or VCO frequency Frequency where the closed loop gain has dropped by 3dB (3dB bandwidth) (Signal) bandwidth Free running VCO frequency (Vctrl = 0) Sampling frequency Frequency where the open loop gain becomes 1 (crosses the 0 dB line) Divided VCO frequency at the PD Modulation frequency Output frequency of synthesizer Reference frequency at the PD / CP Frequency of spurious sideband VCO frequency Distance of spurious sideband from carrier System frequency (crystal frequency from which fre f is derived) Weight (area) of a single pulse Complex frequency Generalized signal Power spectral density of s(t) Time as a variable Duty cycle Modulation index Phase - here, phase usually means excess phase, i.e. without the part t that increases in a linear fashion over time. VCO or carrier phase Divided VCO (excess) phase (at PD) Excess or error phase: the difference of input phases at the PD Phase margin of the loop Reference (excess) phase (at PD) Phase in the frequency domain Circular frequency (also look under fxxx instead xxx ) Eigenfrequency of second order system (closed loop) - n has no relation with the input or output frequency of the PLL! It is rather a sort of gain-bandwidth product of the PLL. For a second order system with = 0.707, n = c = 3dB Standard deviation Real part of complex frequency Damping factor of a second order system
Denition Tmod = Fmod Tre f |T ( f3dB )| = |T (0)| / 2 |GH( fc )| = 1 fdiv = fO /N fout = fvco /D fre f = fsys /R fsys = R fre f
+ w = s(t)dt s = + j F {s(t)} = Tw /T = f / fm = Kvco fm /m -
Unit s s s Hz Hz Hz/s Hz Hz Hz Hz/s Hz Hz Hz Hz Hz Hz Hz Hz Vs or As e.g. V or A W/Hz s 1 1 rad
0 div e m re f (s) n
div = 0 /N e = re f div = 2 f -
rad rad rad rad rad rad rad / s rad/s
= Re {s} -
1 1 1
Christian M nker u
December 20, 2005
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Telecommunication business is notorious for its TLAs (Three Letter Acronyms) - this book also uses quite a few: Acronym ABL ACF AWGN CMOS CP DMD GSM LF LTI MMD OSR PD PFD PSD PLL RF VCO Meaning Anti BackLash (pulses) Auto Correlation Function Added White Gaussian Noise Complementary Metal Oxide Semiconductor Charge Pump Dual Modulus Divider Global System for Mobile communication, originally Global Syst` me Mondial e Low Frequency Linear Time-Invariant (system) Multi Modulus Divider Oversampling Ratio Phase Detector, also used for Phase Frequency Detector Phase Frequency Detector Power Spectral Density Phase Locked Loop Radio Frequency Voltage Controlled Oscillator
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Bibliography
[Bes98] [BS81] [CS98] Roland Best. Theorie und Anwendungen des Phase-Locked Loop. AT Verlag, Aarau / Stuttgart, 1998. German PLL Bible, no CP PLLs. Bronstein and Semendjajew. Taschenbuch der Mathematik. Verlag Harri Deutsch, Thun, 21st edition, 1981. Jan Craninckx and Michel S. J. Steyaert. A fully integrated cmos dcs-1800 frequency synthesizer. Journal of Solid-State Circuits, 33:20542065, Dez. 1998. Dual Path Loop Filter, Loop Filter Calculations, Prescaler. Richard C. Dorf. Modern Control Theory. Addison-Wesley Publishing, Reading, Mass., 6. edition, 1992. General control theory. Floyd M. Gardener. Phaselock Techniques. John Wiley and Sons, New York, 1979. The PLL bible, but no CPs. Paul R. Grey and Robert G. Meyer. Analog Integrated Circuits. John Wiley and Sons, New York, 2nd edition, 1984. Thermal Noise, Noise Bandwidth. Roubik Gregorian and Gabor C. Temes. Analog MOS Integrated Circuits for Signal Processing. John Wiley and Sons, New York, 1986. Switched Circuits, Noise of SC-Filters / S & H Circuits. Ken Kundert. Modeling and simulation of jitter in pll frequency synthesizers. http://www.designers-guide.com, 1998. Thomas H. Lee and John F. Bulzacchelli. A 155 mhz clock recovery delay- and phase locked loop. IEEE J. Solid-State Circuits, 27:17361746, Dez. 1992. Good introduction into clock and data recovery and DLLs, describes Hogges, Triwave and Modied Triwave Phase Detector in detail. Thomas H. Lee. The Design of CMOS Radio-Frequency Integrated Circuits. Cambridge University Press, Cambridge, UK, 1998. Christopher Lam and Behzad Razavi. A 2.6-ghz/5.2-ghz frequency synthesizer in 0,4 m cmos technology. Journal of Solid-State Circuits, 35:788794, Mai 2000. Loop lter noise, prescaler and PLL building blocks. Hans-Dieter L ke. Signal bertragung. Springer Verlag, Berlin, 3rd edition, 1985. u u General Communication Theory, Fourier Transformation, PM / FM modulation. S.R. Norsworthy, R. Schreier, and G.C. Temes (Eds.). Delta-Sigma Data Converter: Theory, Design, and Simulation. IEEE Press, New York, USA, 1997. Micheal Henderson Perrott. Techniques for High Data Rate Modulation and Low Power Operation of Fractional-N Frequency Synthesizers. PhD thesis, Massachusetts Institute of Technology, 1997. two-point modulator, dual path loop lter, XOR+ PFD. 189
[Dor92] [Gar79] [GM84] [GT86]
[Kun98] [LB92]
[Lee98] [LR00]
[L k85] u [NSE97] [Per97]
190
BIBLIOGRAPHY
[PK04] [PM96]
Joel Phillips and Ken Kundert. Noise in mixers, oscillators, samplers & logic an introduction to cyclostationary noise. http://www.designers-guide.com, 2004. John G. Proakis and Dimitris G. Manolakis. Digital signal processing (3rd ed.): principles, algorithms, and applications. Prentice-Hall, Inc., 1996.
[RCK93] Tom A.D. Riley, Miles A. Copeland, and Tad A. Kwasniewski. Delta-Sigma Modulation in Fractional-N Frequency Synthesis. IEEE J. Solid-State Circuits, 28(5):553559, Mai 1993. [Roh97] [Smi99] Ulrich L. Rohde. Microwave and Wireless Synthesizers. John Wiley and Sons, New York, 1997. Loop Dynamics, Noise in the Loop. Steven W. Smith. The Scientist and Engineers Guide to Digital Signal Processing. California Technical Publishing, San Diego, USA, 2nd edition, 1999. http://www.DSPguide.com.
[VFL+ 00] Cicero S. Vaucher, Igor Ferencic, Matthias Locher, Sebastian Sedvallson, Urs Voegeli, and Zhenhua Wangothers. A family of low-power truly modular programmable dividers in standard 0.35- m cmos technology. Journal of Solid-State Circuits, 35:10391045, Jul. 2000. Dual- and Multi-Modulus Divider Concepts.
Christian M nker u
December 20, 2005
List of Figures
1.1 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15 2.16 2.17 2.18 2.19 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 3.20 Phase noise and spurious sidebands on the VCO output . . . . . . . . . . . . 11 PLL block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PLL block diagram - control theory point of view . . . . . . . . . . . . . . . 16 Closed loop gain |T ( j )| and noise bandwidth Bn . . . . . . . . . . . . . . . 18 Bode plot for open loop gain of type I, 2nd / 3rd order PLLs . . . . . . . . . . 19 Averaging loop lters of 1st / 2nd order (no zero) . . . . . . . . . . . . . . . 20 Root locus diagram for typ I, rst order PLL . . . . . . . . . . . . . . . . . . 21 Step response parameters: Overshoot, settling and steady-state error . . . . . 23 Step Response and Frequency Response of Type I, 2nd Order PLL . . . . . . 24 Averaging Loop Filters of 1st / 2nd order (one zero) . . . . . . . . . . . . . . 25 Bode Plot for Open Loop Gain GH( j ) of Type I, 2nd / 3rd order PLLs (one zero) 26 Bode Plot for Open Loop Gain GH( j ) of type II, 3rd / 4th order PLL . . . . 27 Integrating Loop Filters of 1st / 2nd / 3rd order (one zero) . . . . . . . . . . . 27 Root locus diagram for typ II, second order PLL . . . . . . . . . . . . . . . . 28 Step Response and Frequency Response of Type II, 2nd Order PLL . . . . . . 29 Dual Path Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Impedance of Averaging Loop Filter (1 pole, no zero) . . . . . . . . . . . . . 32 Input Impedance of Averaging Loop Filter (1 pole and 1 zero) . . . . . . . . 33 Loop Filter Impedance / Effective Capacitance of Integrating Loop Filter . . . 34 Spectra of Pulses for (Non) Integrating Loop Filter . . . . . . . . . . . . . . 35 Multiplier symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Average multiplier output signal ud as function of phase error e . . . . Average multiplier output signal ud as function of frequency error fe . . Timing diagram for EXOR PD with identical frequency at its inputs . . Timing diagram for EXOR PD with different frequencies at its inputs . EXOR schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EXOR average output signal ud as function of phase error e . . . . . . Average EXOR output signal ud as function of frequency error fe . . . . EXOR+FD schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . Average EXOR+FD output signal ud as function of phase error e . . . Average EXOR+FD output signal ud as function of frequency error fe . Signals in the EXOR+ PD when fre f > fdiv . . . . . . . . . . . . . . . Signals in the EXOR+ PD when fre f = fdiv (div < re f . . . . . . . . . JK Flip-op schematic (neg. edge triggered) . . . . . . . . . . . . . . . Average JK Flip-op output signal ud as function of phase error e . . . Average JK Flip-op output signal ud as function of frequency error fe . Tristate PFD schematic . . . . . . . . . . . . . . . . . . . . . . . . . . Average Tristate PFD output signal id as function of phase error e . . . Average Tristate PFD output signal ud as function of frequency error fe EXOR with bidirectional charge pump and integrating loop lter . . . . 191 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 39 39 40 40 40 41 41 42 42 43 43 44 44 45 45 46 46 47 47
192
LIST OF FIGURES
3.21 3.22 3.23 3.24 3.25 3.26 3.27 3.28 3.29 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 5.1 5.2 5.3 5.4 5.5 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11
EXOR with unidirectional charge pump and integrating loop lter Basic 2/3 divider cell . . . . . . . . . . . . . . . . . . . . . . . . Signals in a 2 / 3 divider cell . . . . . . . . . . . . . . . . . . . . An 8/9 dual modulus prescaler . . . . . . . . . . . . . . . . . . . Dual-modulus divider . . . . . . . . . . . . . . . . . . . . . . . . Signals in a dual-modulus divider . . . . . . . . . . . . . . . . . Multi-modulus divider made from a Chain of 2/3 divider cells . . Improved 2/3 divider cell with modulus enable . . . . . . . . . . D-Flip-Flop in current mode logic . . . . . . . . . . . . . . . . .
. . . . . . . . .
. . . . . . . . .
. . . . . . . . .
. . . . . . . . .
. . . . . . . . .
. . . . . . . . .
48 48 49 49 50 50 50 51 51
Frequency synthesizer using fractional-n techniques . . . . . . . . . . . . . . 54 Timing diagram of 1st order fractional-N PLL . . . . . . . . . . . . . . . . . 55 Quantization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Spectral density of quantization noise . . . . . . . . . . . . . . . . . . . . . 57 Spectral density of quantization noise with oversampling . . . . . . . . . . . 57 Delta modulation and demodulation . . . . . . . . . . . . . . . . . . . . . . 59 Delta modulation signal forms . . . . . . . . . . . . . . . . . . . . . . . . . 59 Analog-to-Digital Converter using sigma-delta modulation . . . . . . . . . . 60 Digital delta-sigma modulation . . . . . . . . . . . . . . . . . . . . . . . . . 61 Digital integrator (one sample delay) . . . . . . . . . . . . . . . . . . . . . . 61 Digital integrator (no delay) . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Digital delta-sigma modulation - equivalent represenation for quantization noise 62 Second order digital sigma-delta modulator . . . . . . . . . . . . . . . . . . 63 Second order digital sigma-delta modulator . . . . . . . . . . . . . . . . . . 63 Non-Integrating Loop Filters . . . . . . . . . Realization of an IIR lter in direct form I . . Realization of an IIR lter in direct form II . IIR implementation of 1st order RC low pass Integrating Loop Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 67 67 68 69 84 84 86 87 88 91 91 94 95 98 99 100 101 102 104 105 106 106 107 108
Spurious generation due to reference frequency leakage . . . . . . Block schematic of a PLL . . . . . . . . . . . . . . . . . . . . . . Comparison of single and double sided notation . . . . . . . . . . Periodic Disturbance of Control Voltage . . . . . . . . . . . . . . Disturbance Caused by DC Leakage Current IL . . . . . . . . . . Spectra of Single Short Pulses v p (t) . . . . . . . . . . . . . . . . Spectra of Periodic Short Pulses ve (t) . . . . . . . . . . . . . . . Mismatch of Charge Pump Currents . . . . . . . . . . . . . . . . Instant Frequency and Spectra of Divided, FM Modulated Signals Characteristic behaviour of alpha spurs . . . . . . . . . . . . . . . Spurious generation due to downsampling of RF components . . . Example for downsampling the TX output into the reference path . Characteristic behaviour of beta spurs for D = 4 . . . . . . . . . . Spurious generation due to system frequency harmonics . . . . . . Characteristic behaviour of Gamma-spurs . . . . . . . . . . . . . Spurious generation due to reference frequency leakage . . . . . . Spurious generation due to system frequency leakage . . . . . . . Reference / system frequency modulating the VCO . . . . . . . . Spurious generation due to modulation of LO buffer and divider . LF injection into the system frequency path . . . . . . . . . . . .
10.1 Upconversion of Noise Around the Carrier f0 . . . . . . . . . . . . . . . . . 124

LIST OF FIGURES
193
10.2 10.3 10.4 10.5
PLL Block Diagram Showing Various Noise Sources . . . . . . . Noise Transfer Function for Reference Clock, Divider and PD / CP Noise Transfer Function for VCO . . . . . . . . . . . . . . . . . Open loop VCO phase noise at an offset of fm from the carrier . .
. . . .
. . . .
. . . .
. . . .
. . . .
. . . .
124 125 125 132
B.1 Equivalent Circuit for Noise of RC Lowpass . . . . . . . . . . . . . . . . . . 151 B.2 Noise transfer function and equivalent noise bandwidth . . . . . . . . . . . . 152 C.1 C.2 C.3 C.4 C.5 Switched Signal . . . . . . . . . . . . . . . . Switched white noise, narrow pulses . . . . . Switched white noise, wide pulses . . . . . . Switched bandlimited noise, narrow pulses Switched bandlimited noise, wide pulses . . . . . . . . . . . . . . . 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 154 155 156 156
D.1 Instant Frequency and Spectra of FM Modulated Signals . . . . . . . . . . . 162 F.1 G.1 G.2 G.3 G.4 Root locus plot of C(s) as varies with constant n . . . . . . . . . . . . . . 174 PDF of random process with Gaussian distribution Gaussian Distribution for m=2 and = 1 / = 3 . Error Function erf(x) . . . . . . . . . . . . . . . . Bessel Functions 0th to 3rd order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 178 179 181
Christian M nker u
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194
LIST OF FIGURES
Christian M nker u
December 20, 2005
List of Tables
2.1 3.1 4.1 8.1 Attenuation of RC Lowpass Filter . . . . . . . . . . . . . . . . . . . . . . . 35 Overview of Phase Detector Types Suitable for Frequency Synthesis . . . . . 37 Operation of Phase Accumulator (Fmod = 5) . . . . . . . . . . . . . . . . . . 56 Operation of Phase Accumulator (Fmod = 5) . . . . . . . . . . . . . . . . . . 111
G.1 Function Values of Error Integral (m = 0) . . . . . . . . . . . . . . . . . . . 180
195

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Phase Noise and Spurious Sidebands in Frequency Synthesizers

i=0 0.8 i=1 0.6 i=2 i=3 0.4

Version 3.2 December 20, 2005 Muenker@ieee.org

Phase Noise and Spurious Sidebands in Frequency Synthesizers v3.2

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3.5.1 3.5.2 3.5.3 3.5.4 VCO .

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III Phase Noise and Jitter

Phase Noise and Spurious Sidebands in Frequency Synthesizers v3.2

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Phase Noise and Spurious Sidebands in Frequency Synthesizers v3.2

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Phase Noise and Spurious Sidebands in Frequency Synthesizers v3.2

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Phase Noise and Spurious Sidebands in Frequency Synthesizers v3.2

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Around The Loop in a Day

2.1 Basic PLL Theory

with a divider by N can also be treated as well see soon.

Around The Loop in a Day

= e,re f (t) e,div (t) = e (t)

0t + e,re f (t) 0t + e,div (t)

where the second part could be dened as excess frequency.

2.1 Basic PLL Theory

vco = FR + Kvco vctrl (t)

are Current Controlled Oscillators (CCOs) as well.

Phase Noise and Spurious Sidebands in Frequency Synthesizers v3.2

December 20, 2005

Around The Loop in a Day

div (t) = vco (t)/N div (t) = vco (t)/N

Phase Detector / Charge Pump

Figure 2.1: PLL block diagram

vco, vco G(s)

PD / CP / LF / VCO Divider H(s)

cut here to open loop

0 (s) Kvco = K F(s) e (s) s

Phase Noise and Spurious Sidebands in Frequency Synthesizers v3.2

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2.1 Basic PLL Theory

Phase Noise and Spurious Sidebands in Frequency Synthesizers v3.2

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Around The Loop in a Day

log |C(j )| log N 3dB f 3dB B f n

2.2 Type I PLLs (Averaging Loop Filter)

2.2 Type I PLLs (Averaging Loop Filter)

Open Loop Gain (dB)

Type I, second order PLL

Around The Loop in a Day

to VCO VPD= ICPR1 PD PD/CP C1 C2 I CP= VPD / R1 R1 R2 R2

2nd pole 1st pole 1st pole

N KO N = 2 sN (s/1 + 1) + KO s N/(KO 1 ) + sN/KO + 1 N

Natural Frequency and Damping Ratio for a Type I PLL

Natural Frequency : Damping :

Phase Noise and Spurious Sidebands in Frequency Synthesizers v3.2

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2.2 Type I PLLs (Averaging Loop Filter)

Around The Loop in a Day

Final Value Theorem

lim h(t) = lim sH(s)

for k = 0 for k = 1 for k 2

(pulse response) (step response) (ramp response) (2.2.10)

Settling time and rise time for Type I PLL

= ln( ) = 2 ln( )T1 = (ln 0.9 ln 0.1) 4.4T1

Phase Noise and Spurious Sidebands in Frequency Synthesizers v3.2