EE 179 - Lecture 3

? ? ? ? ? ? ? ? Three-Step Simulation Process Simulation Cycle Delta Cycle Inertial vs. Transport Delay Signal Updating and Driver Queues Signal vs. Variable Projected Output Waveform Resolved Signals

VHDL Simulation
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Mechanics of simulating a VHDL model involves three steps

? Analysis Synonymous with compiling VHDL programs. Analyzer performs the customary syntactical checks, code generation, compilation and places the resulting model in the default design library WORK. Synopsys/Scirocco uses vhdlan for analysis and Xilinx/Modelsim uses vcom ? Elaboration Involves flattening the hierarchical description of the design to produce a netlist of processes. Signals and variables are initialized. The resulting model is ready to be simulated. Synopsys/Scirocco uses scs and Xilinx/Modelsim uses vcom for elaboration ? Simulation Involves execution of the user-defined processes that interact with each other and with the environment. This is done through event generation based on simulation time, and causing the appropriate effected processes to respond to those events. Synopsys/Scirocco uses scsim and Xilinx/Modelsim uses vsim as their simulation engine
Authored by Dr. Tri Caohuu & Vivek Verma

VHDL Simulation
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Three-step simulation process flow chart

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VHDL Simulation : More on Analysis

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Design units contained in files are analyzed to produce hierarchical models that are placed in design library WORK Models in WORK are linked with other user requested design libraries and/or STD (contains STANDARD and TEXTIO) design library that exists in all VHDL environments The order of analysis should always be in a bottom up fashion, starting from lowest-level in the hierarchy and proceeding to higher level Any changes in the entity description file of a low-level module will cause a re-analysis of all dependant modules

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VHDL Simulation : More on Elaboration

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Overall process comprises of following steps

? Flattening of the Design Hierarchy Components are tied with architectures. Also produces a large number of processes representing each low-level component that communicate via nets (signals). ? Elaboration of Declarations - Type consistency, etc done through following the rules that govern the declaration and initialization of signals and variables. ? Storage Allocation Memory allocation for every variable, signal, constant, etc. ? Initialization Signals, variables and constants are initialized to user specified or default values

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VHDL Simulation : More on Simulation

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Simulation is carried out in small units called simulation cycles/step times Every cycle, signal values are computed and any sensitive processes are triggered Signal propagation continues until every signal is updated and all processes finish executing Simulation time advances until a signal driver becomes active or simulation time is TIMEHIGH Simulators are event or cycle based, Synopsys/Scirocco can do both

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VHDL Simulation : More on Simulation

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Flow chart of a simulation cycle for an event driven simulator

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Simulation Cycle vs. Delta Cycle

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Simulation cycle is the simulator step time i.e. a time value at which the clock in the design is being run like 10 ns, 200 ns, etc Delta cycles are used by the simulator to order events within a simulation cycle. A delta cycle has an infinitesimally small delay and it does not appear on the trace waveform produced for analysis. For instance 10 ns + ?, 10 ns + 2 ?

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Simulation Cycle vs. Delta Cycle

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Following example shows a circuit, and its simulation waveform. Notice the second waveform that shows the ordering of delta events at 10 ns

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Simulation Cycle vs. Delta Cycle

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Example Two

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Simulation Cycle vs. Delta Cycle

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Example Three (Prob. 2.3 in text book, Charles Roth)

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Inertial Delay vs. Transport Delay

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VHDL provides for two types of delays

? Transport Delay Intended to model wiring delay. Simply delays the signal by specified delay time
Z1 <= transport X after 10 ns; -- Z1 gets X 10 ns after statement execution

? Inertial Delay Default delay type in VHDL. Used to model gates that do not propagate short pulses. Any signal with a pulse-width shorter than the specified delay time is rejected
Z2 <= X after 10 ns; -- Z2 gets X only if X remains stable for 10 ns after statement execution

(Refer to the reject clause usage for more specific pulse rejection)

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Inertial Delay vs. Transport Delay

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Example One

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Inertial Delay vs. Transport Delay

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Example Two

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Signal Updating and Driver Queues

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Simulator maintains a driver queue for every signal Transactions on a signal produce drivers that are added to that signals driver queue and propagated on to other dependent signals For signals with multiple drivers, a resolution function is used to derive effective (final) value Signals scheduled to receive a constant/new value in the current simulation cycle are updated After exhausting the driver queues for all signals, the simulator moves on to the next simulation cycle

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Miscellaneous Definitions
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Transaction It occurs on a signal when a new assignment has been made to the signal, but the value may not have changed. It is a time-value pair where the value represents a future value of the signal and time represents when the update happens Event An event is a transaction that changes the value of the signal. Thus, every event is a transaction but every transaction is not an event Cycle Simulation This technique computes the steady state response of the circuit at each clock cycle boundary, not taking into account detailed circuit timing. No concept of delta cycle.
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Signal vs. Variable

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Time Dimension

? Operations on a variable are instantaneous as it has no time dimension associated with it. Very similar to variables in procedural languages like C, Pascal ? Operations on a signal take a minimum of one delta cycle and there is a time dimension associated with every change in a signal ? Variables can only be used in processes, procedures and functions. A variable has local scope, which means that it must be declared in the process it is used, and can only be used within that process. Variables retain values over process invocations ? Signals must be declared outside of processes. A signal declared in an architecture has scope throughout the architecture
(There are additional differences regarding synthesis that will be covered later) Authored by Dr. Tri Caohuu & Vivek Verma

Scope

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Signal vs. Variable

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Following example highlights the differences in timing and scope

? Variables declared inside processes and signals outside processes ? Assuming trigger changes at time 10 ns, all variable operations will happen instantaneously at 10 ns, so new values for var1, var2, var3 will be available for other updates at 0 ns + ? ? Signal operations take at least a ? , so they happen at 10 ns + ? . Thus, new values for sig1, sig2, sig3 will not be available for updates on sum and the simulator will use their old values

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Projected Output Waveform

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Assigning a waveform to a signal in one statement Sequence of values where each value is specified with a time element Represented as a sequence of transactions in the driver queue Since this sequence of transactions havent occurred yet, they are called Projected Output Waveform Following example shows a waveform signal assignment

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Resolved Signals
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In practice, signals can have multiple drivers, like buses or circuits based on wired logic. How is the value determined? A signal with multiple drivers must be of a resolved type which has a resolution function associated with it. Signals of resolved types are called Resolved Signals When a resolved signal is assigned a value, the resolution function is automatically invoked to examine all drivers on the shared signal and determine the effective (final) value In the following example, X01Z is a resolved type. The resolution function is shown on the next slide

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Resolved Signals
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Example of resolved type and a resolution function based on the operations of a tri-state bus

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Resolved Signals
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Resolution functions can also be wired-or and wiredand Following tables can be used to modify the example on the last slide

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