B.Sc. (H)-II Sem. Computer Science-2012 Assignment: Paper: CSHT204 Computer System Architecture Instruction: 1. Attempt All questions.

(a) Define fetch, decode phases of instruction cycle. Describe the sequence of micro-operation and flowchart showing register transfer statement of various phases of typical CPU. (b) Formulate a mapping procedure that provides eight consecutive microinstructions of each routine of a typical computer. The operation code has five bits and the control memory has 2048 words. (c) The memory unit of computer has 256K words of 32bits each. The computer has an instruction format with four fields: an operation code field, a mode field to specify one of the addressing modes, a register address field to specify one of 60 processor registers, and a memory address. Specify the instruction format and the number of bits in each field if the instructions in one memory field.

2.

(a) What are the two instruction needed in the basic computer in order to set the E flip-flop to 1 ? (b) Draw and explain of the flow chart of an interrupt cycles. Also explain how multiple interrupts is resolved in the computer system ? (c ) What should be the size of memory address register (MAR) and memory buffer register (MBR) if the magnetic core memory has a capacity of 8000 words of 12 bits each ? 3. (a) Design the control gates associated with the address register (AR) in basic computer with the following register transfer statements: R ' T0 : AR PC R ' T2 : AR IR (0 11) D '7 IT3 : AR M [ AR ] RT0 : AR 0 D5T4 : AR AR + 1 (b) Derive an expression for a speed up factor of a k-segment instruction pipeline. Explain the functioning of a six segment instruction pipeline with its space-time diagram.

(c) A digital computer has a memory unit with a capacity of 16,384 words, 40 bits per word. The instruction code format consists of six bits for the operation part (no indirect mode bit). Two instructions are packed in one memory word, and a 40-bit instruction register IR is available in the control unit. Formulate a procedure for fetching and executing instructions for this computer. 4. (a) What are the purpose of different kind of addressing modes ? An instruction is stored at location 300 with its address field at location 301. The address field has the value 400. A processor register R1 contains the number 200. Evaluate the effective
address if the addressing mode of the instruction is (i) direct (ii) immediate (iii) relative (iv) register indirect. (b) Give the different fields of an Assembly language. Give examples of pseudoinstruction and assembler directive. (c) Give an examples of Zero, One, Two and Three address instructions. 5. (a) Design and explain the address sequencer for the micro programmed control unit having control memory of 128 word. There are 4 status bits in the system. Length of microinstruction is 20 bits out of which 9 bits are used for micro operations. (b) A bus organized CPU which has 16 registers with 32 bits in each, an ALU, and a destination decoder. (i) How many multiplexers are there in the A bus, and what is the size of each multiplexer? (ii) How many inputs are needed for MUX A and MUX B? (iii) How many inputs and outputs are there in decoder? (iv) How many inputs and outputs are there in the ALU for data, including input and output? (v) Formulate a control word for the system assuming that the ALU has 35 operations. (c) Convert A*B+C*D+E*F from infix to reverse Polish notation.