SYLLABUS

EC 401 MICROCONTROLLERS AND APPLICATIONS

Contact Hrs. / Week: 4 Hrs

Contact Hrs. / Semester: 64 Hrs.

CONTENT LIST AND TIMEALLOCATION

CONTENTS

Chapter No. 1 2
')a

Contents Introductionto Microcontrollers Architecture of MCS 8051

Introduction to Advanced Microcontrollers Introduction to PIC Controllers Program Development Tools Instruction Set of 8051 Hardware Features of 8051 and Programming Applications of 8051 TOTAL

No. of Hours 4 8
2 6 4 16 12 12 64

3
5

">64

"1<7 8

\.

"'
"

CONTENTS
CHAPTER -1 INTRODUCTION TO MICROCONTROLLERS Block diagram of microcomputer, microprocessor and microcontroller Microcontroller types - embedded, external memory, Harvard and Princeton RISC and CISC architectures. Microcontroller memory types Evolution of microcontrollers - 4-bit, 8-bit, 16-bitand 32-bit

1-15

CHAPTER - 2 ARCHITECTURE

OF MCS 8051

16 34

Introduction to MCS 8051 family Pin diagram of 8051 with functions Block diagram of 8051 with details of GPR, PC, data pointer, flags, PSW, SP, SFR, I/O ports, counter /timer, serial I/O, data memory, program memory, register banks and stack

CHAPTER 3 INTRODUCTIONTO ADVANCEDMICROCONTROLLERS

35 44

-f-

Features of MCS-96 family Features of MCS-251 family

CHAPTER

-4 INTRODUCTION

TO PIC CONTROLLERS

45-53

Introduction to 16F74

Architectural details and block diagram of 16F74 - CPU, registers,data memory

and program memory CHAPTER

-5 PROGRAM

DEVELOPMENT TOOLS

54 62

--.
..... ~

Definitions of instructions, program and software Machine instruction format, addressing modes and types Tools - Assembler, linker, loader and compiler Flowchart and algorithm Assembly instruction format 8051 data typ~s and directives

iiii8iic~ -

CHAPTER

-6 INSTRUCTION
.

SET OF 8051

63 82
,

Instruction classification

- Data transfer, Arithmetic,

LQgical, Boolean and Branch

groups
CHAPTER

Details of each instruction with examples

-7 HARDWARE

FEATURES OF 8051 ~ND PROGRAMMING

83 -110

Programming model of the 8051

I/O port programming I/O bit manipulation Bit addressable RAM Single bit operation with carry Counter/timer programming in the 8051 Interrupts programming Programming the serial communication interrupt Interfacing external memory
CHAPTER

-8 APPLICATIONS

OF 8051

111-126

Programmable peripheral interface (8255A) 8051 interfacing Switch / LED / relay / buzzer / optocoupler interface Analog to digital converter (ADC) interface Stepper motor interface Digital-to-analog converter (DAC) interface LCD (liquid crystal display) interface Hex keypad interface APPENDIX A SAMPLE PROGRAMS MULTIPE CHOICE QUESTIONS MODEL QUESTION PAPERS

127 -133 134-137 138 --139

'"

INTRODUCTION TO MICROCONTROLLERS
,

BLOCK DIAGRAM OF MICROPROCESSOR

The microprocessor is a general-purpose single-chip central processing unit(CPU) of a digital computer. It is a semiconductor device consisting of electronic logic circuits manufactured by using large scale Integration (LSI) or very large scale integration (VLSI) technique. The microprocessor is capable of performing various computing functions and making decisions to change the sequence of program execution. The main use of a microprocessor is to fetch data, perform extensive calculations on that data and store those calculations in a mass storage device or display the results for human use. The programs used by the microprocessor are stored in the mass storage device and loaded into RAM as the user directs. A few microprocessor programs are stored in ROM. The ROM-based programs are primarily small fixed programs that operate peripherals and other fixed devices that are connected to the system. To make a complete microcomputer, one must add memory, usually readonly program memory (ROM) and random-access data memory (RAM), memory decoders, an oscillator and a number of input/output (I/O) devices, such as parallel and serial data ports. Additionally, special-purpose supporting devices, such as interrupt handlers or counters, may be added.

Address bus Data bus

Control bus

MAR

[ [ (

PC

1Ro
R1

Control
I

IR

. .
.....J

Flag Register

SP
I

Rn

ALU

Interrupt circuits

n general purpose register

Fig. 1.1: Block diagram of a microprocessor

Introduction to Microcontrollers

stack only. This end is usually called the top of the stack. The stack pointer is a register used as a memory pointer. It contains the address of the current top element of the stack.

Memory Address Register (MAR) The MAR is used to hold the address of the locationto or from which data are to be transferred. Interrupt Circuits Normal execution of the program may sometimes be disturbed if some device requires urgent servicing.To achieve this, the device can raise an interruptsignal. An inter' u t from the input/out utdevicefor se,ryJce ...!b~J2r"~;tc;~ssQr. b Interrupt circuits han e sue requ~sts. The proces$or
provides the requested service by executing an aE!E!iate interrupt service routine (ISR).

- "'! Memory Data Register (MDR)

~. l'

~,

-~
.

";:;:::'

The MDR contains the data to be written into or read out of the addressed location.
... .
~ -~.

--- -

Bus Structure
The universal feature in all microprocessors is bus structure. The microprocessor has an internal bus. All the hardware functional units inside a microprocessor are connected to the internal bus . consisting of (a) Address bus (b) Data bus (c) Control bus Addrcss Bus The address bus consists of 20, 24 or 32 parallel signal lines. On these lines the CPU sends

,\".

u.oidirec1l9n;;T-.
Data Bus

the address of the-.!!I~mory 109atioo that is to be written or to be read from. Address bus!s

..

- -"

,.

-~

The data bus consists of 1J.IJ6.!..~~ or ?411.rall1 lines.The data bus lines are bidirectional. signal This means that th.e.~~ r~pjs_!~tlJ'!.9Q~!~f?S line~JLoT merno~ or from a p~rt as ~Ssends" data out on these lines to a memory location or to a port. "" ,~ -- - -ControlBus
.

-- --

TioWrite. - - - -~' -

The CPU sends out.signals_Qnthe cont(ol busto enabL~.~h~ <2utput~ otaddressd memory devicesor port devices. Typical control b~aJ 9r~ Memory Read, Memory Write, I/O Read and
"

-.

---

--

BLOCK DIAGRAM OF MICROCOMPUTER

As shown in Fig. 1.2, every computer system has three basic units: (1) Centralprocessing unit (2) Memory unit (3) Input/Outputunit.

4
Data bus I
"-"

Microcontrollers

and Applications

Mem 0 ry unit

CPU 1- GeneralPurpose
MicroI

L v

---

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I

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Input / Output

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RAM

ROM

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I/O
Port

0.. 1::

Serial COM

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processor I I

Port

L_-

- - - - r--_J

L-

--

- - - -=- - -I - - . -

Address bus

Fig. 1.2: Block diagram of microcomputer

Central Processing Unit

Microprocessor is also called central processing unit (CPU) because it can be designed to do the functions as the central processing unit in a large computer. The Central processing unit (CPU) does arithmetic operations like addition, subtraction, multiplication, division, comparison and logic operations such as AND, OR and XOR. It also regulates the operation of the complete machine. It fetches and interprets and it causes certain parts of the circuitry to respond according to those instructions. The CPU can be considered as the nerve element of the computer's brain. M'rJ1ory Unit The memory unit stores programs, data, calculations and results. Two types of memory are included in the computer: (a) Temporary memory called random-access memory (RAM) (b) Permanent memory called read-only memory (ROM). RAM is sometimes called "main memory". Information stored in RAM exists only as long as power is applied to the computer. When power is removed, the programs and data stored in the RAM are lost unless copied to external permanent memory. The ROM chips are permanently programmed with computer instructions and special data. They are referred to as "firmware" because software is embedded into the hardware. External memory can be attached to the computer by connecting floppy disk drives or hard disk drives.

Input I Output Unit

User communicates with the computer through the input and output units. These user interfaces are called "peripherals". A peripheral is any type of device connected to the basic computer. An input unit allows commands, programs and data to enter the computer. Keyboards, joysticks, game paddles, graphics tablets, light pens, microphones and analog to digital converters (ADCs) are examples of input devices. The computer communicates with our environment and us via an output unit. Monochrome and colour displays, printers, plotters, speaker and digital to analog converters (DACs) are examples of output devices,

1"1. I I
I 'I

Introduction to Microcontrollers

Some devices are used for both input and output. These include the mass storage devices (the floppy disk drives, the hard disk drives, and archival storage tape systems) and MOdulator DEModulators (MODEMs) which enable computer to computer communication over long distances.

BLOCK DIAGRAM OF MICROCONTROLLER

.
Power

,.

Power
distribution

Control store

Reset

Reset
control

...
C/) Q,)

0 C/)

()

a.. Clock timing

t 0 0..

C/)

/' .

'.......

./

0 --

Input & output pins

Clocking

......

RAM

Fig. 1.3: Block diagram of microcontroller

Fig. 1.3 shows the block diagram of a typical microcontroller. It is a true computer on a chip. The design incorporates all of the features found in a microprocessor CPU: ALU, PC, SP and registers. It also has other features needed to make a complete computer: ROM, RAM, parallel 1/0, serial 1/0, counters and a clock circuit. Like the microprocessor, a microcontroller is a general-purpose device, but one which is meant to fetch data, perform limited calculations on that data and control its environment based on those calculations. The prime use of a microcontroller is to control the operation of a machine using a fixed program th9tf; stored in ROM and that does not change over the lifetime of the system. ' ... The desig~ approach of the micro controller is similar to that of the microprocessor. The microprocessor design accomplishes this goal by having a very flexible and extensive set of multipYle instructions. These instructions work in a hardware configuration that enables large amounts of memory and I/O to be~connected to address and data bus pins on the integrated circuit package. Much of the activity in the microprocessor has to do with moving code {lnd data words to and from external memory to the CPU. The architecture features working registers that can be programmed to take part in the memory access process and the instruction set is aimed at speeding up this activity in -order to improve throughput. The pins that connect the microprocessor to external memory are unique, each having a single function. Data is handled in byte or larger sizes. The microcontroller design uses a much more limited set of single- and double-byte instructions that are used to move code and data from internal memory to the ALU. Many instructions are coupled with pins on the integrated circuit package; the pins are Hprogrammable" - that is, capable of having several different functions depending upon the wishes of the programmer. .

Microcontrollers

and Applications

DIFFERENCESBETWEENMICROPROCESSOR AND MICROCONTROLLER

Table. 1.1 showfi he differences between microprocessorand microcontroller Microprocessor Microprocessorshave many operationalcodes (opcodes) for moving data from external memory to the CPU Microprocessors have one or two types of bit-handling instructions Microprocessor is concerned with rapid movement of code and data from external addresses to the chip Microprocessor must have many additional parts to function as a computer Microprocessors are intended to be generalpurpose digital computers Microprocessors contain a CPU, memory addressing circuits and interrupt handling circuits Microcontroller Microcontrollersmay have one or two opcodes for moving data from externill memory to the CPU Microcontrollers have manytypes of bit-handling instructions Microcontroller is concerned with rapid movement of bits within the chip Microcontroller can function as a computer without the addition of external parts Microcontrollers are intended to be specialpurpose digital controllers Microcontrollers have additional features such as on-chip timers, parallel and serial I/O and internal RAM and ROM

Table. 1.1: Differences between microprocessor and microcontroller

MICROCONTRO LLERTYPES
EMBEDDED MICROCONTROLLERS
When all the hardwar~ required to run the appHc,C!!iQD~ provided on the mlcrocontroller chip, it is referred to as an ~~rT1beddedmlcrocOntroller. Fig. 1.3 shows the block diagram of an embedded microcontroller. Power, reset and clock are required to operate the device. I/O pins are provided to allow the interfacing with external devices. .-

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I
I

I I
I
I
I

-.

Merits
.:. Embedded microcontrollers are cheaper .:. They are much more precise and easier to control

II. I

"-"I

::31

Introduction to Microcontrollers

EXETRNAL MEMORY MICROCONTROLLERS

Addressbus

... ,

.
Micro co ntro lier

..., ...

Control bus

... ,...

RAM/ROM

Data bus

,...

Fig. 1.4: Eternal memory microcontro/lers External memory microcontrollers allow the connection of external memory as shown in Fig. 1.4. The design emphasis is on high-speed computation features r~ther than on-chip features, such as RAM and ROM., The difference between microcomputers and microcontrollers becomes very fine here. The e~ternal memory microcontrol~e.rqjffers trom a miGroproce~~9r.in ~hearea of builtin periphei"al features such as timers, interrupt contl'ollers, QMA and I/O devices~The _E!~ernalmemory DUS -can be used to ~_d9r~s meJ!1.o!YQ1appeg 110 devices ~xe~nd thELcapil"Qilities of the microcontroller significantly. When external memory is used with tti~ micJ.Q~ntr()!ler, all the built-in nanrware Tnterfates can also beacceSSed. This featuremakes the microcontroller flexibletor different

applications.
MICROCONTROLLER
PRINCETON (VON

-ARCHITECTURES
ARCHITECTURE

NEUMANN)

Fig. 1.5 shows the block diagram of Princeton architecture. It has COlDDlO..!l.l1lernory storing for instructi?n as well as data. ThE!memory interfac.e unit is responsible for deciding wt}~ther.The..!!l~rnory 'access -isfor instruction fetch or data transfer. The processing speed can beTncreased by using the cQ!Jfept of prefetching:"Wlffi1hiscO'ncept, the time required to execute an Tnstruction can be utilized ., -" ~-.to fetch the next instruction. - -

--- - -

!'9 ro -0

"0 >-

CPU

c: "roO E ro ,... "- c:: 0) 0 "Q..

Fig. 1.5: Princeton (Von Neumann) architecture

~ if
8 Merits
Microcontrollers
and Applications

.:. Princeton architecture simplifies the microcontroller chip design because only one memory is
accessed.

.:. Random access memory (RAM) can be used for both instruction and data storage.
.:. Availability of program counter stack contents allows greater flexibil~ty in developing software.

HARDVARD ARCHITECTURE
Fig. 1.6 shows the block diagram of Harvard architecture.J1.Y.J~.~_~eparate emory banks ,for m storing instruction and data. Harvard architecture executes instructions in fewer irlstruction cycles than the Princeton architecture because of instruction parallelism. Instruction parallelism can be defined as a technique of simultaneous issue and processing of multiple instructions within a single processor(CPU).

;-_.

""

...

>o
<oE Ow E

CPU

...... 0 E w E E <0 "01 0 "(L

>-

Fig. 1.6: block diagram of Harvard architecture

Merits .:. Harvard architecture executes instructions in fewer instruction cycles than the Princeton architecture because of instruction parallelism .:. Harvardarchitecture is suitable for real-timeapplications
~

RISC AND CISC ARCHITECTURES

CISC stands for Complex Instruction Set Computer. CISC has large instruction sets, multiple addressing modes and multiple instruction formats and sizes. Their control is microprogrammed and different instructions take different number of cycles to execute. The control units are complex. RISC stands for Reduced Instruction Set Computer. RISC has relatively less instructions, addressing modes and instruction formats. As a result, a relatively small and simple decoding and executing hardware subsystem of the CPU is required. The chip area dedicated to the control unit is less. There is more area available for other features. In RISC systems, stroamlined operation is accomplished by standard, fixed size of the instruction (equal to the word length and to the width of the data bus) and single-cycle execution of all instructions.

-I.
I ....... "',

Introduction

to Microcontrollers

Rise VERSUS CISC

Table. 1.2 shows the comparison between RISC and CISC.

!
I

CISC CISC stands for Complex Instruction Set ~puter RISC has relatively more instructions, addressing modes and instruction formats. As a result, a relatively large and complex decoding and executing hardware subsystem of the CPU is required. The chip area,dedicated to the control unit is more. There is less area available for other features. ---features. lmpler ang sm'aUer~controlunit results in More complex and larger control unit results re9\;!~d number of design errors and higher in increased number of design errors and reliability. reduced reliability. RISC design approach is ..2.ujt,iJ?I~ for CISC design approach is not suitable for efficient handling of pipelines efficient handling~elines Throughput is less. Througb.putis more. It takes a shorter time to complete the It takes a longer time to complete the design design of a RiSe control unit. Due to shortE2.r of a CISC control unit. Due to longer design design time, the chances of the end product time, the chances of the end product becoming obsolete are 1El.S.becoming obsolete are more. Overall design cost of RISC control unit is Overall design cost of CISC control unit is more less~ .. Because of the simplicity, I~s number of Because of the complexity, more number of instruction formats and standard instruction instruction formats and different instruction lengths, design of -virtual memory lengths, design of virtual memory management subsystem is difficult. management subsystem is easier. Since the total number of instructions in a Since the total number of instructions in a R~SC system is !pa,lI, con;:!2ilerdesign is CISC system is larg~, Gompilerdesign is more sents an simple.r. RISC instruction - set presents a complex. CISC instruction set pre r~ burden on the compiler increased burden on the compiler. The availability of a relatively lQr:.9.e number CISC system d,gesnqt .provide as m any CPU of CPU registers in a RISC permits a more registers as in RISC. Therefore, it does not efficient code optimization stage in a permit efficient code optimization stage in a compiler. . compiler. RISC compiler is :?imRIEtr.CISC compiler is complex
Table. 1.2: RiSe versus CISC

RISC RISC stands for Reduced Instruction Set ~uter RISC has relatively less instructions, addressing modes and inStruction formats. As a result, a relatively small cmd~simPle decoding and execu~ hardware subsystem of the CPU is required. The chip area dedicated to the control unit"is less. There is more area available for other

10 Microcontrollers and Applicatiom

MICROCONTROLLER MEMORY TYPES

The microcontroller memory can be categorized as: (1) Controlstorage (2) Variablestorage CONTROL STORAGE
Control storage is also known as program memory and firmware. Information stored in nonvolatile memory remains intact even if the electricq'!'power is turned off. ~on-v9IatiIe memory is used f6r permanent storaQ..e.The non~ratile memory is known as read only memory (ROM). I! is a broad -class of semiconductor m-emor~es designed for applications where the ratio of read ~perations to write operations is very high. A ROM can b~ written into (programmed) only once. Thereafter information can only be read from the memory. Tne write operation is more complicated than the read operation. The ROM chips are permanently programmed with computer instructions and'special data. .. .. -

TYPES OF CONTROL

STORAGE

The following different types of control store may be available in a microcontroller: Mask ROM (MROM) The mask ROM is the type in which data are permanently stored in the memory during the manufacturing process. Programmable ROM (PROM) The PROM is the type in which the data are electrically stored by the user with the aid of specialized equipment. Erasable PROM (EPROM) The EPROM is a MOS (metal oxide semiconductor) device. The EPROM is electrically programmable by the user, but the stored gcya9an be e(ased either by expo~ure to UV (Ultraviolet) light or by electrical means. The latter type is called an EEPROM (Electrically Erasable PROM) or EAPROM (Electrically Alterable PROM). Flash Memory
.

Flash memory is a QQ!J:Y..oJatilememorv.haLq,an be electricallyerased and reprogrammed.It is a specific type of ~EPROM.that is erased and programmedin large blocks. Flash memory costs far
less than byte-programmable VARIABLE EEPROM. DATA STORAGE

Yolatile memory rEttCiins storeq_i~formation C!.s~loQ~s electrical power supply is on. If the

electrical power is removed, all information stored in the memory wiWb~ lost. Many semiconductor
memories are volatile. Volatile memory is used for temporary storage. Volatile memory is referred to .. -

as random access memory (RAM) and can be read from and written to by the microcontroller(s processor.

I - -. -- -- - -- ..

- -

--

.-

ns

Introduction to Microcontrollers

11

TYPESOF VARIABLE DATA STORAGE

The following different types of variable data storage are available in a microcontroller:
.....

(1) ~its: Single flip-flops ~re called bits. Bit manipulation is efficient and faster. (2) Registers: a-bit (byte) locations accessed by the processor are called registers. The.~!equire .. -

special instructions or addressing modes. (3) Variable RAM: Temporary storage space used for saving and accessing data in a random fashion. It is also known as scratchpad RAM. "-.
<

---

.
,

j f

(4) ~rogram counter stack: A stack, also knowJJ...aslasJin first out (LIFO), can be thought of as a

s.etof registers, one on top of another. Each register can store one value. A stack is a data .-structurewith two principal operations, ~USH and'pOP.A PUSH operation pla~e7anew val~e on top of the stack. The prior top level becomes the seconq level. A.ppP operatiQndoes the -opposite.It readsthe value from the top level, and then removes it so that the prior second level oecomes the new top level. Stack is used to store addresses and data while a subprogram . -...
--

EfXecut~s.

All variable storage is implemented as static random access memory (SRAM). The storage elements used in the static memory are latches, so data can be stored for an indefinite period of time as long as the power is on. Memory refreshing is not necessary.

MICROCONTROLLER VO SPACE
Input-output (I/O) devices are the means through which the microcontroller communicates with the outside world. Because more than one device is usually connected to a computer, some means have to be provided by which a particular device can be selected to participate in a given operation. There are two schemes for addressing I/O devices: (1) Memory mapped I/O scheme (2) 1/0 mapped I/O (Isolated I/O) scheme

MEMORY MAPPED I/O SCHEME

In memory mapped I/O scheme there is only one address space. I/O devices are identified by assigning them unique addresses within the memory address space of the computer. Thus it becomes possible to access I/O devices in the same way as any other memory location. Any instruction that moves data to or from a memory location can be used to transfer data to or from an I/O device. The use of memory mapped I/O offers considerable flexibility in handling I/O operations because any machine instruction and addressing mode that can be used to deal with memory operands can aiso refer to an I/O device.

I/O MAPPED I/O (ISOLATED I/O) SCHEME

In this scheme there are two address spaces: (a) memory address space and (b) I/O address space. In this scheme the addresses assigned to memory locations can also be assigned to I/O devices. I/O transfers may be distinguished from Memory Read and Write operations by including a special I/O control line such as 10/ on the bus. Special instructions such as IN and OUT are needed to perform I/O transfers. The IN instruction may be used to read the data from an input device. The OUT instruction may be used to send data to an output device.

:f
12
Microcontrollers and Applications

EVOLUTION OF MICROCONTROLLERS
Microcontroller models vary in data size from 4 to 32 bits. Four-bit units are produced in huge volumes for very simple applications and a-bit units are the most versatile. Sixteen- and 32-bit units are used in high-speed control and signal processing applications. Many .models feature programmable pins that allow external memory to be added with the loss of I/O capability.

4-BIT MICROCONTROLLERS
In four-bit microcontrollers, the word-bit count is 4. Pin count and package size are reduced to minimize the cost. It still allows the implementation of useful intelligence. 4-bit microcontrollers are the most popular today. 4-bit microcontrollers are intended for use in large volumes as true 1-chip computers. Applications .) Appliances .:. Toys

a-BIT MICROCONTROLLERS
Eight-bit microcontrollers are suitable for ~<l!Lcomputjng tasks and control and monitoring _9P..EI!9~i9ns.ASCII data is stored in byte sizes. Therefore, a-bit word size is the natural choice for data communications. Most integrated circuit memories and many logic functions are arranged in an a-bit configuration that interfaces easily to data buses of a bits. Applications of eight-bit microcontrollers can range from simple appliance control to high-speed machine control and data collection. Different microcontroller manufacturers offer different amounts of internal ROM-and RAM. Memory can be expanded to include off-chip ROM and RAM. In some cases the ROM is an Electrically Reprogrammable Read Only Memory (EPROM). The EPROM . vers~ons can be us~d by the designer in the research and development stage of a product. After the design is finalized, ROM version can be ordered in large quantities. EPROM design is suitable in case the configuration is changed frequently or production volumes are less. Some microcontrollers use fewer external pins to reduce the package size and the cost. Special features' such as analogto-digital (AID) and digital-to-analog (D/A) converters may be included on the chip.The pulse width modulation (PWM) output is useful for controlling motor speed; it can be done using software in the a-bit units.

Applications .:. Simple appliance control .:. High-speed machine control .:. Data collection

16-BIT MICRO CONTROLLERS """"i. ... .... Sixteen-bit microcontrollers are suitable for high-speed control such as control of servomechanisms or for digital sign~1processing (DSP) applications. The 16-bit controllers have beendesignedto take advantageof high-levelprogramminglanguagesin sophisticatedapplications.

- - - --

. _..

"

Introduction to Microcontrollers

13

Applications .:. Control of servomechanisms

such as robot arms

.:. Digital signal processing (DSP) 32-BIT MICROCONTROLLERS Thirty two-bit microcontrollers are suitable for environments in which application programs run under an operating system. The design emphasis is on high-speed computation features rather than on-chip features, such as RAM, ROM, timers and serial ports. The line between microcomputers and microcontrollers becomes very fine here. The 32-bit controllers have been designed to take advantage of high-level programming languages in sophisticated applications. These microcontrollers are called as "embedded controllers" by some manufacturers. Functions needed for I/O, data communications and timing and counting are done by adding supporting chips. Applications .:. Robotics .:. Highly intelligent instrumentation .:. Avionics .:. .:. .:. Image processing Telecommunications Automobiles

t
14

Microcontrollers

and Applications

IMPORTANT POINTS
(... The microprocessor is a general-purpose single-chip central processing unit (CPU) of a digital computer. (... The microcontroller is a true computer on a chip. It has features such as ROM, RAM, parallel 1/ 0, serial I/O, counters and a clock circuit in addition to those found in a microprocessor. (... When all the hardware required to run the application is provided on the microcontroller chip, it

is referredto as an embedded microcontroller. d~a.

instructions in fewer instruction cycles than the Princeton architecture.

I'" Princeton (Von Neumann) architecture has common memory for storing instruction as well as
i

(... Harvardarchitecture uses separate memory banks for storing instructionand data. It executes /
r... CISC stands for Complex Instruction Set Computer. CISC has large instruction sets, multiple

addressing modes and multiple instruction formats and sizes.

I'" RISC stands for Reduced Instruction Set Computer. RISC has relatively less instructions, addressin,g modes and instruction formats. (... Control storage is also known as program memory and firmware. It is non-volatile. r... Volatile memory is referred to as random access memory (RAM) and it is used for variable storage. (.- In memory mapped I/O scheme there is only one address space. I/O devices are identified by assigning them unique addresses within the memory address space of the computer. (... In I/O mapped I/O (isolated I/O) scheme, there are two address spaces: (a) memory address space and (b) I/O address space. In this scheme the addresses assigned to memory locations can also be assigned to I/O devices.

REVIEW QUESTIONS

'-). I..... "I

Objective Type 1. The is a true computer on a chip. 2. architecture has common memory for storing instruction as well as data. 3. architecture uses separate memory banks for storing instruction and data. 4. microcontroller consists of all the hardware required to run the application. 5. In . I/O scheme, there is only one address space. 6. In I/O scheme, the addresses assigned to memory locations can also be assigned
to I/O devices.

.....

Introduction

to Microcontrollers

15

Answers 1. microcontroller 4. Embedded Descriptive Type 1. Explain why EPROM versions of microcontrollers exist. 2. 3. 4. 5. 6. (2)
2. Princeton (Von Neumann) 5. memory mapped

3. Harvard 6. I/O mapped I/O (isolated I/O)

List four major differences between a micropr?cessor and a microcontroller. (4) List four major differences between RISC and CISCo (4) List some applications of microcontrollers. (4) Write a short note on microcontroller memory types. (5) With the help of block diagrams distinguish between Princeton (Von Neumann) and Harvard architecture. (6)

,,'

r-

ARCHITECTURE OF MCS 8051

INTRODUCTION TO MCS 8051 FAMILY

The 8051 microcontroller actually includes a whole family of microcontrollers that have numbers ranging from 8031 to 8751 and are available in N-Channel Metal Oxide Silicon (NMOS) and Complementary Metal Oxide Silicon (CMOS) construction in a variety of package types. 8052 is an enhanced version of the 8051. All the features of 8052 are the same as that of 8051 except the following: (a) Internal ROM: 8KB, (b) Internal RAM: 256B, (c) Timers: 03 and (d) Interrupt sources: 08

FEATURES OF 8051 MICROCONTROLLER

The 8051 architecture consists of the following specific features: (1) Eight-bit CPU with registers A (the accumulator) and B (2) Sixteen-bit program counter (PC) and data pointer (DPTR) (3) Eight-bit program status word (PSW) (4) Eight-bit stack pointer (SP) (5) Internal ROM of 4KB (6) Internal RAM of 128 bytes: (a) Four register banks, each containing eight registers (b) Sixteen bytes, which may be addressed at the bit level (c) Eighty bytes of general-purpose data memory (7) Four flags (8) Thirty-two input/output pins arranged as four 8-bit ports: PO - P3 (9) Two 16-bit timer/counters: TO and T1 (10) Full duplex serial data receiver/transmitter: SBUF (11) Control registers: TCON, TMOD, SCON, PCON, IP and IE (12) Two external and three internal interrupt sources (13) Oscillator and clock circuits

..,

Architecture of MCS 8051

=:1

17

BLOCKDIAGRAMOF 8051 MICROCONTROLLER

Fig. 2.1 and 2.2 show the simplified and detailed block diagram, microcontroller. It consists of the following important functional blocks: (1) Central processing unit (CPU) (2) Intemal memory (3) Special function registers (SFRs) (4) Timers / Counters (5) Serial port (6) Interrupt control (7) I/O ports (8) Oscillator and clock
.
I

respectively,

of 8051

Central Processing Unit (CPU)

The CPU of 8051 does arithmetic operations like addition, subtraction, multiplication, division, comparison and logic operations such as AND, OR, XOR, rotate, cleat and complement. The CPU is can perform bitwise and bytewise manipulations.

Internal Memory
The internal memory stores programs, data, calculations and results. The 8051 has two typesof internal memory: (a) Random access memory (RAM) or data memory and (b) Read only memory(ROM) or program memory.The 8051 has,. separate address spaces for data and program memory. RandomAccess Memory(RAM) The intemal RAM is of 128 bytes rangingfrom OOH 7FH. It is also refenedto as data memory. to ReadOnlyMemory(ROM) The intemal ROM is of 4KB ranging from OOOOH OFFFH.It is also referred to as program to memory. ,.

,.

~
r' .J

I
I

I
I

External Interrupts

...... ())

I Timer 1 Interrupt Control 4K ROM 128 RAM Timer 2 _0-

L.. Q,)(J)

..... c ~ ~c. 0 c

Interrupt Control

Four 110Ports

Osc

Bus control

Serial Port

f TXD RXD

I.

I-

PO P2 ~ Address I Data

P1

P3

Fig. 2.1: Simplified block diagram of 8051 microcontroller

~ n .... 0 n 0 :J -+ a (1) ~ Q :J CL "'0 "'0 n Q =. 0 :J (I'J

Architecture

of MCS 8051

19

Vs

VSS1

-G

-:" I
1 I I I I
I

I I i I I I I I I 1 I I
..

PRQG.RAM ADDRESS REGISTER

BUFFER

SFRs TIMERS

PC
NCREMENTE

I PSEN-I ALE/PROG-' -. 1 EANPP I RST I

1 I I I I

L-

TIMING AND
CONTROL

::::I <5
!;; ~

t!;;
~

:z go::

DATA:S
MULTIPLE

osc
XTAL2

1 XTAL1

------

---------P1.0-P1.7

----------P3.0 - P3.7

I I I I I I I I I I I I I I I I I I I I I I 61 I I I I I I I I I I I I I I I

1
Special Function Registers
The 8051

Fig. 2.2: Detailed block diagram of 8051 microcontroller (SFRs)

has several special function registers (not shown in the block diagram) designated as

A, 8, DPTR, PSW, IP, IE, TCON, SCON, PCON, Po' P1, P2, P3' S~UF etc. All these are..!?~. address~le and some of them.are bitaddressablealso.The SFRscan be accessed by their names Q'rbytheir addresses ranging from 801i to FFH. These are useful in accessing I/O ports, timers/ counters., erial port, power,controlling etc.~Some the addressesfrom 80H to FFH are notdefined s of 0' ,., for SFRs. Attempting to use such addresses may cause unpredictable results. . . --- -;- ~ ~ 1

;; W" r
'

I..,

f
20
Microcontrollers and Applications

Counters and Timers

Manymicrocontrollerapplications require the counting of external events or the generation of precise internal time delays be~een events. Both of these tasks can be accomplished using software techniques. But software loops for counting or timing consume processor time so that more important functions are not done. To relieve the processor of this burden,~w.2..12-mtup.counter~, ~amed TO and T1 , are provided. Each collnter may be programmed to act qS a !imer to count internal clock P~Jse-s or-as counferto counfextemal pulses,} The counters are diviaed into two 8-bit registers called the a
t!.m~~!~JTLO, TL 1) ~!1d l]igb.~<!Hg, J"IjJJ Bytes. AU, ounter actlo,n IS confrontefby b!t states in t~ c timer mode control register (TMOD), the timer/counter control register (TCON) and certain prograrrf

instructions. ~-'
e::-

- -..

-- -

t""

- -~

Serial Port
The 8051 communicates ~ith other devicE?s by sending anq receiving da_ta 121ts seri2-lIy using ac ~e:~aljata goQll'JJunicatio"- ~~~u~. R..=gister SBU Fis ~<? tlQld dat~. Register ~ON controls data comr!J.Y,!1LGatipn. Register PCON controls data rates. Pins RXD and TXD connect to the serial data

network.
~-'
Interrupt

-.

,l

. -

...

~~

-- -

--.....

Control

Interrupt is a hardware signal activated by an I/O device to alert the CPU. Interrupts may be generatedcaus~~~~~ Request ~y s e
.

oe.eraj!Q.n~Q.rprovid~d by the main programThe start of an Int~rrupt PU to suspend the execution ofelitern~1 source~.;.. andarrivalthe e,xecutlonof

the Interrup.t Service Routine (ISRtpresent in program Q1emoJY. After responding to the interrupt, the CPU-returns back to the mmn program which it was executing before the interrupt occurred. Program resumption is done with the help of stac~. The PC (prograr:n counter) address is sayg&tQn ~..$tack ~fore chanQing it to !h_einterrupt ~ddre~.s in RQM. The PC address wm b. r~stored from the stack ~Lan~1 il1struction is executed ~t theD9 of the IS~. Most applications of micr~contro.Uers involve real-time interrupts which require quicker respon~e.\\ -, . Interrupts can be e~le~_or..gisabled unger program control by altering control bits in the inteJIupt enable register (IE). interrupt Briority re.,glster(IP) and timer control register (TCON). Five interrupts are provided in the 8051. The interrupts are of two types: (1) Internal interrupts and (2) External interrupts. ,
~

\ 1

\ I I I
, I

I~ 1\
I
I

Internal Interrupts The followingthree interrupts are generated by internaloperations: (a) Timerflag 0 (TFO) (b) Timerflag 1 (TF1) (c) Serialport interrupt (RI orTI) When a timer/counteroverflo~s, the correspondingtimerflag, TFOorTFl, is sett01.Theflag is clearedto 0 wnen Theresu1tinginterrupfgeneratesa progra'm'camofneappropriate timer subroutine in"memory.If a data byte isreceiv-ea, interrupt bit RI is set to 1 i,nthe qCON register.When a data oyte has been transmitted. interrupt bifTI is set to 1 in SCaN. These are ORed together to provide a single interrupt to the process'or:the serial port interrupt. ,..

- -

.--

ii

Architecture of MCS 8051

21

External Interrupts The following two interrupts are triggered by external signals: (a) INTO (Port.pin P3.2) (b) INT1 (Port pin P3.3) Reset Whenevera high level isappJiedtothe RSTpin, the 8051 enters a resetcondition. ~e!.c"an
~ec~ns12~~~d_!9 _~e,a ~on:mas!<~b~einterru.pt:. A reset is an ~~sol!:ltEZJ;OJJl.lrt~nq t9jur1]~~99Lam adttress O_OO.Q~~nd commence execuung from there. Program counter (PC) is not stored fo"f later programresumption. -"

110 Ports

special circuits like latch, buffer ana driver are Included in these ports. --

Ports represent physical c5>nnecti?n CPLl ~t~_ou!sLd~e_wQIlci of Microcontroller u_s~s them in order to m_Ql)itor control other compon~l'1tsor devices...Physically, port fsa register inside a .or mrer6COiitrolier ~igh js~onngcJ.ea by-~iresto the pins of a 'microcon~ue to tu.n'ctionaTity,' P somepins have multiple roles.There are fourllO gort)(PO"- 3) of 8 lines each. Some of these portscan ba,configurecr.asirf~ or output. In-"" -., _. ~ can performcertain specific functions. addition, po1T -~_.~

--

..

Oscillator and Clock

In order to synchronize all the i~emal operations of the microcontroller, on-chie scillator is l.\~d.~.Jt equires an e~ternal crystal for its operation. A quartz crystal is connected for this'purpcfmrr oy using"flie..reraiTnafsXfAl f~md XfAL2. Different versions of 8051 operate oVer frequencies ranging
~

from1 MHzto 16MHz.

PIN DIAGRAM OF 8051 WITH FUNCTIONS

A pinout of the 8051 packaged in aJQ:pin DIP is shown in Fig. 2.3 with the full and abbreviated names q! the signals for each pin. It is important to note that many of the pins are used for more than one function (thE}alternate functions are shown in parentheses), Not all of the possible 8051 featu res may be used at the same time. Programming instructions or physical pin connections determine the use of any multifunction pins. For-example, port 3 bit 0 (abbreviated P3.0) ll1ay be used as a generalpurpose I/O pin, or as an input (RXD) to~U~ the serial data receiver register. The system designer decides which o~these two functions is to be used and designs the hardware and software affecting that pin accordingly.

Port 1: P 1.0 - P 1.7 (pins 1 - 8)

Port 1 is a bidirectional 1/0 port consisting of 8 lines.
'"

Reset: RST (pin 9)

.

Port 3: P3.0 - P3.7 (pins 10 -17) Port 3 is a bidirectional I/O port consisting of 8 lines. In addition, port 3 provides special functions as listed below:

RSTis ana~tivehig~inputusedt~resettlie microcontroller hichterminates w allactivities.

(I >
'

",J ""
,

22

Microcontrollers-and Applicati<:>ns \J

Port 1 Bit 0 I 1 Port 1 Bit 1 I 2 Port 1 Bit 2 Port 1 Bit 3 Port 1 Bit 4 Port 1 Bit 5 Port 1 Bit 6 Port 1 Bit 7 Reset Input Port 3 Bit 0 (Receive Data) Port 3 Bit 1
(XMIT Data)

P1.0 Pl.l P1.2 Pl.3 P1.4 P1.5 P1.6 P1.7 RSTt

Vee 40

+5V

(ADO)PO.O 39
(ADl)PO.l

I Port0 Bit 0

I3
I
4

38

IPort0 Bit 1 1) (Address/Data

I Port 0 Bit 2
(Address/Data 2)

(Address/Data 0)

(AD2)PO.2 37 (AD3)PO.3 36

I5

I6
I
7

I Port0 Bit3 (Address/Data 3) (AD4)PO.4 35 I Port 0 Bit 4

(Address/Data 4)
I

(AD5)PO.5 34

(Address/Data 5)

Port0 Bit5

I8

(AD6)PO.633 (AD7)PO.732
(Vpp)/EA 31 (PROG)AlE 30 PSEN 29

I Port0 Bit 6
I

(Address/Data 6)

I9

Port0 Bit7
(Address/Data 7) External Enable (EPROMProgramming Voltage) Address latch Enable (EPROMProgramPulse) ProgramStore Enable

10 P3.0{RXD) 11 P3.l(TXD) 12 P3.20NTO)

13 P3.3C1NTl)

Port3 Bit 2 (Interrupt 0)

Port 3 Bit 3 (Interrupt 1) Port 3 Bit 4 (Timer 0 Input) }

(AI5)P2.7 14 P3.4(TO) (A14)P2.6

281 27

(Address 15) Port 2 Bit 7 Port 2 Bit 6 (Address 14)

Port 3 Bit 5 (Timer 1 S"put)

Port3 Bit 6 (Write Strobe) Port 3 Bit 7 (Read Strobe) Crystal Input 2 CrystalInput 1

15 P3.5(Tl)

(A13)P2.5 26
(A 12)P2.4

Port 2 Bit 5 (Address 13) Port2 Bit 4 (Address 12) Port2 Bit 3 (Address 11)

16 P3.6(WR) 17 P3.7(RO)
18 XTAL2

25

(A11)P2.3 ,24
(A10)P2.2 23

Port 2 Bit 2 (Address 10)

I

19 XTAL1

(A9)P2.1 22

Port2Bit 1
(Address 9)

I
,<-... I "
I

Ground

I 20

Vss

(A1P2.0

21 I (Address 8) Port 2 BitO

Note: Alternate functions are shown be'low the port name (in parentheses). Pin numbers and pin names are shown inside the DIP package. Fig. 2.3: Pin diagram of 8051

..

..

Architecture of MCS 8051

23

P3.0 (RXD): Serial input port P3.1 (TXD): Serial output port P3.2 (INTO )': External interrupt with vector 0003H P3.3 (INT1 ): External interrupt with vector 0013H P3.4 (TO): Timer 0 external input P3.5 (T1): Timer 1 external input P3.6 (WR): External data memory write strobe P3.? (RD ): External data memory read strobe

Crystal inputs: XTAL2and XTAL (pins 18 -19) 1:

XTAL 1 is the input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL 1 is the output from the inverting oscillator amplifier.

Ground:

VSS (pin 20)

This is a return (Ground) pin for the supply. It is a OV reference.

Port 2/ High order address bus: P 2.0 - P 2.7/ A8 - A 15 (pins 21

- 28)

Port 2 is a bidirectional I/O port consisting of 8 lines. In addition, port 2 provides high order addressbyte (A8 - A15) through which the 8051 can access 64KB of external memory.

Program Store Enable: PSEN (pin 29)

PSEN is an output pin to access the external program memory (ROM). It is connected to 'OE (Output Enable)' pin of the ROM chip.

Address Latch Enable / Program Pulse: ALE/ PROG(pin 30)

ALE is an output pin used to perform demultiplexing of multiplexed address/data lines (ADO AD?). It latches the low order address byte (AO - A7). When ALE = 1, the mC sends out address on ADO- AD? Later when ALE =0, data is transferred on these lin~s. This pin is also the program pulse input (PROG ) during EPROM programming.

External Access Enable I EPROM Programming Voltage: EA I VPP (pin 31)

The lowest 4KB of Program Memory can either be in the on-chip ROM or in an external ROM.

This selection is made by strapping the EA pin to either VCC or VSS. If the EA pin is strapped to V'cC,the 8051can access4KB of internalROM (OOOOH- OFFFH) and externalROMof 60KB (1GOGH FFFFH). If the EA pin is strapped to VSS, then all program fetches are directed to external ROM (OOOOH FFFFH).This pin also receivesthe 12.75Vprogrammingsupply voltage (VPP)during EPROM programming.

'l1l

24

Microcontrollers

and Applications

Port 0 I Address Data Bus: P 0.7 - P 0.0 I AD7 - ADO (pins 32 - 39)

Port 0 is a bidirectional I/O port consisting of 8 lines. Port 0' is also the mujtiplexedJow-order
~dress and data bus AD7 - ADO dlJring ~sses.. t9 extemalprogram and data rl}e!!1<?'l"ALE signal Indicates whether address or data is present on these lines. When ALE = 1, address A7 - AO is present. Later when ALE =0, data 07 - DO is transferred on these lines.

VCC: Supply voltage (pin 40)

This is a +5V supply voltage pin.

8051MEMORYORGANIZATION
The 8051 requires memory for program and data. ROM is used for program code and RAM is used for data storage. The 8051 can access 64KB each of ROM and RAM. The 8051 has separate address spaces for program and data memory. The total address space of 64KBis arranged as two parts: (1) Internal (on-chip) ROM/RAM and (2) External ROM/RAM. PROGRAM MEMORY

The Program memory can be up to 64KB long. The lower 4KB can reside on-chip. If the EA pin

is strapped to VCC, the 8051 can access 4KB of internal ROM (OOOOH-OFFFH) and external ROM
of 60KB (1 GOGH - FFFFH) as shown in Fig. 2.4 (a). If the EA pin is strapped to VSS, then all program

fetches are directed to external ROM

(OOOOH

- FFFFH)

as shown in Fig. 2.4 (b). The read strobe to

external ROM, PSEN , is used for all external program fetches. PSEN is not activated for internal program fetches. FFFF FFFF

60K BYTES EXTERNAL OR

64K BYTES EXTERNAL

1000 AND FFFF 4k BYTES INTERNAL

" 0000

0000 (a) Fig. 2.4: Program Memory (b)

-- --

--

'-Architectureof MCS 8051

25 FFFF

INTERNAL

FFI
I I

SFRs DIRECT ADDRESSING ONLY AND DIRECT AND INDIRECT ADDRESSING 0000

64K BYTES EXTERNAL

80 7F

00

Fig. 2.5: Data Memory

DATA MEMORY The 8051 can address up to~!iELP.!J1atamemQf.Y. The 8051 has J.g? qYJ~s of on-chip RAM plus a number of Special Function Registers (SFRs). The lower 128 bytes of RAM can be accessed either by direct addressing or by indirect addressing. Fig. 2.5 shows the data memory organization.

INTERNAL RAM AREA

Fig. 2.6 shows the organization of 128 bytes of internal RAM which can be accessed by both direct and indirect addressing. It can be divided into the following three segments: (1) Register Banks 0-3"

(2) Bit Addressable Area

--;;

(3) ScratchPadArea Register Banks 0-3

There are four register banks of 8 bytes each, ranging from OOHto 1FH (32 bytes). The device defaults to register bank 0 after reset. To use the other register banks1 the user must select them in software. Each register b~anKcontarns eight 1-byte7egisters0 through 7. Reset initializes the stack pointer to location 07H and it is incremented once to start fromlocatfon OSH, which is register ROof.

reg'ister bank1 .

-. -'

--

- ----.

...,-.

--

--

...

Bit Addressable Area

'"' 16 bytes have been assigned for this segment, ranging from 20H to ~H. Each one of the 128 bits of this segment can be directly addressed (0 - 7FH). The bits can be referred to in two ways, both of which are acceptable by most assemblers. One way is to refer to their address (Le., 0 - 7FH). The other way, is with reference to bytes ,gQHto 2Ft!. Thus, bits OH to 7H can also be referred to as bits 20.0 to 20.7, and bits 8H to FH are the same as 21.0 to 21.7, and so on. Each of the 16 bytes in this segment can also be 'addressed as a byte.

'"

-'

:I
26
Microcontrollers and Applications A

7f

General. Purpose Area

30 2F 20 IF 18 11 10 Of
08 07 06 05 04 03 02 01 00 I Byte Addresses

Bt Address A.re Register Bank 3

<'

7F 00

Register Bank 2 Regiier Bank 1 R7 R6 R5 R4 R3 R2 R)

Register Bank 0

RO
fntff'nal RAM

I~
"""

Fig. 2.6: Internal RAM Area

.--

Ins Architecture of MCS 8051 27

SCRATCH PAD AREA 30Hthrough 7FH are availableto the use.L.a~..9atC!J18M. However,if the s~ck pointer has been initializedto this area, enough bytes- should be left aside to prevent SP data destruction. ~ -~~. c- - - .-~ ..._= , REGISTER STRUCTURE OF THE 8051
Reg1sters are used to store opcodes, operands and addresses of memory or I/O devices temporarily. The register structure of the 8051 can be treated as a coJJectionof 8- and 16-bit registers and 8-bit memory locations. These registers and memory locations can be made to operate using the software instructions that are incorporated as part of the design. The registers in the 8051 can.be
.' .

classifiedas follows:

(1) Byte addressable registers (2) Byte and bit addressable registers (3) General purpose registers (4) Special function registers (5) 8-bit registers (6) 16-bit registers (7) RAM independent registers (8) RAM dependent registers (part of RAM) GENERAL PURPOSE REGISTERS

As discussed earlier, the 8051 has an internal RAM of 128 bytes, out of which 32 bytes are kept

aside as general purpose registers (GPRs) ranging from 0 to 1FH (32 bytes). GPRs are organized as
four banks of 8 registers (RO - R7) each. That is, each register bank contains ~ight 1-byte registers ROthrough R7. GPRs are addressed as RO.. ..R7 orOOH 1FH.ln order to access them as RO R7, a particular bank should be chosen in software using 04 and 03 bits of Program Status Word (PSW). The device defaults to register bank 0 after reset.

8051 SPECIAL

FUNCTION

REGISTERS

The 8051 has several special function registers (SFRs) designated as ACC, B, OPTR, PSW, IP, IE, TCON, SCON, PCON, Po' Pl' P2, P3, SBUF etc. These are useful in accessing I/O ports, timers/ counters, serial port, power controlling etc. SFRs can only be accessed by direct addressing. Sixteen addresses in SFR space are both byte- and bit-addressable. The bit-addressable SFRs are those whose address ends in OH or 8H. The SFRs can be accessed by their names or by their addresses ranging from 80H to FFH. Some of the addresses from 80H to FFH are not defined. Attempting to use such addresses may cause unpredictable results. Fig. 2.7 gives a brief look at the special function register (SFR) space. Special function registers can be further grouped as follows: (1) . Math registers (A and B) (2) Interrupt registers (IP and IE) (3) Timer/counter registers (TLO, TL 1, THO and TH1) (4) Timer control registers (TMOO and TCON) (5) Serial data registers (SCON, SBUF and PCON) (6) Program status word (PSW)

...

,.J

"'...

28

Microcontrollers

and Applications

(7) Stack pointer (SP) (8) Program counter (PC) (9) Data pointer (DPH and DPL) (10) Ports (PO, P1, P2 and P3) 8 BYTES
FB
!."

.
8
I

FF F7 EF

FO

E8 EO 08 DO C8 CO 88 80 AS AD 98 90 88 80

A A PSI/V

E7 OF 07 CF C7

IP P3
IE P2

8F

.
SBUF

87 AF A7 9F 97

SCaN
P1 TCON PO

TMOD
SP

TLO DPL

TU OPH

THO

TH1 PCON

8F 87

'"

81T ADDRESSABLE

Fig. 2.7: SFR memory map

Math Registers (A and B)

The accumulator A is used for arithmetic and logical operations. It is used as destination for all addition and subt(action operations. For logical operations this can be used as a source or destination. There are some specific operations like clear, complement, must reside in A register only. rotate and swap for which the operands It can be used

The B register is used for multiplication and division along with the accumulator. as a scratch pad where data may be stored.

jI

Interrupt Registers (IP and IE) Interruptscan be e~ableQor Qisa~d uodJ~!J?r2gr~m controlby a~ering controlbits in the interrupt nableregist~r\fE) andinterrupt riority e p registet (IP). - --f ---

...........

,.....-

Architecture of MCS 8051

29

Timer/Counter Registers (TLO, TL 1, THO and TH1) The 8051has two 16-bit upcounters, namedTOand T1. The counters aredivided intotwo 8-bit registerscalledthe timer low (TLO,TL1) and high (THO,TH1) bytes. Timer Control Registers (TMOD and TCON) All counter pction is controJJ.~dy bit states in TMOD (timer mode control register), TCON b (timer/counter ontrol register) and certainprogrammslructR5ns. c ... ~

Serial Data Registers (SCON, SBUF and PCON)

'1

The 8051 communicates with other devices by sending and receiving data bits serially using

a
..

~~!ia' data communication circuit. Register SBUF (sefia:raata b,uffer}'is ~~ed fo~h<?ldd~ta.,~l)F is Ehy-sicPll-1WQJ~gJsters. On!.is ~rife only~and is ~~~d _tohold data to_Detransmitted out of the 8051. viaTXD(transmitdata).The.2!her1~..pd onlyand bo.lds receiveddat'!from external source~'yJ.9RXD, {receive data). B.th rT1lJtuallyexclusive regtster,s use addresS99F-J.Regi~r.qON (serial control) controls data communication. Register PCON (power control) controls data ~at~. .J
" -0, -,-"

Program Status Word (PSW)

ITagi3 ~which indicates some condition produced by the execution of an instruction or controls,certain operations of the 8051: Certain 8051 instructions cheCKthese flags to determine which of twQ.?ilternative actions should be done in ex_ecutingthe instrLJction~. Fig. 2.8 shows an 8-bit flag register know'h as PSW (prograrl] status word) in the 8051 . PSW is a bit addressable regISter. A

briefexplanationof PSW is as follows:

'

PF (Parity FlagJ PF is set to 1 if the accumulator contains an odd number of 1s. Otherwise it is cleared. CY (Carry Flag)

An additioncauses.CYflag to'be set if there is a carry out of the !X1$1?and a subtraction causes itto be set if a borrow is needed. Other instructionsalso affect this flag. ~~ "_.,' .-

AC(AuxiliaryCarry Flag)

AF is WJ1.1b.~ a carry 9ut of bi.L3during_an addition or ~ borrow bi.bit 3 du~~ 1his flag is used -- - exclusively for ---...-M_'-MBCD arithmetic. OV (Overflow Flag)

s~btraction.

OF is set if an ov.2!1lpY'l ga!ts, i.e., a resu.l! i~ 91}t 01r:ange. Mor_especifically, for additiQn this Q
.

flag is set when there is a c~lry.l!1!~ the~nd

~o carry out of the MSB or _viceversa. For

siThfraction, it is set when the MSB needs a bo!!QY'I. nd t~ere is no borrow-1rom the MSB, or ~ige a versa. The overflow flag will be set if signe-d arithmetic is too large to fit in the destination register or

amemory locatIOn. -- '~ - --

"-

'.

'"

U) 0

Cy

AC

Fa

RSj

RSa

Ov

PSW.7 Carry flag receives carry out

from bit 7 of .A.LUoperands

PS'WO
Parity of accumi.llator set by hardw'are to 1 if It cootains an odd number of 1s; other.vise it is reset m O.

PSvv.6 Aux:ilr.af)' carry flag receivescarr! out from bit 3 of additionoperands.

PSVV.5 General purpose status flag

PSW.1 User-definal~eflag PS'W.2 Ovemowflag set by arithmeiicoperations PSW~ Registerbank select bit 0 Fig. 2.8: 8051 program status word

PSVV.4 Registerbank selectf)it 1

~ n' "'" 0 (') 0,. :J -+"'" 0 (!) "'" (II Q :J 0... -0 -0 (') Q ~ 0 :J V>

L I

,..

.. .""rco' .. -

," ,

"""-',,,..

-.-

Architecture of MCS 8051

31

BankSelection Two bits RS1 and RSOof PSW are used for RAM bank selection as shown in Table. 2.1.
RS1 (PSW.4) 0 0 1 1 RSO lPSW.3) 0 1 0 1 Bank 0 1 2 3

Table. 2.1: RAM bank selection

Stack Pointer (SP)

A stack is a section of memory arranged in last-in-first-out (LIFO) manner. It~~et as..ide to storead and data while a sub ro J.!!Jj$e~tin9: The mem-9IY~ b'(te w~~ mostrecentl store IScalle stack.,Tile stack pointer (SP) an 8-bt re9iste~ that points.-

To the top of stacR. Reset initializes the stack pointer to location 07H. Itis incremented once to start . ~ -from location r-~ which is register ROQ!..r~mistE2~ 08~{ p~r}k1. =f - r --When data is stored on !be staQk the SP vallJe is iocremented by one. When data is retrieve
!Lo v'

.n.te.~tb'y..Q!I.n orderto save and retrJ.ID!eata PUSH/CALL I d

and POP/REi"instructions are used respectively.

Data Pointer (DPTR DPH and DPL)

Data pointer is a 16-bit register. It is op"er

QPTR used for addressing tb.eoff-chip ROtv!~"'iJth is

r~.
FFFFH). "
. ~ ~ .

-bit re ist~ namely reJ-l ;:)ng DPL. of MOVC and MOVX instructions

SinceDPTRis a 16-b!!..r~_g~W", 64KBof '3M/f3L\M ~

.

~ addre~<!iQQ.tt-

t5>

Program Counter

(PC)

The program counter (PC) ~ps track of the e<sec~tion f ~. o It is a 16-blt registe~ th.?.t containsJhe . ~ _. -, 'the -~. memory(ROM)address ofthe~instructioncurrentlybeing~xecut~. Duril1g execu1io[1 - re' .~ r . ,9fthecurrent:ipstructlonl contentsof. e add~ess ! the a ~g.areUQd~~ to c~porJ.D ~tothe. addressof the next instruction to be.executed. It is customary to say that the PC points to'the/ .--: -,..-' instructionthat is to be f~ch~d from the memq!)'.When 8051 js powered up, the Pc. is loaded with OOOOH. Therefore the first instruction byte of a program must reside in ROM location OOOOH. , . ~ .

Ports (PO, P1, P2 and P3) Ports PO... P2 and P3 are 8-bit registers. These are byte addressable as well as bit P1, addressable.

,& ..

32

Microcontrollers

and Applications

SUMMARY Table~2.2 gives the summary of special function registers.

Special function Math Register name *A (Accumulator) *B *IP (Interrupt priority) *IE (Interrupt enable) TLO (Timer/Counter 0 lowbyte) TL1 (Timer/Counter 1 low byte) THO (Timer/Counter 0 high byte) TH1 (Timer/Counter 1 high byte) TMOD (Timer mode) *TCON (Timer control) *SCON (Serial control) SBUF (Serial data buffer) PCON (Power control) *PSW (Program status word) SP (Stack pointer) DPL (Data pointer low byte) DPH (Data pointer high byte) *PO *P1 *P2 *P3 Address EOH FOH B8H A8H 8AH 8BH 8CH 8DH 89H 88H 98H 99H 87H DOH 81H 82H 83H 80H 90H AOH BOH Purpose The accumulator A is used for arithmetic and logical operations. It holds operands in specific operations like clear, complement, rotate and swap. The B register is used for multiplication and division along with the accumulator. It can be used as a scratch pad where data may be stored. Interrupts can be enabled or disabled under program conJrolby l!I!fing ce interrupti enable register (IE) and interrupt priorityregister (IP). The 8051 has two 16bit up counters, named TO and T1. The counters are divided into two 8-bit registers called the timer low (TLO,TL1) and high (THO,TH1) bytes.

Interrupt

Timer/ Counter

Timer control

All counter action is controlled by bit states in TMOD (timer mode control register), TCON (timer/counter control register) and certain program instructions. Register SCON controls data communication.
--

Serial data

Register SBUF is used to hold data. Register PCON controls data rates. PSW consists of PF, CY, AC and OV flags. Two bits RS1 and RSO of PSW are used for RAM bank selection The stack pointer register points to the top of stack. Data pointer is a 16-bit register. It is operated as two 8-bit registers, namely DPH and DPL. DPTR is used for addressing the off-chip ROM and RAMwith MOVC and MOVXinstructions respectively. Since DPTR is a 16-bit register, 64KB of ROM/RAMcan be addressed (OOOOH FFFFH). to Ports PO, P1, P2 and P3 are 8-bit registers. These are byte addressable as wellas bit addressable.

Flags Stack Data pointer

~ -I..
, .,

"

Port

Note: * = byte addressable as well as bit addressable

Table.2.2: Summaryof special functionregisters

-.:.

... --=-~

.-

:II

Architecture of MCS 8051

33

IMPORTANT POINTS

..

Important features of 8051 microcontroller (1) 8-bit CPU (2) 8-bit registers: A, B, RO - R7 (3) 16-bit program counter (PC) and data pointer (OPTR) (4) 8-bit program status word (PSW), stack pointer (SP) (5) Internal ROM of 4KB (6) Internal RAM of 128 bytes (7) Four flags: PF, CY, AC and OV (8) 32 I/O pins arranged as four 8-bit ports: PO- P3 (9) Two 16-bit timer/counters: TO and T1

(10) Two external and three internal interrupt sources and reset (6 interrupts) (11) 1 serial port The flag register in the 8051 is called Program Status Word (PSW). The size of the flag register in the 8051 is 8 bits. 01 (PSW.1) and 05 (PSW.5) are user-definable. RAM bank selection is done as

follows:
RAM Address 00 - 1FH 20 - 2FH 30 - 7FH Description Reqister Banks 0-3 Bit addressable RAM Scratch Pad RAM

I'- RAM address space I'- A stack is a section of memory

stack pointer to location 07H.

arranged in last-in-first-out (LIFO) manner. Reset initializes the

I'- The program counter (PC) keeps track of the execution of a program. When 8051 is powered
up, the PC is loaded with OODOH.

REVIEW QUESTIONS Objective Type

1. The 8051 is a(n) 2. The 8051 has 3. The 8051 family has -bit microcontroller. on-chiptimer(s). pins for I/O.
bits. - as the first location of the stack. for registers RO- R7. for registers RO - R7.

4. The flag register in the 8051 is called 5. The size of the flag register in the 8051 is 6. On power-up, the 8051 uses RAM location 7. On power-up, the 8051. uses bank .
8. On power-up, the 8051 uses RAM locations

..

.J

~ """"

l
~

34
Microcontrollers and Applications

Answers
1. 8 4. PSW 7. 0

2.2 5.8
8. 0
to

3. 32 6. 08
7

Descriptive Type 1. Listthe features of 8051 microcontroller. 2. Write a brief note on 8051 memory organization. (5) (5)
i

3. Explain registerstructureofthe8051 the

(5)

4. Explain the program status word (PSW) of the 8051 (5) 5. Explainthe role of program counter (PC), stack pointer (SP) and data pointer (DPTR) in 8051. (6) (9) 6. Draw the block diagram of 8051 microcontroller and explain.

t
II
I-\..

1(.
I ., ,.,

IS

INTRODUCTION TO ADVANCED MICROCONTROLLERS

OVERVIEWOF MCS 96 MICROCONTROLLERFAMILY
Intel MCS 96 microcontroller family of products is popular for 16-bit e edded microcontrollers. They are found in a variety of embedded applications. The MCS 96 family shares a common core architecture which is register base? The register architecture eliminat~s the aCGumulatpr bottleneck and enables fast context switching. All devices have bit, byte, word 'and 32-bit operations. The highperformance regist~r to register architecture is well suited for complex real-time control applications

suchas hard disk drives, modems, printers, pattern recognition and motor control. FEA TU R ES
.:. .:.

--

On-chip memory Register-to-regis~er arGhitecture

,..-

.:. .:.

Threeoperandinstructions.Buscontrollerfeatures, rogrammable ait-stategeneration w and8- or 16-bitbuswidths , ,. p ,

-

.:. Flat addressability of -. large register files

.:.

Three distinct product lines: . Event Processor Array..--

.
.

HighSpeedInput/Output ~
Motor Control ~

BEN E FITS
.:.
.:.

Lowcost
More compact code than accumulator-based
of 232 registers can be directly

architecture
at any time

.:. Minimum
.:.

addressed

Efficientusage of wide variety of memory and peripheral devices

MCS96 MICROCONTROLLER FAMILYPRODUCT LINES

The MCS 96 microcontroller product family has the following three distinct product lines: (1) High Speed Input/Output (HSIO) Family (2) Event Processor Array (EPA) Family (3) Motor Control Family

.l

36

Microcontrollers and Applicatiom

HIGH SPEED INPUT/OUTPUT (HSIO) FAMILY

The HSIO Family consists of devices that have the High Speed Input/Output sub-system. Key Features .:. Up to 20 MHz operation
.:.

.:. Fast register to register architecture

.:.

Up to 1000 bytes register RAM

Up to 32K internalOTPROM

.:. Dynamicallyconfigurable8- or 16-bitbuswidth .:. 16-bit counter .:. Full duplex serial port

.:. HOLD/HLDA bus protocol .:. Up to 3 dedicated PWM generators .:. 16-Bit watchdog timer
.:.

.:. 8-Channel high speed I/O (HSIO) subsystem .:. 16-bit timer'

.:. Eightchannel 8- or 1a-bit AID converter .:. IDLEand POWERDOWN modes

.:.

Five8-bit I/O ports

Peripheraltransaction server (PTS)on KCand KD

8XC196KB
The 8xC196KB is the first memberof the CHMOS MCS96 controllerfamily. It is available in 8K byte ROM and 8K byte OTPROM versions. All versions feature' 232 bytes of register RAM. The 8xC196KB uses the High-Speed Input/Output (HSIO) structurefor event control. The HSIO has up to 4 input and 6 output,lines and uses either of two 16-bittimer/counters as a time base. Additional features include a hardware-generated pulse width modulator (PWM), a full-duplex serial I/O (SIO) port, a watchdog timer and an 8-channel 10-bit resolution analog to digital (AID) converter. The 8xC196KB has 48 input/output (I/O) lines which are shared with the peripherals. 8XC196KC The 8xC196KC is the next step up in the CHMOS 196 family. It is available in 16K byte ROM and 16K byte OTPROM versions. All versions feature 488 bytes of register RAM. The 8xC196KC is offered in a 20 MHz version, allowing 25% increase in performance. The 8xC196KC has all the peripherals as the 8xC196KB with the following enhancements: (1) Three hardware PWM generators (2) AID converter has both 8- and 10-bit conversion modes with programmable sample and conversion times. (3) Peripheral transaction server (PTS) acts as a microcoded interrupt handler which greatly reduces CPU overhead during interrupt servicing. 8xC196KD
The 8xC196KD has all the features of the 8xC196KC, but has extended The 8xC196KD is available in 32K byte ROM and 32K byte OTPROM versions. 1000 bytes of Register RAM. With the availability of 32K of memory, program level languages becomes much more practical. The 8xC196KD is also offered the on chip memory. Both versions feature development in high in a 20 MHz version.

EVENT PROCESSOR ARRAY (EPA) FAMILY

\
L

The most recent products form the EPA Family.This family of devices has the advanced peripheralswhich include a flexible input/outputsystemand EPA (event processor array).

:I

15

Introduction to Advanced

Microcontrollers

37

Key Features .:. Up to 50 MHz operation .:. Fast register to register architecture
.:.

.:. 3.3 volt operation (NP only)

.:.

Up to 1000 bytes of register RAM Dynamicallyconfigurable 8- or 16-bitbus width Dynamicallymultiplexed/demultiplexed (NP, bus
bus protocol

Upto 512 bytes of internal RAM Enhancedbus controller

NU)

.:. Up to 32K of internal OTPROM

.:. .:.

.:. Up to 1M byte of external addressing

.:.

.:.

Chipselect unit (NP, NU)

.:. HOlD/HlDA

.:. Up to 10 channel event processor array

.:. .:. .:.

Two 16-bittimer/counterswith prescalarand quadrature counting mode Fullduplexserial port with independentbaud rate generat~r Fullduplex synchronous serial port 16-bitwatchdogtimer. IDLEand POWERDOWN modes 3 PWMoutputs (NP,NU) . .:. Up to 8 channel 8- or 1O-bitAID converter .:. PeripheralTransactionServer

.:. Slave port for direct interprocessor communication

.:. .:.
.:.

8XC196NT
The 8xC196NT has 1M byte external addressability. Four of the AID inputs are replaced with the extended address port (EPORT). The four EPORT pins can be used as additional address lines (A 16 - A 19) or standard low speed lIas or.a combination of both. The 8xC196NT has 20 MHz operation.

8XC196NP
The 8xC196NP offers a dynamically selectable multiplexed/demultiplexed bus. Other key features the 8xC196NPare the chip select unit, 1M byte addressing, 3 PWM outputs and 25 MHz of operationat 5 volts.

8XL196NP
The 8xCl 196NP is functionally identical with the 8xC196NP, but offers low power operation (3 volts at 1"3MHz).

80C196NU
The 80C196NU doubles the performance of the 8xC196NP, operating at 50 MHz (5V). The 80C196NU alsofeatures a 32-bit accumulatorimplantedin hardware to increase the performanceof multiply/accumulate instructions.The 80C196NUis pin compatiblewith the 8xC196NP.This feature, alongwith its clock doubling circuitry, enables the 80C196NU to provide a high performance insocketupgrade to 8xC196NP designs. Other key features include 1M byte addressing, 3 PWM outputs,chip select unit and both 40 and 50 MHz (5V) versions.

...

"!~ ..

38

Microcontrollers

and Applications I

MOTORCONTROLFAMILY
The motor control family is c.omprisedof devices that support motor control applications.This family also uses the EPA system for I/O control. . Key Features
.:. Register RAM file .:. On-chip ROM/OTPROM .:. Fast, flexible interrupts .:. Event processor array (EPA)
.:.

.:. High performance CPU .:. Sophisticated three-phase PWM waveform generator .:. Peripheral transaction server (PTS) .:. Two 16-bit timer/counter

16-bitwatchdogtimer

.:. AID converter

.:. Frequency generator module (MD only) .:. Serial I/O (MH only)

8XC196MCIMH

'-

II

The 8xC196MC/MH are members of the MCS 96 motor control family. This device has a peripheral set which is optimized for 3-phase AC induction and DC brushless motor control as well as power

inverterapplications. Some of the specific features are listed below: (1) Waveform generator (WFG): WFG is used to generate 3-phase PWM. The WFG generates three complementary non-overlapping PWM pulses. The WFG features programmable frequency,duty cycle and dead times. (2) PWM generators: There are two PWM generators. These have a common programmable frequency and separately programmable duty cycles and 8-bit resolution. (3) Advanced event processor array (EPA) structure: Advanced EPA structure is used for event monitoring and control. (4) PeripheralTransaction Server (PTS): PTS supports microcoded interrupt processing requiring less CPU intervention. 8xC196MC 8xC196MH (5) (6) (7) (8) (9) (10) (11) (12) (13)
I-~ ""

Register RAM Factory programmed ROM ROM OTPROM AID converter I/O lines Input only lines Capture/comparemodules Compareonly modules

488 bytes 16K bytes 16K bytes 16K bytes 13 channels 40 13 4 4 Not available

744 bytes 32K bytes 32K bytes 32K bytes 8 channels 44 8 2 4 Available

(14) TwochannelUART

"'.,.,

~ ,~ -~ :::~

_1

Ins Introduction to Advanced Microcontrollers

39

8XC196MD
is
The 8xC196MD has all of the 8xC196MC features with the following enhancements: .:. A frequency generator allows generating a programmable frequency square wave, which finds use in infrared remote control communications. )r .:. Twoadditional capture I compare and two compare only modules are added to the event processor array, giving additional event capture and generation capabilities. .:. Eightadditionailia pins, two input only and one analog/digital input pin are added. The 8xC196MD maintains pin-for-pin compatibility with the 8xC196MC device, allowing easy upgrades of existing

designs.

MCS-251MICROCONTROLLER FAMILY
OVERVIEW
MCS 251 architecture is the next generation of Intel MCS 51 architecture. It increases system performance by a factor of five using existing MCS 51 microcontroller code. By rewriting code using the MCS 251 architecture instructions, designers can increase performance up to 15 times. The following list gives an overview of MCS-251 microcontroller family:
.:.

Binarycode compatible with MCS 51 architecture

.:. 5 to 15 times increase in performance compared to MCS 51 microcontroller at the same clock speed .:. 3-stage pipeline CPU architecture
.:.

2 clocks (1 state)~perinstruction

.:. 16-bit internal code bus

. 2 byteslstate code fetch

.:.

8-BitALU

. High speed a-bit source and 16-bit destination bus

. 40 bytes general purpose register file Accessible as sixteen a-bit, sixteen 16-bit or ten 32-bit registers .
.:.

Accumulator functionality and data indexing capability

24-bitlinearcode and data addressing

.:. 64KB stack space .:. New instructions and addressing modes . .
.:.

8, 16 and 32-bit data transfer, arithmetic and logical instructions Supports register, immediate, direct, indirect, displacement, relative and bit addressing

Supports64 interrupt sources

. 1TRAP instru~tioninterrupt (highest priority) . 1 non-maskableinterrupt (2nd highestpriority)

. 62 maskable interruptsources . 4 Interruptprioritylevels