ABSTRACT

This paper presents the design exploration and applications of a spurious-power suppression technique (SPST) which can dramatically reduce the power dissipation of combinational VLSI designs for multimedia/DSP purposes. The proposed SPST separates the target designs into two parts, i.e., the most significant part and least significant part (MSP and LSP), and turns off the MSP when it does not affect the computation results to save power. Furthermore, this paper proposes an original glitch-diminishing technique to filter out useless switching power by asserting the data signals after the data transient period.

There are different entities that one would like to optimize when designing a VLSI circuit. These entities can often not be optimized simultaneously, only improve one entity at the expense of one or more others The design of an efficient integrated circuit in terms of power, area, and speed simultaneously, has become a very challenging problem. Power dissipation is recognized as a critical parameter in modern the objective of a good multiplier is to provide a physically compact, good speed and low power consuming chip. To save significant power consumption of a VLSI design, it is a good direction to reduce its dynamic power that is the major part of total power dissipation. In this paper, we propose a high speed low-power multiplier adopting the new SPST implementing approach. This multiplier is designed by equipping the Spurious Power Suppression Technique (SPST) on a modified Booth encoder which is controlled by a detection unit using an AND gate. The modified booth encoder will reduce the number of partial products generated by a factor of 2. The SPST adder will avoid the unwanted addition and thus minimize the switching power dissipation.

In this project we used Modelsim for logical verification, and further synthesizing it on Xilinx-ISE tool.

CONTENTS
CHAPTER NO NAME OF THE CHAPTER
LIST OF FIGURES LIST OF ACRONYMS I INTRODUCTION 1.1 1.2 1.3 1.4 II Introduction Spurious power suppression technique Realization Issues of the SPST Aim of the thesis

PAGE NO
i ii 1 1 2 5 6 7 7 9 9 12 14 15 17 17 18 20 20 21 23 23 23 24 24

LITERATURE SURVEY 2.1 2.2 Back ground of project Different types of multipliers 2.2.1 Binary Multiplication 2.2.2 Hardware Multipliers 2.2.3 Array Multipliers 2.3 Iterative Techniques

III

SPST Modified Booth Encoder 3.1 Applying the SPST to the Modified Booth Encoder 3.1.1 Block Diagram of MAC 3.2 Booth Encoder 3.2.1 Booths Algorithm (radix-4) 3.2.2 Modified booth encoder 3.2.3 Partial Product generator control Logic 3.2.4 Partial Product Generator 3.3 3.4 3.5 Sign or zero extension Carry-Save Adder Circuit Design Features

IV

IMPLEMENTATION 4.1 4.2 Block diagram of VMFU Explanation 4.2.1 4.2.2 4.2.3 4.2.4 4.3 High-Speed Booth Encoded Parallel Multiplier Design Modified Booth Encoder Partial product generator Truth table of Modified Booth Encoder

27 27 28 29 29 32 33 35 36 36 37 38 38 40 41 42 44

Theoretical power comparison table

RESULT ANALYSIS 5.1 5.2 5.3 5.4 Top module Partial product generator Carry save adder Modified booth encoder

VI VII VIII

CONCLUSION FUTURESCOPE REFERENCES APPENDIX A XILINX APPENDIX B SOURCE CODE APPENDIX C SYNTHESIS REPORT

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