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CODE COMPRESSION ARCHITECTURE FOR ENERGY MINIMISATION IN EMBEDDED SYSTEMS

BY
V.Raviteja
ravi.teja.veguru@gmail.com

P.Venkatesh
venki_919@yahoo.co.in

AudiSankara College Of Engineering & Technology Gudur

Abstract Systems-On-Chip will reach capacities of one billion

transistors in near future. Then we will face a new problem in 1

-2designing of embedded systems which use these high transistor density ICs. The problem is due to complex bus systems which are used to connect different components of the system. These complex bus systems will result an increased contribution to total power consumption of embedded system. In this paper, we present a technique called Adaptive Dictionary Coding that encodes and decodes the data streams on the bus lines. By encoding the data before transmitting over bus systems, and decoding the data after receiving from the bus systems, we can minimize the power consumption of data and address buses. This coding technique exploits the redundancy of data that is being transferred over bus systems and compresses the data. The energy penalty that is introduced by encoder and decoder is taken into account in the evaluation of achieved energy savings. By employing this bus encoding scheme we can save more than 25% of energy on both address and data buses without any performance degradation.

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I. INTRODUCTION Modern VLSI circuits are reaching capacity of billion transistors on a single chip. This leads to new problems in designing such large circuits. The complexity and lengths of bus systems will contribute more to total power consumption of the circuit. More importantly, the distance between two consecutive lines is decreased. So, the parasitic capacitance between two bus lines and bus lines and various layers will increase. As a result, more energy is being consumed to drive such high capacitances. One way to reduce power consumption is to use latest Place and Route Software that avoids side-by-side routing of bus lines. But this will prevent a satisfying solution at a feasible routing time due to complexity of multi-hundred-million gates on a single chip. In this paper, we explain a bus encoder technique to reduce the contribution of bus systems to total power consumption of system. It can be applied in addition even though Place and Route software gives an optimal solution to reduce power consumption.

II. REDUDANCY OF DATA ON GENARAL DATA BUSES In order to measure the redundancy of data a new parameter called Transition Density, is introduced. It is defined as Transition Density D( x) = nx N

n x Number of transitions (a switch of signal from one logic level to another). N Total number of bus accesses.

-4There exists correlation between consecutive data words on general data bus. A typical graph of Transition Densities for different bus lines is shown in figure1.

Transition densities

1 0.8 0.6 0.4 0.2 0 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 Bus Line Numer

Figure 1: Graph showing transition densities in different lines of bus It can be observed that the transition densities on data buses are low for bus lines of significant bits. That indicates the existence of correlation between consecutive data words on a bus. The reasons for low transition density of significant bit bus lines are: (1) Locality of calculation: The result of an operation is close to one of its operands. For example, loop variables are often increased or decreased by one. (2) Data bytes and Boolean variables are extended to words. In these cases, the most significant bits of word are zeros. (3) While running a program, it may use several sets of data simultaneously. In this case the lower part of value of each set may vary but upper sub words of values in each data set tend to be same. (4) The programs favor a few working zones of their address space. That means consecutive memory accesses tend to have consecutive addresses in general except in the case of jump and call instructions.

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III. ADAPTIVE DICTIONARY CODING (ADC) TECHNIQUE This technique exploits the information redundancy in data streams. In this section we give a detailed description of ADC Technique. The original N-bit data word is divided in to three parts Upper part, Index part and Bypassed part as shown in figure 2. Wi , Wb are widths of Index and Bypassed parts correspondingly. The Upper part length will be N-Wi -Wb .

Figure 2: Word structure in ADC Technique The upper part of data word has less transition densities that mean it has repetitions. We can place these Upper parts of data words in a dictionary. Whenever we find a match to a word dictionary, instead of transmitting entire word we can transmit its index in dictionary. If we use a part of current data word as an index, this coding leads to energy savings. The coding scheme is as explained below: The encoder compares the Upper part to the entry indexed by the Index part in dictionary. If the Upper part of current word is identical to the entry, it sends the Index part of the data and Bypassed part together with a separate signal that indicates match found which is called hit signal. The Upper part of bus is put into high impedance state to save the energy. Using the index part received the decoder is able to recover the Upper part from dictionary in decoder which is synchronized with dictionary in encoder. If the encoder fails to find a match to Upper part of data in its dictionary, it sends entire word and a separate signal that indicate match not found which is called miss signal. Then both encoder and decoder update their dictionaries. This ensures the synchronization of the encoder and decoder dictionaries at the end of any memory

-6access cycle. In both cases, the lower part i.e. Bypassed part is sent as it is because it has high transition density. The above explained encoding and decoding schemes are written in the form of algorithms as shown below: ALGORITHM Encoding: Bus. Index_part = Data. Index_part Bus. Bypassed_part = Data. Bypassed_part If EncoderDictionary [Data. Index_part] = Data. Upper_part Bus. Status = 1 Else Bus. Upper_part = Data. Upper_part Bus. Status = 1 EncoderDictionary [Data. Index_part] = Data. Upper_part Decoding: Data. Index_part = Bus. Index_part Data. Bypassed_part = Bus. Bypassed_part If Bus. Status = 1 Data. Upper_part = DecoderDictionary [Bus. Index_part] Else Data. Upper_part = Bus. Upper_part DecoderDictionary [Bus. Index_part] = Bus. Upper_part

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IV. BUS SYSTEM ARCHITECTURE To implement above algorithms we should place encoder and decoder circuits on either side of bus. The total architecture of bus system is as shown in figure 3.

Figure 3: Encoder and decoder architectures of bus system The encoder is composed of one dictionary, one comparator and one tri state gate. When a word is to be sent, the comparator in the encoder compares the output of Upper part of data word and the output of the dictionary that uses the Index part of data word as an address. If two values are identical, a hit signal is given. When the output of the dictionary is not equal the Upper part of the current word, a miss signal is given. The miss signal lets the tri state gate pass the Upper part of the data word and forces the dictionary to update the entry corresponding to the Index part of the data word to Upper part of current data word. The status line of the bus is connected to the output of the comparator. So it contains the information to indicate match found or not. When a word enters the decoder, the Index part of the bus fed into the dictionary in the decoder as an address. In case of a hit, the signal on the status 7

-8line shuts the tri state gate. The output of the dictionary together with the Index part and Bypassed part of the bus forms the decoder output. In case of a miss, the status signal lets the tri state gate pass the Upper part of the bus and write the Upper part of the bus into the dictionary. The Upper part of the bus together with the Index part and Bypassed part of the bus forms the decoder output. V. PERFORMANCE AND COST ISSUES The two table-look-up processes are time consuming parts of encodingdecoding process. For dictionary, we use SRAM, so, the time overhead of dictionary is about 0.4 ns if we use 0.13 m technology. The clock period of the processor using 0.13 m technology (PIII 1.2 G Hz) is 0.83 ns. That means that the dictionary-look-up takes less than half of a clock cycle. So, there will be no performance degradation. The Index part of data word doesnt go to encoding process and appears directly on bus. This results in an early arrival of the Index part on the receiving part. Thus the table-look-up processes the encoder and decoder take place simultaneously. To maximize the energy saving we should take the length of Bypassed part of data word Wb should be zero. But it increases dictionary size and require more memory and also it makes the encoder and decoder circuits complex. To trade off cost and energy saving we take W b = 7 and W i = 4. Simulation test performed by Henkel and others shows that it saves around 25.7% of energy for data buses and 36.6% of energy for address buses.

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VI. CONCLUSION In this paper we presented ADC technique to save energy around 25% in future embedded systems. This is done by encoding and decoding data stream on bus systems. This encoding scheme exploits the property of less transition density on most significant side of data words. Implementation of this technique costs little bit and there will be no sacrifice in performance.

REFERENCES [1] A dictionary-base en/decoding scheme for low power data buses Tiehan Lv, J.Henkel, Haris Lekatsas and Wayne Wolf. IEEE transactions on VLSI systems October 2003. [2] Minimizing memory access energy in embedded systems by selective instruction compression Luca Benni, Alberto Macii, Enrico Macii and Massimo Poncino. IEEE transactions on VLSI systems October 2002. [3] Code compression for embedded systems - Haris Lekatsas and Wayne Wolf. IEEE design automation conference 1998. [4] The data compression book Mark Nelson. [5] Basic VLSI design Douglus A Pucknell, Kamron E Shrughian.