SAN JOSE STATE UNIVERSITY

ARITHMETIC LOGIC UNIT

SENIOR DESIGN PROJECT EE198B
SUBMITTED TO PROFESSOR DR. DAVID PARENT






COLLEGE OF
ENGINEERING






SUBMITTED BY
Arturo Coronado
Juan Tello
Rodger Stamness









SAN JOSE, CALIFORNIA
December 15, 2002

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Table of Contents


Page No.

Title Page.1
Table of Contents2
Abstract.. 3
Introduction4
Technical Specifications5
Timeline/Journal7
Hand Calculations/Floor Plan14
Results...17
Conclusion18
Acknowledgements..19
Verification of Functionality20-52

















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Abstract

This project is the first functional Registered Arithmetic Logic Unit, designed and
tested at San Jose State University. The full custom Integrated Circuit was designed to
have physical redundancy for increased reliability and lifetime. Radiation hardening
techniques were implemented to further improve consistency in performance. Mosis
fabricated and returned the finished ALU. The ALU was then tested with the 500MHz
Agilent Logic Analyzer. The chip functioned as designed with minimal complication.




























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Introduction


In todays market, there exists a lack of sufficient information regarding space
bound circuit applications. Because of national security and copyright implications, it is
very difficult to obtain technical data from NASA or any other organization that builds
space bound ASIC circuits. The proposed solution to this problem is to design and
create a space bound ALU for use in the public domain. But our motives for this project
were twofold; we also wanted to be one of the first groups, if not the first group in the
Electrical Engineering department to design, fabricate and test a digital circuit. Our hope
is that future students interested in digital circuit synthesis will benefit from our
experience and use our report as a guideline to designing circuits at this school.

Design specifications are included initially because they serve as the basis for any
design. As far at technical specifications, we used the specifications from the Philips
74l181. We also listed our own specification in terms of power, area and frequency. To
give the reader a better understanding of the time involved in the design, we included a
timeline of the process. The heart of this report consists of a journal; this journal
discusses the actual steps that we took in planning designing and laying out the circuit;
testing and verification is discussed last. We believe that this part is crucial in giving one
a clear grasp of the amount of work that in involved in circuit design. We end with the
acknowledgements and a conclusion to the process involved.

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Technical Specifications

Pin Configuration

1. Gnd 21. Vdd
2. NC 22. NC
3. S0 23. NC
4. S1 24. Cn+4
5. S2 25. P
6. NC 26. NC
7. S3 27. A=B
8. B3 28. Fo
9. A3 29. F1
10. NC 30. F2
11. NC 31. F3
12. B2 32. G
13. A2 33. INPUT (SCHMITT TRIGGER)
14. B1 34. NC
15. A1 35. OUTPUT (SCHMITT TRIGGER)
16. NC 36. NC
17. B0 37. OUTPUT (VERIFICATION CIRCUIT)
18. A0 38. A (VERIFICATION CIRCUIT)
19. M 39. B (VERIFICATION CIRCUIT)
20. Cn 40. C (VERIFICATION CIRCUIT)


Logic and Arithmetic Functionality


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Timing

The ALU was designed to operate at a clock speed of 25MHz. But functional
verification indicates that speeds of 50MHz and 100MHz are possible but were not
verified for errors as exhaustively as the original 25MHz clock speed.
The clock Layout on the chip was done in such a way such that the ground and
more importantly the 5V power, was crossed only once. This minimized the noise that a
clock can generate on a power lines. This was accomplished by routing the clock around
the perimeter of the chip, the only place the clock was needed. The Flip Flops were at
differing lengths from the source of the clock so to minimize clock skew a 20um wide
lock line was used. This wide clock line acted like a Fat Bus design and no glitching
was seen as a result.

Power

The power consumption of this chip was determined to be 75 mW at 25MHZ and
95mW at 50MHZ and 120 mW at 100MHZ. To determine the power consumption, the
ground for the chip was broken and a Digital Multimeter was inserted to measure the
average current the chip consumed at each clock speed. The functions being
implemented were a cycle of each logic and arithmetic state sequentially run as an
infinite loop, a function provided by the Logic Analyzer.

Size

The IC was designed to fit on an 1800X1800um area and only occupies 60% of
that total footprint. There is a Schmitt Trigger and a 2of3 verification block on the corner
of the chip for further testing applications.

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`




JOURNAL

Selecting a project
On February 15, 2002, we discussed project feasibility. The project had to be big enough
so that it would be done within one year. We wanted fewer than 500 transistors and
discussed potential projects that included a small CPU and an ALU.

While talking to a senior design group that included Juan Gonzalez and Prashanta Lal,
they advised us to do a 4bit ALU because it has about 400 transistors and its complexity
level was attainable for a senior project. Then, on April we talked to our advisor Dr.
Parent. He said that it was a good idea if we added redundancy to the ALU with a
verification circuit on the chip. The same month, we started to do research on three
aspects: space reliability and cost of chips, the effect of alpha particles on chips and the
schematic and layout methodologies.

Research
Current space bound technology is limited to those countries with the money and
resources required for space bound applications. Underdeveloped countries with limited
space budgets or those countries whose beliefs are not consistent with those of developed
countries, lack the technical expertise and resources to implement space programs. There
PHILIPS 74F181 ALU

Increase Reliability
Reverse Engineered
Logic
Cadence Tools
Verify Specs
Mosis
Test
Timeline
Feb.
March
April
May-June 7

June 7-Aug 6
Aug 7
Sept-Nov

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are no libraries for space bound circuits in the public domain. There exist few solutions to
this problem. One solution would be for the aspiring country to join forces with another
country in order to begin a space program. This solution poses many problems for the
developing country, namely that it would have to abide by another countries rules and
demands. This is the case with many countries that choose to work with the United States
or Russia.

The solution to the problem is the implementation of a space bound application
library for use in the public domain. The project will be a space bound ALU for use in
this library; it will be accessible to everyone. This is the best solution to the problem and
it allows the space programs free use of the design, thereby allowing them to focus on
other aspects of their program.

Our finding showed that chips malfunction due exposure to cosmic rays over extended
periods of time. In particular, as alpha partials bombard the surface of the chip, it starts to
fail. This problem leads us to believe that by using multiple contacts, as it is shown in
figure A, can help to prevent contact failure thus extending the life of a chip on space,
and it will also reduce its repairing cost.


Figure A. Multiple Contacts




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At the same time, initially, we wanted to improve reliability one step further by
connecting three ALU in one single chip plus a verification circuit; all three ALUs are to
perform the same operation and the verification circuit checks their outputs, and if two
out of three have the same answer, an answer is given at the output otherwise and error is
given. In figure B, the block diagram of our design is shown.

Two out of three task were completed up to now; reliability and cost, and the effect of
alpha particles on chips. Now, the third task was to select the schematic and layout
methodologies that can be employed to ease our work without trading off its functionality
or efficiency. We started by selecting two possible ALU architecture models, one from
National Semiconductor, and the second from Philips. We selected the Philips 74LSF181
4bit ALU architecture model because it had the simplest and easiest data sheet to
understand.


LOGIC

The Process
After selecting the model, which is shown in figure C, the next task was to select
simplification techniques. Potential techniques were AOI, Boolean and data patha brief
example of each technique will be given in the subsequent paragraphs. We employed all
three techniques, and all of them had advantages and disadvantages; however, we
employed a different technique known as functional cellular building blocks because it is
faster and it has more reliable results.

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Figure C. ALU Gate Model from Philips

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AOI technique
The technique AND-OR-INVERT (AOI) allows the sum-of-products of a Boolean
function in one logic stage. Figure X below shows an example of this technique.


Figure X. AOI Technique

One of the disadvantage of this technique that stop us from using it was that it is limited
to the number of inputs and our design have multiple inputs.

Boolean technique
The main idea of this technique is to start with a truth table that is then used to fill in the
Karnaugh maps. Then, a simplified function is obtained from it so that logic gates are
connected accordingly. The figure XX below shows this technique.

Figure XX




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Data path technique
This technique consists of starting from the output to the input, and collecting all terms
on which the output depends on the inputs. By doing this, every output has its unique
function, which can be further simplified by using Boolean technique. It will end up
having multiple input gates like OR, AND, XOR and other gates. Area consideration and
number of transistor stopped us from going any further.


CELL DESIGN

Functional cell blocks
The main idea is to build small functional cells, test their functionality, and assemble two
or more of these small functional cells in order to build bigger cells and test all of them
every time. For example, the smallest functional cell that can be built is an INVERTER
cell which is shown in figure D, and then a symbol is created which represents its
functionality. Then a test bench is built to test the Inverters functionality, it is shown in
figure E. Its corresponding waveform is shown in figure F .


Figure D. Schematic of an inverter

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Figure E. Test Bench of an inverter



Figure F. Inverter Waveform


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HAND CALCULATIONS

At this point, hand calculations where used to determine proper rise and fall time
response. The following equations were used to calculate
PHL
and
PLH
:

Propagation delay time high to low
HL Iave
V VOH Cload
,
%) 50 ( *



Propagation delay time low to high
LH Iave
VOL V Cload
,
) % 50 ( *



The following equations were used to determine W/L ratios:


1
]
1

,
_

+

1
, 4
ln
,
, 2
) , ( * . Vdd
n Vth Vdd
n Vth Vdd
n Vth
n Vth Vdd nCox PHL
Cload
Ln
Wn



1
1
]
1

,
_

+

1
, 4
ln
,
, 2
) , ( * . Vdd
p Vth Vdd
p Vth Vdd
p Vth
p Vth Vdd pCox PLH
Cload
Lp
Wp




FLOOR PLAN
Below is our initial block diagram of the project. The inputs and outputs of the circuit are
latched. Each of these inputs will then go into all three ALUs. The outputs of the ALUs
are then fed into a circuit that will verify that two out of three ALUs have the same
outputs. The verification circuit then outputs to the latches. This gives the circuit part of
its reliability.


Figure B. Logical Block Diagram

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However, due to potential problems foreseen by our advisor, we made the following
changes to our initial floor plan as it is shown in figure G.


Figure G

All of the components for the project will be designed and fabricated. Because of this,
there is no need to buy any components.

In February, it was decided that the project would be focused around the Philips 74F181
ALU. By March, the goal was to improve reliability and redundancy was introduced. The
months of May and June consisted of the reverse engineering of the logic of the ALU.
The circuit will then be laid out using the Cadence software; this will be completed by
August 7, 2002. The chip will then be thoroughly tested from September to November.























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Results


Positives

The Logic and Arithmetic functions operate as designed and specified in the
Logic and Arithmetic Functionality section of this report.

The clock speed for the chip was designed to be 25MHz. The timing has been
verified to be more than adequate to allow the combinational portion of the circuit to
ripple through from the input registers to the output registers. The chip can operate
functionally at 50 MHz and some simpler operations can be done at 100MHz

The chip has a significant amount of floor space available for future upgrades or
expansion of original design. Approximately 40% of the chip is unused real estate.

The power dissipation was one of the greatest accomplishments of the project.
The original estimate was that the chip might dissipate .166 Watts, where in actuality
the chip used 75mW at 25MHz.

Negatives

A closer inspection of the functionality for the Carry Out bit resulted in the
discovery of a bug. The carry out is generated correctly when the standard arithmetic
operations are performed except for one. The adding of 0000 to 1111 with no carry
in should result in a 1111 with no carry out. The actual result generated a carry.
Without the ability to trace the steps of the combinational logic it is not possible to
explain with certainty where the bug is being generated.

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Conclusion

We consider our project to be a resounding success. The functionality of our chip
worked and we were able to adhere to the power, area and frequency limitations. We
consider the overall process as a great learning experience and believe that the
knowledge we attained will be invaluable in our future endeavors. All three of us
were able to bring something to the table, so to speak. In the planning stages, we
were all able to bring in different perspectives; we feel this increased the quality and
integrity of our project. We hope that this report serves as a blueprint for future
students and would like them to use our chip to learn how to use the logic analyzer.
We also hope that our project is put on the school website so that anyone interested in
our ALU can learn from it. Lastly, we would like to thank our advisor Dr. David
Parent, for taking us on as a senior project and for his unwavering support of us.

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Acknowledgements

David Parent, PhD
Professor Parent was a great sounding board in the initial stages of our project in
EE198A. He provided realistic design obstacles that we as first time designers were
unaware of, this helped steer us out of potential disaster. Professor Parent
coordinated the fabrication of our chip through Mosis. His support of our project
gave us confidence when it came time to present.

Dan Hicks
Dan was crucial in the layout portion of our design; he provided his expertise in
implementing the padframe. There was no LVS option for the padframe, so his
knowledge was our foundation for connecting our logic to the outside world

Juan Gonzales & Prashanta Lal
Juan and Prashanta designed an ALU the semester before us and had many
success and failures. They shared these experiences with our team so we could
benefit from them. The successes we had were directly because of learning from
their mistakes and accomplishments.

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Verification of Arithmetic and Logic Functionality

Included below are the test input vectors and output waveforms from the logic analyze.
Pages 19-21 are the binary input vectors that tested all the logic and arithmetic of the
chip. Pages 20-31 are the actual output waveforms of the functions listed in the
arithmetic and logic table included.

Bus1 0 clk
Bus1 1 F3
Bus1 2 F2
Bus1 3 F1
Bus1 4 F0
Bus1 5 A3
Bus1 6 A2
Bus1 7 A1
Bus1 8 A0
Bus1 9 B3
Bus1 10 B2
Bus1 11 B1
Bus1 12 B0
Bus1 13 S0
Bus1 14 S1
Bus1 15 S2
Bus1 16 S3
Bus1 17 Cout
Bus1 18 Cin
Bus1 19 Mode