PROGRAMMABLE CONTROLLERS

Jerzy Kasprzyk

Lecture: PID Control in PLC

PID is implemented digitally discrete in time, not continuous in time.

1. GE Fanuc
Function blocks PIDISA i PIDIND belong to Control Functions.
(enable)

PID
SP CV

(ok)

(set point) (process variable)

(output)

PV
MAN

UP

DN

(address)

When PID is active, declared Sample Period is compared with elapsed time from the previous algorithm execution. If it is greater then successive iteration is carried out. If calculated CV is outside the range Lower Output Clamp Upper Output Clamp, or it changes faster than declared Minimum Slew Time then CV is limited to appropriate value and value in buffer memory in integral term is adjusted (anti-reset windup).

Calculated CV is also stored in Manual Command register as well as in Internal CV register, assuming PID is in AUTO mode. If the block is in manual mode (Boolean 1 on the input MAN), then CV is equal to the value in Manual Command register, which can be incremented (1 on UP) or decremented (1 on DN). In manual mode the output value can be written manually from a programmer as well.

Features: Bumpless transition between manual and automatic mode Bias can be used as the offset or for Feedforward Control

SP
+

Bias
Derivative Term

Dead Band

Proportional Term Integral Term

Slew Time

Clamp

Polarisation

CV

PV

Fig. 1. Block diagram of PIDISA

Bias

SP
+

Derivative Term

Dead Band

Proportional Term

CV
Slew Time Clamp Polarisation

PV

Integral Term

Fig. 2. Block diagram of PIDIND

Table 1. PID configuration registers Address %Ref + 0 %Ref + 1 %Ref + 2 %Ref + 3 %Ref + 4 %Ref + 5 %Ref + 6 %Ref + 7 %Ref + 8 %Ref + 9 %Ref + 10 %Ref + 11 %Ref + 12 %Ref + 13 %Ref + 14 %Ref + 15 %Ref + 16 %Ref + 17 %Ref + 18 %Ref + 19 %Ref + 20 %Ref + 21 %Ref + 22 %Ref + 23 %Ref + 24 %Ref + 25 %Ref + 26 %Ref + 27 Y Remainder Storage ** Lower Range for SP, PV * Loop Number * Algorithm (PID ISA or PID IND) Sample Period * Dead Band (+) * Dead Band (-) * Proportional Gain * Derivative * Integral Rate * Bias * Upper Clamp * Lower Clamp * Minimum Slew Time * Config Word * Manual Command * Control Word ** Internal SP ** Internal CV ** Internal PV ** Output ** Diff Term Storage * Integral Term Storage ** Integral Term Storage ** Slew Term Storage ** Clock ** (time last executed)
**

Description

Address %Ref + 28 %Ref + 29...34 %Ref + 35...39 Upper Range for SP, PV * Reserved for internal use **

Description

Reserved for external use **

%Ref address of the first configuration register

* **

parameter, that may be set by the user parameter used exclusively by CPU

Fig. 3. Configuration screen for PID

2. Concept
2.1. Library CONT_CTL Seven groups: Conditioning DTIME Dead Time INTEGRATOR Integrator with Output Limit LAG_FILTER Lag Element, 1st Order LDLG Lead/Lag Function with Smoothing LEAD Differentiator with Delay MFLOW Mass Flow Controller QDTIME Dead Time (Simple) SCALING Scaling TOTALIZER Totalling Unit VEL_LIM Velocity Limiter Controller AUTOTUNE Automatic Controller Tuning PI_B Basic PI Controller PIDFF Complete PID Controller STEP2 2-Position On/Off Controller STEP3 3-Position On/Off Controller

Mathematics Output processing

Setpoint management CLC and CLC_PRO (for compatibility with the former CLC and CLC_PRO)

2.2. Modes of functioning Tracking

Manual

Automatic

To optimize CPU scan, the use can declare sampling interval using EN input and function block SAMPLETM belonging to the group Specials in library System.

Function Blocks PIDFF and PI_B see Help in Concept