Microcomputers

Microcomputers

The Input/Output (I/O) System

I/O is the link between the MPU and the outside world. An input port is a circuit through which an external device can send signals (data?) to the MPU. An output port is a circuit that allows the MPU to send signals (data?) to external devices. I/O ports connect both digital and analogue devices by DAC and ADC

Bus
A Bus is a common communications pathway used to carry information between the various elements of a computer system The term BUS refers to a group of wires or conduction tracks on a printed circuit board (PCB) though which binary information is transferred from one part of the microcomputer to another The individual subsystems of the digital computer are connected through an interconnecting BUS system.

Bus There are three main bus groups

ADDRESS BUS DATA BUS CONTROL BUS

Data Bus

The Data Bus carries the data which is transferred throughout the system. ( bi-directional) Examples of data transfers
Program instructions being read from memory into MPU. Data being sent from MPU to I/O port Data being read from I/O port going to MPU Results from MPU sent to Memory

These are called read and write operations

Address Bus
An address is a binary number that identifies a specific memory storage location or I/O port involved in a data transfer The Address Bus is used to transmit the address of the location to the memory or the I/O port. The Address Bus is unidirectional ( one way ): addresses are always issued by the MPU.

Control Bus
The Control Bus: is another group of signals whose functions are to provide synchronization ( timing control ) between the MPU and the other system components. Control signals are unidirectional, and are mainly outputs from the MPU. Example Control signals
RD: read signal asserted to read data into MPU WR: write signal asserted to write data from MPU

Main memory The duties of the memory are :

To store programs To provide data to the MPU on request To accept result from the MPU for storage

Main memory Types

ROM : read only memory. Contains program (Firmware). does not lose its contents when power is removed (Non-volatile) RAM: random access memory (read/write memory) used as variable data, loses contents when power is removed volatile. When power up will contain random data values

Read-Only Memory
uP can read instructions from ROM quickly Cannot write new data to the ROM ROM remembers the data, even after power cycled Typically, when the power is turned on, the microprocessor will start fetching instructions from the still-remembered program in ROM (bootstrap )

Available ROMs
Masked ROM or just ROM PROM or programmable ROM(once only) EPROM (erasable via ultraviolet light) Flash (can be erased and re-written about 10000 times, usually must write a whole block not just 1 byte or 2 bytes, slow writing, fast reading) EEPROM (electrically erasable read-only memory, also known as EEROMboth reading and writing are very slow but can program millions of timesuseless for storing a program but good for say configuration information.

ROM
A0 A1
m+1 bit Address Capacity :

D0 D1 D2

A2 Am

m +1

2 m+1 ( n + 1)
ROM PROM EEPROM

n+1 bit Data

Dn

: OEOutput Enableof uP connect to RD

CE (CS )

: Chip Enable to Address decoder

CE

OE

Timing Diagram for a Typical ROM

A0-Am

D0-Dn

CE

OE
OE falls to data valid Addr valid to data valid

27XX EPROM
U3 10 9 8 7 6 5 4 3 25 24 21 23 2 22 27 20 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 OE PGM CE VPP O0 O1 O2 O3 O4 O5 O6 O7 11 12 13 15 16 17 18 19 U1 8 7 6 5 4 3 2 1 23 22 19 20 18 21 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 OE CE VPP O0 O1 O2 O3 O4 O5 O6 O7 9 10 11 13 14 15 16 17

U2 8 7 6 5 4 3 2 1 23 22 19 21 20 18 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 OE/VPP CE O0 O1 O2 O3 O4 O5 O6 O7 9 10 11 13 14 15 16 17

16 kbit 2 kbyte

2716

2732
32 kbit 4 kbyte

2764
64 kbit 8 kbyte

PGM and VPP are used to programming

27XXX EPROM
U7 U4 10 9 8 7 6 5 4 3 25 24 21 23 2 26 22 27 20 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 OE PGM CE VPP D0 D1 D2 D3 D4 D5 D6 D7 11 12 13 15 16 17 18 19 10 9 8 7 6 5 4 3 25 24 21 23 2 26 27 22 20 1 U5 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 OE CE VPP D0 D1 D2 D3 D4 D5 D6 D7 11 12 13 15 16 17 18 19 10 9 8 7 6 5 4 3 25 24 21 23 2 26 27 1 22 20 28 U6 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 OE/VPP CE VCC O0 O1 O2 O3 O4 O5 O6 O7 11 12 13 15 16 17 18 19 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 24 31 22 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 OE PGM CE VPP D0 D1 D2 D3 D4 D5 D6 D7 13 14 15 17 18 19 20 21

27128
128 kbit 16 kbyte

27256
256 kbit 32 kbyte

27512
512 kbit 64 kbyte

27010
1024 kbit 128 kbyte

28XX E2PROM
12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 24 31 22 32 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 30 1 24 31 22 32 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 OE WE CE VCC D0 D1 D2 D3 D4 D5 D6 D7 13 14 15 17 18 19 20 21

8 7 6 5 4 3 2 1 23 22 19 20 21 18 24

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 OE WE CE VCC

I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7

9 10 11 13 14 15 16 17

10 9 8 7 6 5 4 3 25 24 21 23 2 22 27 20 28

I/O0 A0 I/O1 A1 I/O2 A2 I/O3 A3 I/O4 A4 I/O5 A5 I/O6 A6 I/O7 A7 A8 A9 RDY/BUSY A10 A11 A12 OE WE CE VCC

11 12 13 15 16 17 18 19 1

10 9 8 7 6 5 4 3 25 24 21 23 2 26 1 22 27 20 28

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 OE WE CE VCC

D0 D1 D2 D3 D4 D5 D6 D7

11 12 13 15 16 17 18 19

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 OE WE CE VCC

D0 D1 D2 D3 D4 D5 D6 D7

2816 16 kbit 2 kbyte

2864 64 kbit 8 kbyte

28256 256 kbit 32 kbyte

28010 1026 kbit 128 kbyte

28040 4096 kbit 512 kbyte

RAM (Random Access Memory)

The uP can read the data from RAM quickly, The uP can write new data quickly to RAM RAM forgets its data if power is turned off Two type of is available :
Static RAM(SRAM): ff base, fast, expensive, low cap/vol, applied for cache , no refresh Dynamic RAM (DRAM): cap base, slow , low cost high capacity/volume , applied for main memory(pc) need refresh.

RAM(Static)
m+1 bit Address Capacity :

A0 A1 A2 Am

D0 D1 D2

m +1

2 m+1 ( n + 1)
RAM
CS

n+1 bit Data

Dn
Data bus is Bidirectional

RD

: Read signal connect to MemRD of uP connect to MemWR of uP

WR RD

WR : Write signal CS : Chip Select

to Address decoder