DEVICE TECHNOLOGY FOR NANOSCALE III-V COMPOUND SEMICONDUCTOR FIELD EFFECT TRANSISTORS

A DISSERTATION SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING AND THE COMMITTEE ON GRADUATE STUDIES OF STANFORD UNIVERSITY IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY

Jenny Ruey-Chen Hu December 2011

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 2011 by Jenny Ruey-Chen Hu. All Rights Reserved. Re-distributed by Stanford University under license with the author.

This work is licensed under a Creative Commons AttributionNoncommercial 3.0 United States License. http://creativecommons.org/licenses/by-nc/3.0/us/

This dissertation is online at: http://purl.stanford.edu/hh851xd2122

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I certify that I have read this dissertation and that, in my opinion, it is fully adequate in scope and quality as a dissertation for the degree of Doctor of Philosophy. Philip Wong, Primary Adviser

I certify that I have read this dissertation and that, in my opinion, it is fully adequate in scope and quality as a dissertation for the degree of Doctor of Philosophy. Krishna Saraswat, Co-Adviser

I certify that I have read this dissertation and that, in my opinion, it is fully adequate in scope and quality as a dissertation for the degree of Doctor of Philosophy. Yoshio Nishi

Approved for the Stanford University Committee on Graduate Studies. Patricia J. Gumport, Vice Provost Graduate Education

This signature page was generated electronically upon submission of this dissertation in electronic format. An original signed hard copy of the signature page is on file in University Archives.

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Abstract
As silicon CMOS technology reaches its fundamental scaling limits, alternative materials such as high mobility III-V compounds have proven to be strong contenders for extending high performance logic. However, most promising demonstrations of III-V FET/HEMTs have micron-scale source/drain spacing despite gate lengths on the nanometer scale. III-V semiconductor devices have historically relied on alloyed ohmic contacts which require large spacings to prevent shorting between the source and drain after alloying, where contacts can diffuse up to hundreds of nanometers. This severely limits the scalability of III-V logic technology. Non-alloyed contacts offer a practical route to greatly reduce the III-V device footprint for application in future technology nodes. In this dissertation, I demonstrate a route to non-alloyed contacts by shifting the pinned III-V Fermi level to reduce the metal/n-GaAs and metal/n-InGaAs Schottky barrier heights. The Fermi level is controlled by the insertion of thin dielectrics in a metal-insulator-semiconductor (MIS) contact structure. The MIS contact is studied across a wide range of metal and dielectric materials, and found to have great flexibility in the material selection. I will also discuss the use of bi-layer high- dielectrics, and report results which show that despite an overall thicker dielectric, there is an additional reduction in the barrier height and contact resistance beyond that of a single dielectric MIS. This MIS contact is then integrated in an InGaAs MOSFET as a non-alloyed source/drain contact, though it can also be applied to Schottky Barrier FETs. I will conclude by discussing possible physical mechanisms of the observed barrier height reductions, by examining the effects of fixed charge and electronic dipoles.

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Acknowledgements
First of all, I would like to thank my advisor, Professor H.-S. Philip Wong for all his support and guidance the last few years. I have learned a lot from him in not only in research, but also in my view on life and career. In particular, I really appreciate his positive attitude and excitement towards research, which never fails to motivate me to learn more. I would also like to thank my co-advisor Professor Krishna Saraswat whose doors was always open to me, and eager to help me progress in my research. Next, I would like to thank several of the people who have helped me a lot in both discussions and lab work : Aneesh Nainani, Ze Yuan, Saeroonter Oh, Masaharu Kobayashi, Joseph Chen, Donghun Choi, Eunji Kim, and Byungha Shin. My work also relied heavily on the availability of the ALD tool, and I want to thank Yoonyoung Chung, Yasuhiro Oshima, and J Provine for helping make this possible. I would also like to acknowledge Dr. Jim McVittie for all his expertise and ensuring that that my research would go smoothly. I also need to thank all my friends and colleagues who made my life at Stanford very enjoyable. I feel blessed to have made so many good friends in CIS and in the Nanoelectronics group. Finally, I would like to thank my parents and brother for their wholehearted love and support all these years. This dissertation is dedicated to them.

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Table of Contents
Abstract ... iv Acknowledgements . v Table of Contents vi List of Tables . ix List of Figures.. x Chapter 1. Introduction....1 1.1 Motivation.....1 1.2 Thesis Outline ...5 Chapter 2. Materials Characterization .... 6 2.1 III-V Compound Semiconductors 6 2.1.1 GaAs and InGaAs for III-V FETs..8 2.1.2 Surface Passivation.9 2.2 ALD Dielectrics.. 11 2.2.1 Operation Principle.......11 2.2.2 Process Development ...13 2.2.3 Temperature Dependence .15 2.3 Atomic Stoichiometry by XPS 16 2.4 Density Measurements by XRR..19 2.5 Band Alignment by SRPES..21 2.6 Summary..23

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Chapter 3. MOS Gate Stack...24 3.1 Introduction.24 3.2 III-V MOSCAP26 3.2.1 Device Fabrication Process..26 3.2.2 Electrical Characterization...27 3.3 III-V MOSFET.40 3.3.1 Device Fabrication Process..40 3.3.2 Electrical Characterization...41 3.4 Summary..42 Chapter 4. Single Dielectric MIS Contacts..44 4.1 Introduction.44 4.2 Background..46 4.3 Device Fabrication ..54 4.4 Electrical Characterization...56 4.4.1 Contact Resistance Measurement ....56 4.4.2 Diode Current Measurement....58 4.4.3 Effect of Semiconductor Doping......59 4.4.4 Effect of Metal Work Function..60 4.4.5 Effect of Insulator Material....65 4.4.6 Summary....67 4.5 III-V MOSFET S/D Contacts...... 68 4.6 Summary.73

Chapter 5. Physical Mechanism of Single Dielectric MIS Contact ...74 5.1 Introduction..74 5.2 Fermi-level Pinning Theories...75 5.2.1 Metal Induced Gap States Theory..76 5.2.2 Bond Polarization Theory..78 5.3 Fermi-Level Depinning vs. Shifting.79
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5.4 Fixed Charge84 5.5 Discussion90 5.6 Summary..91 5.7 Future Work.91 Chapter 6. Bilayer Dielectric MIS Contacts....93 6.1 Introduction.....93 6.2 Background.....94 6.3 Device Fabricatrion Process97 6.4 Electrical Characterization..98 6.4.1 Diode Current ..98 6.4.2 Contact Resistance..102 6.4.3 Effective Barrier Height..105 6.4.4 Inverted Dielectric Layers..106 6.4.5 TiO2 Degradation Over Time .107 6.5 Discussion.109 6.6 Summary114 Chapter 7. Conclusions.....116 7.1 Thesis Contributions .116 7.2 Future Directions ...117 7.3 Concluding Remarks ..118 Appendix A : Piece Processing.119 Appendix B : Test Structures & Mask Design...121 Appendix C: MOSFET Fabrication....126 Publications....132 References ..134

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List of Tables
Table 2.1. Table 2.2. Table 2.3. Table 2.4. Table 2.5. Table 4.1. Table 4.2. Summary of electron mobility (e) , hole mobility (p), and band gap (Eg) of several III-V compound semiconductors. ................................................ 6 Growth rate in /cycle for several ALD films at different deposition temperatures. .............................................................................................. 16 Summary of measured atomic concentrations of ALD films. .................... 18 Summary of the fitted density (), thickness (t), and roughness for the Al2O3 / SiO2 / Si structure .......................................................................... 20 Summary of ALD cycles, measured thicknesses, and density.................... 21 Summary of effective barrier heights for several metal work functions with and without an ultrathin 0.7nm Ge3N4 dielectric. ...................................... 51 Summary of effective barrier heights for Al and Au MIS contacts for varying thicknesses of GeOx. Ohmic denotes cases where the on/off current ratio at 1V is less than 10. ........................................................... 51 Table 4.3. Table 4.4. Table 5.1. Table 6.1. Table 6.2. Table 6.3. Summary of Si and Ge MIS contact literature. .......................................... 53 Summary of the ALD precursors and deposition temperature. .................. 54 Summary of how Fermi level depinning and shifting differ in their effect on the MIS contact behavior. ........................................................................... 81 Summary of the ALD precursors and deposition temperature. .................. 98 Electronegativity, work function, and dielectric constant of the elements corresponding to the investigated dielectrics. .......................................... 110 Calculation of and the ratio taken relative to TiO2 for the investigated dielectrics. These values were calculated based on ideal stoichiometry and density values, so the actual value can differ. ........................................... 111

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List of Figures
Figure 1.1. Figure 1.2. Figure 1.3. Figure 1.4. Figure 2.1. Figure 2.2. Figure 2.3. Figure 2.4. Figure 2.5. Figure 2.6. Figure 2.7. Figure 2.8. Figure 2.9. (a) Illustration of Moores Law . (b) The exponential increase in off-state leakage or power is approaching the active power. ..................................... 2 TEM images of MOSFET scaling over the years ....................................... 3 III-V device with a 50nm gate length but m device footprint. ................... 4 (a) LSD and Lgap gate to S/D spacings in a HEMT (b) Decrease in delay as LSD and Lgap are scaled ........................................................................ 4 Universal trend observed in semiconductors between (a) effective mass and bandgap, (b) dielectric constant and bandgap. ............................................. 7 Schematic illustration of different III-V FETs device structures ................. 9 SRPES Ga 3d and As 3d spectra of the GaAs surface after a surface clean and passivation with HCl + (NH4)2S......................................................... 10 ALD Al2O3 reactions using TMA and H2O precursors. ........................... 12 ALD thickness measured across a 4 wafer ............................................... 13 ALD Al2O3 thickness vs. number of cycles. ............................................. 14 ALD growth rate varying deposition temperature and material................. 15 Surface scan of as-deposited HfO2 showing the presence of carbon......... 17 Detailed scans of the (a) Hf4f peak and (b) O1s peak in HfO2. ................ 18

Figure 2.10. XRR measured and simulated intensity for ALD Al2O3 .......................... 20 Figure 2.11. (a) Aligned valence band spectra of Al2O3/GaAs illustrating a EV of 3.2eV. (b) Al2p energy loss spectrum ........................................................ 22 Figure 2.12. Measured band gap and band offsets of (a) Al2O3, (b) TiO2, (c) HfO2, and (d) ZrO2 on GaAs. .................................................................................... 23 Figure 3.1. (a) C-V for Pt/Al2O3/n-InGaAs with 50, 70, and 100 cycles of ALD showing the presence of significant oxide charge. (b) After a FGA at 400oC for 30 min there is VFB alignment across all thicknesses .............. 28 Figure 3.2. MOSCAP C-V of Pt/Al2O3/n-InGaAs across many frequencies from 1kHz
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to 1MHz. (a) as deposited and (b) after FGA ............................................. 29 Figure 3.3. Figure 3.4. As deposited MOSCAP C-Vs for different metal gates. ............................ 30 Pt/Al2O3/n-InGaAs MOSCAP 1MHz C-V measurements for 50, 75, 100, and 125 cycles of ALD Al2O3 before and after annealing for 30 min under iehter inert N2 or forming gas (FG) .......................................................... 32 Figure 3.5. Figure 3.6. Figure 3.7. Current-Voltage leakage measurements of Pt/Al2O3/n-InGaAs MOSCAPs for all annealing conditions. ....................................................................... 33 The midgap DIT and absolute value of the interface sheet charge (QIT) on n-InGaAs before and after various annealing............................................. 35 Pt/Al2O3/p-InGaAs MOSCAP 1MHz C-V measurements for 50, 75, 100, and 125 cycles of ALD Al2O3 before and after annealing for 30 min under iehter inert N2 or forming gas (FG) ........................................................... 37 Figure 3.8. Current-Voltage (I-V) measurements of Pt/Al2O3/p-InGaAs MOSCAPs for all annealing conditions. ............................................................................ 38 Figure 3.9. The midgap DIT and absolute value of the interface sheet charge (QIT) on pInGaAs before and after various annealing ................................................ 39 Figure 3.10. Schematic diagram of the fabricated InGaAs MOSFET. ........................... 40 Figure 3.11. Transfer and output characteristics of a surface channel enhancement mode InGaAs nMOSFET with L=10 m. The FET is measured before and after FGA annealing. ........................................................................................... 41 Figure 4.1. (a) Band diagram of an ideal unpinned Schottky barrier. (b) Band diagram of a pinned Schottky barrier where the effective metal work function M,eff is modeled as differing from the work function in vacuum M. .. 47 Figure 4.2. Figure 4.3. Band information (EC, EV, ECNL) and pinned Schottky barrier heights for high mobility semiconductor materials ...................................................... 48 (a) Schematic band diagram of a pinned Fermi level. (b) Metal/ semiconductor Fermi level depinning, where with an insulator, the metal wavefunction is attenuated in the gap states............................................... 49 Figure 4.4. Figure 4.5. Current-voltage characteristics for Al/GeOx/Ge diodes illustrating Fermi level depinning. .......................................................................................... 51 Contact resistance versus SiN thickness for the Al/SiN/Ge MIS ............... 52
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Figure 4.6. Figure 4.7.

(a) Schematic diagram of the contact structure. (b) Cross sectional TEM image of the Al/SiN/n-GaAs contact .......................................................... 55 There exists an optimal insulator thickness for minimal contact resistance, which arises from the tradeoff between a reduced barrier and and an increased tunneling resistance. ................................................................... 56

Figure 4.8. Figure 4.9. Figure 4.10.

RC measurements of the Al/SiN/n-GaAs MIS shows the expected RC tradeoff with dielectric thickness................................................................ 57 Back-to-back Al/SiN/n-GaAs diode measurement demonstrate the effective modulation of B,eff by the SiN thickness................................................ 58 RC vs. tINS for different substrate dopings. ............................................. 59 a fully self-consistent NEGF simulation .................................................... 60

Figure 4.11. Simulation of the tunneling limited contact resistance of Al/SiN/n-GaAs by Figure 4.12. RC ratio of metal/SiN/GaAs MIS using different metals. .......................... 61 Figure 4.13. Equation and linear fitting used to calculate the ideality factor. ................ 62 Figure 4.14. (a) Diode current measurement across temperature. (b) B,eff extraction from the Arrhenius plot. (c) Equations. ...................................................... 63 Figure 4.15. (a) B,eff is decreases with increasing SiN thickness. (b)The ideality factors increases with SiN thickness ......................................................... 64 Figure 4.16. Effective barrier height vs. metal work function for Schottky diodes and MIS contacts. .............................................................................................. 64 Figure 4.17. Comparison of the RC vs. tINS tradeoff for SiN and Al2O3. .................... 66 Figure 4.18. (a) RC vs. tINS tradeoff for different dielectrics (b) The tunneling barrier height dependence on the conduction band offset. (c) Dielectric materials affect both the RSB and RT branches......................................................... 67 Figure 4.19. The effect of different metals, dielectrics, and substrates on the tradeoff between RC and insulator thickness. .......................................................... 68 Figure 4.20. (a) MBE grown n-InGaAs substrate on InP. (b) RC tradeoff indicates the successful reduction in the InGaAs barrier height. .................................... 69 Figure 4.21. Schematic view of the fabricated InGaAs MOSFET ................................. 70 Figure 4.22. (a) Circular TLM data. (b) TLM measurement results show similar RC trends as from diodes. (c) RTOT vs. L plot from MOSFETs of different
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dimensions. (d) MOSCAP C-V from 2kHz to 1MHz ................................ 71 Figure 4.23. SiN MIS contact implemented on a surface channel enhancement mode InGaAs nMOSFET with L=10 m. (a) ID-VG. (b) ID-VD ....................... 72 Figure 5.1. Figure 5.2. Figure 5.3. Figure 5.4. Figure 5.5. Experimentally measured Schottky barrier heights on n-GaAs for different metal work functions. ................................................................................. 75 Distribution of the metal induced gap states. ............................................. 77 (a) Illustration of the relation between S and . (b) The slopes show that a smaller S leads to a higher degree of pinning of EF to ECNL. .................. 78 Illustration of the interface specific region. ............................................... 79 Schematic band diagrams: (a) Schottky barrier with a pinned Fermi level, (b) Fermi level umpinning through MIGS reduction, (c) Fermi level shifting through dipole formation at the interface ...................................... 80 Figure 5.6. Figure 5.7. Figure 5.8. Figure 5.9. No reduction in p-InGaAs B,eff, suggesting the Fermi level is shifted towards the conduction band, rather than depinned. .................................. 82 The roughly parallel shift in B,eff independent of M confirms the dielectric dipole induced shift of roughly 0.4 to 0.5eV. ............................. 83 The RC vs. TiO2 thickness tradeoff plot for Al/TiO2/n-GaAs MIS contacts appears to be independent of the surface passivations. .............................. 84 After removing the positive fixed charge in Al/Al2O3/n-GaAs MIS (a) there is no longer a reduced barrier height and (b) the current decreases. 86 Figure 5.10. Al/Al2O3/n-GaAs RC vs. tINS comparing samples with ALD deposition temperatures of 250 and 300oC.................................................................. 87 Figure 5.11. (a) As deposited Pt/HfO2/InGaAs MOSCAP C-Vs for different oxide thicknesses. (b) After annealing in FGA at 300oC for 15 min, the MIS contact resistance increased greatly. ........................................................... 88 Figure 5.12. Schematic band diagrams illustrating how the presence of electronic dipoles and fixed charge can affect B,eff. ............................................... 89 Figure 6.1. (a) Schematic of the investigated bilayer dielectrics. (b) Illustration of how the high-/SiO2 dipoles affect the band alignments. (c) Extracted barrier heights for varying dielectric thicknesses show the Si Fermi level is tuned towards the conduction and valence bands.
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(d) ID-VD of FinFETs

comparing the effect of MIS and the control contacts. ............................ 94 Figure 6.2. (a) C-V of MOSCAPs with and without high- GeO2. (b) Survey of high- materials and their corresponding VFB shifts. (c) Illustration of the equalization of the oxygen areal density through oxygen transfer at the interface and dipole formation. ................................................................. 95 Figure 6.3. Figure 6.4. Figure 6.5. Figure 6.6. Figure 6.7. Figure 6.8. Figure 6.9. (a) VFB shift of NiSi/A12O3/HfO2/SiO2/Si MOSCAPs.. (b) VFB shift of NiSi/HfO2/Y2O3/SiO2/Si MOSCAP.. ....................................................... 96 MIS diode current of Al/TiO2/n-GaAs and bilyaer Al/Al2O3/TiO2/n-GaAs with a constant 13 TiO2 thicknes ............................................................ 99 Al/Al2O3/TiO2/n-GaAs MIS diode current with a constant 7 Al2O3 thickness and varying TiO2 thickness. ..................................................... 100 Diode current of Al/HfO2/TiO2/n-GaAs with a constant 13 TiO2 (30cy) thickness and varying HfO2 thickness. ................................................... 100 Diode current of Al/ZrO2/TiO2/n-GaAs with a constant 13 TiO2 (30cy) thickness and varying ZrO2 thickness. .................................................... 101 Comparison of the maximum current in Al/Al2O3/TiO2/n-GaAs, Al/HfO2/TiO2/n-GaAs and Al/ZrO2/TiO2/n-GaAs bilayer MISt. .......... 101 Schematic of RC vs. tINS illustrating the tradeoff. ................................. 102 holding on thickness constant and varying the other and vice versa........ 102 Figure 6.11. (a) RC vs. tINS for MIS contacts using TiO2, Al2O3, and TiO2 + Al2O3. (b) MIS contacts with TiO2, HfO2, and TiO2 + HfO2 dielectrics show the same trends as TiO2 + Al2O3................................................................... 103 Figure 6.12. RC vs. tINS for MIS contacts using TiO2 + HfO2, TiO2 + ZrO2, and TiO2 + Al2O3 bilayer dielectrics.These bilayer MIS contacts result in lower Rc than their single dielectric MIS contact counterparts ............................... 104 Figure 6.13. Summary of minimum RC of single and bilayer MIS. ............................ 105 Figure 6.14. Summary of the effective barrier height of single and bilayer MIS. ........ 105 Figure 6.15. Summary of minimum RC of single and bilayer MIS. ............................ 106 Figure 6.16. Comparison of gate leakage of Pt/TiO2/Ge MOSCAPs with and without an Al2O3 interlayer.. ..................................................................................... 107
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Figure 6.10. Optimization of the TiO2 and Al2O3 thicknesses for minimum RC by

Figure 6.17. Bilayer MIS diode current measured immediately, 3 days, 6 days, and 9 days after fabrication, .............................................................................. 108 Figure 6.18. (a) Current device structure. (b) Device structure needed to prevent TiO2 degradation over time. .............................................................................. 109 Figure 6.19. (a) Schematic of net dipole build up due to screening ability differences at the interface. (b) Illustration of how the dipole magnitude changes with the electronegativity of the dopant atom. ....................................................... 110 Figure 6.20. Effect of RTA annealing on the contact resistance of Al/dielectric/n-GaAs single dielectric and bilayer MIS.............................................................. 113 Figure 6.21. Schematic of the transfer of oxygen from the higher to lower material, leaving behind a positively charged oxygen vacancy and adding a negatively charged ion on the other side to form the dipole. ................... 114 Figure 6.22. Summary of the conduction band offsets and calculated ratios taken relative to TiO2 for the investigated dielectrics. ...................................... 115

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Chapter 1 Introduction
1.1 Motivation
The silicon Metal Oxide Semiconductor Field Effect Transistor (MOSFET) has been the most important building block of Integrated Circuits (ICs) since its invention in the 1960s. It is used as elemental units to build both switches for digital logic and amplifiers for analog applications. To continuously improve the performance and complexity of ICs, the semiconductor industry has been faithfully following Moores Law [1], which states that the number of transistors doubles every two years (Figure 1.1a). As a result, although the basic device structure and functionality has remained the same, the physical dimensions have been continuously shrinking for the last 40 years. This MOSFET scaling has not only technological benefits, but also economical benefits of reducing cost per transistor through increased device density. However, Dennards idea of classical scaling [2] through simple physical scaling of dimensions ended after the 130 nm technology node as increasing leakage currents were causing an unacceptable exponential increase in the off-state static power consumption (Figure 1.1b). With the on-current scaling linearly at a much slower rate than the off-state current, significant changes were required to enhance the on-current and minimize off-current. As a result, tremendous research and developments efforts were put forth to maintain the desired technological advancements. New materials and device structures were introduced to boost the performance and to make up for the loss of classical and
1

(a)
101

(b)

Micron

100

10-1

10-2

Figure 1.1. (a) Illustr ration of Moo ores Law wh here the num mber of transi istors doubles s every two years and th dimension scale to im o he ns mprove perform mance and re educe the cost t per transi istor. (Adapte from Intel) (b) The off-state leakage or power is exponentially ed y increasing as we scale and is approa g aching the act power. (A tive Adapted from Intel)

gate oxide scaling (Figur 1.2). Strai re ined silicon was introdu uced in the 9 nm techno 90 ology node to enhan the carri mobilitie high-k/m nce ier es, metal gate in the 45 nm n node to mini imize th gate leak he kage, and FinFETs in th 22 nm no to reduc the short channel ef he ode ce t ffects. However, as silicon begi to reach its fundame H ins ental limits, even greater hurdles ne to r eed be overcome where the u of more n use novel materi and device structure may be ne ials es eeded to continue CMOS scaling. High mobility ch o C hannel mate erials such a Ge and III-V as co ompounds offer a potent solution to meet the power and p o tial performance specificatio of e ons fu uture CMOS nodes [3]. In this the S . esis, we focu on III-V semiconduc us ctor FET de evices ta argeted for beyond 15 nm digital log applicatio b m gic ons. III-V semiconductors are com mpounds com mposed of gr roup III elem ments (In, Ga Al, a, et and grou V elemen (As, Sb, N, P, etc.) that in gene have sig tc.) up nts eral gnificantly h higher el lectron and hole mobilities than silicon. Hig gher mobilit ties and injection velocities id deally translate to better MOSFET performance where the mobilitie can be fu r e, ese es urther en nhanced thr rough physic cally strainin the mate ng erials. The e excellent tran nsport prope erties co oupled with smaller ban gaps give III-V semi nd e iconductors the advanta of high s age speed
2

and low power operation. However, for III-V FETs to become a viable technology there

Manufacturing
LG= 35 nm 30 nm 20 nm

Development
10 nm

Research
5 nm Nanowire

Strained Silicon

Metal Gate

High-k
Si Substrate

Carbon Nanotube FET

FinFET HK/MG

Source: Intel

Beyond Si CMOS

Figure 1.2. TEM images of MOSFET scaling over the years with technological advances labeled. (Adapted from Intel)

are several challenges that need to be overcome. These include (1) finding an optimal, reliable high-k gate dielectric, (2) a cost effective integration of III-V materials on Si, and (3) a scalable low resistance ohmic contact. Ohmic contact formation on III-V semiconductors is fairly difficult because there is strong metal/III-V Fermi level pinning that results in high Schottky barrier heights. In materials with large bandgaps such as GaAs (1.42eV), the pinned barrier can be fairly large, ranging from 0.7 to 1.0eV [4]. Without the silicidation technology available to Si, III-V materials traditionally rely on multi-layered alloyed structures to form ohmic contacts, such as Au/Ge/Ni in the case of GaAs [5]. However, these source/drain (S/D) contact materials can then diffuse up to hundreds of nanometers during alloying which severely limits the scalability of III-V logic technology [6]. Recently there have been many demonstrations of III-V FET/HEMTs with excellent performance [7-13], but most of these demonstrations are on devices with micron scale S/D spacings despite nanometer scale gate lengths (Figure 1.3). To reduce the device footprint in line with the expected device density improvement, it becomes necessary to develop scalable non-alloyed contacts.
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Figure 1.3. Illustration of a device with a 50nm gate length but a device pitch of more than 2m. Figure from Ref#[14].

Another issue with large gate to S/D spacing is the increase in the series resistance and therefore the delay, which counteracts the benefit of the excellent III-V transport properties. Figure 1.4 illustrates the effect of reducing the large spacing through scaling the LSD and Lgap parameters in a HEMT structure. By reducing the gate to S/D spacings the device performance can in fact be restored. Therefore, to improve the III-V FET performance, we need a method to form contacts so LSD and Lgap can be scaled accordingly. This provides the motivation to develop a non-alloyed contact structure that is compatible with III-V semiconductors.

(a)
source

Lsd Lgap
n+ cap i-InP i-In0.52Al0.48As i-InGaAs QW channel i-In0.52Al0.48As on InP substrate gate

Lsd
drain

(b)
Delay [ps] Delay [psec]

2 0nm 1 20nm 80nm

Lgap=10nm Lgap=20nm Lgap=80nm

Series resistance reduction

0 10 100 1000

Lsd [nm] Lsd [nm]

Figure 1.4. (a) Schematic illustration of LSD and Lgap gate to S/D spacings in a HEMT (b) The delay decreases as LSD and Lgap are scaled to reduce the series resistance. Figure from Ref#[6].

1.2 Thesis Outline

This thesis focuses on nanoscale III-V transistors device technology for digital logic applications. More specifically, the MOS gate dielectric and S/D ohmic contact formation are investigated in detail, followed with implementation of the optimal conditions on a III-V MOSFET. This thesis is organized into seven chapters. Chapter 2 starts by looking into the material properties of III-V compound semiconductors and material characterization of various ALD dielectrics through stoichiometry, density, and band alignment measurements. Chapter 3 builds upon the as-deposited ALD Al2O3 gate dielectric and investigates the effect of forming gas and inert gas annealing on MOSCAPs and MOSFETs. The focus is then switched to S/D ohmic contact formation in Chapter 4. A novel metal-insulator-semiconductor (MIS) contact structure is introduced to reduce the effective barrier height and the effect of different metal, dielectric, and semiconductor materials is studied in detail. Chapter 5 looks into the underlying physical mechanisms behind the observed electrical behavior by starting with different Femi-level pinning theories and seeing how the theories could explain the experimental results from Chapter 4. Chapter 6 investigates the effect of combining different dielectric layers into a bilayer dielectric MIS contact. Finally, Chapter 7 summarizes the main contributions of this thesis along with recommendation for possible future areas of investigation.

Chapter 2 Materials Characterization

In this second chapter we look at the materials, surface passivation treatments, and device structures of III-V FETs. Atomic layer deposition (ALD) of dielectric materials for use in both the gate stack and source/drain contacts are discussed in terms of deposition method and recipe development. The ALD dielectrics are then characterized through atomic stoichiometry, density, and band alignment measurements.

2.1 III-V Compound Semiconductors

III-V compound semiconductors are composed of group III (Ga, In, Al ) and group V (As, Sb, P) elements, and span a wide range of binary (GaAs, InAs, GaSb, InSb), ternary (InGaAs, InGaSb), and even quaternary alloys (InAlGaP). These III-V compounds have much lower effective masses and therefore higher electron and hole mobilities than silicon, as shown in Table 2.1.
Si e (cm2/Vs) p (cm2/Vs) Eg (eV) 400 160 1.12 Strained Si 1,000 240 1.12 Ge 3,900 1,800 0.66 GaAs 8,500 400 1.42 In0.53Ga0.47As 8,000 300 0.72 InAs 20,000 500 0.36 GaSb 3,000 1,000 0.73 InSb 77,000 850 0.17 InP 5,400 200 1.35

Table 2.1. Summary of electron mobility (e) , hole mobility (p), and band gap (Eg) of several III-V compound semiconductors. Values are from Ref# [15].

However, these high mobility materials also have many fundamental drawbacks of lower density of states, smaller bandgap, and larger dielectric constants than silicon, with universal trends [16] observed between effective mass vs. bandgap (Figure 2.1a) and dielectric constant vs. bandgap (Figure 2.1b). This results in tradeoffs in the optimal material for digital logic applications. Despite having a high mobility valley, a low density of states means in FET operation carriers can begin to occupy other lower mobility valleys, leading to an overall lower effective mobility [17, 18]. This issue can be worsened by quantum confinement, but could be mitigated through strain engineering.

(a)
Effective Mass

0.5 0.4
C AlN

0.3 0.2 0.1 0

Si

SiC GaN

AlSb Ge InP AlAs CNT GaAs GaSb InAs InSb

4 Bandgap (eV)

(b)
Dielectric Constant

20
InSb

15 10 5 0

Ge InAs GaAs InP Si GaP SiC CdTe AlAs ZnTe

GaN ZnSe C AlN

4 Bandgap (eV)

Figure 2.1. Universal trend observed in semiconductors between (a) effective mass and bandgap, (b) dielectric constant and bandgap. Figure from Ref# [4, 16].
7

Also, the smaller bandgap of high mobility materials combined with larger electric fields as we scale can result in increased band-to-band tunneling leakage currents, potentially limiting the scalability of these III-V compound semiconductors [18]. Finally, the larger dielectric constant of these materials can lead to larger short channel effects, but can be resolved through changes in the device structure. The tradeoff between mobility and bandgap is illustrated through the high mobility but extremely small bandgap of InAs, and the reverse is true for GaAs which has a larger bandgap but lower mobility. As a result, InxGa1-xAs is often chosen for its intermediate material properties, and in particular In0.53Ga0.47As is commonly used because it is lattice matched to InP substrates and can be easily grown by MBE. GaAs and In0.53Ga0.47As are the two III-V materials used extensively in this thesis.

2.1.1 GaAs and InGaAs for III-V FETs

For the application of high performance digital logic, both the arsenides (GaAs, InAs, InGaAs) and antimonides (GaSb, InSb, InGaSb) have been experimentally and theoretically studied by many research groups. III-V FETs have been implemented in a multitude of different schemes that can be categorized in four main schematics [19] as shown in Figure 2.: (a) a MOSFET resembling standard silicon design [20, 21], (b) a quantum well FET (QWFET) with recessed gate [7, 9, 13], (c) a QWFET with virtual extensions [22], and (d) a QWFET with regrown extensions [23]. Since III-V FETs for CMOS is not yet a mature technology, there is still no agreement or a clear solution as to what the best integration scheme is. The strengths and weaknesses of these technologies are described very well in the reference [19]. Our research is based on a surface channel III-V MOSFET structure (Figure 2.2a) that closely resembles that of Si CMOS, following the reported GaAs [20, 24, 25] and InGaAs [11, 21, 26] MOSFETs. The key advantages include the simplicity, highly scalable nature, and similarities to silicon MOSFET fabrication. However, the disadvantages include mobility degradation from dielectric/interface scattering, the need for ion implantation and activation of source/drain dopants, and the integration of a high
8

quality gate dielectric with low interface trap density. We are not saying our chosen schematic is the optimal solution, but instead, the focus of our work is to demonstrate progress in one of the device strategies being pursued.

(a)

(b)

(c)

(d)

Figure 2.2. Schematic illustration of III-V FETs device structures. (a) MOSFET resembling silicon design, (b) QWFET with recessed gate, (c) QWFET with virtual extensions, (d) QWFET with regrown extensions. Figure from Ref#[19].

2.1.2 Surface Passivation

For the GaAs and InGaAs surface channel MOSFET structure chosen in our work, the gate dielectric to semiconductor interface is critical in determining the MOSFET performance. A high interface trap density (DIT) can make it difficult to reach MOSFET inversion and also degrades the channel mobility through scattering. Current III-V MOSFET performance is often limited by high DIT [19]. Unlike silicon, whose native oxide SiO2 forms a low DIT interface, the GaAs native oxide forms a high surface state interface that causes strong Fermi-level pinning [5], and so great care needs to be taken in minimizing the formation of native oxide during gate stack and source/drain contact fabrication. The effect of different surface cleans on GaAs were studied by Chen et al. [27, 28], with the results summarized in Figure 2.3. Using just HCl will remove the native oxide, as shown through the absence of Ga-O and As-O peaks, but elemental As-As peaks remain and the surface would begin to oxidize at high temperatures. On the other hand, native oxide removal using dilute HCl followed by sulfur passivation in ammonia sulfide (NH4)2S will remove the majority of the elemental As and terminate the surface with Ga-S and As-S bonding. The sulfur
9

termination prevents the surface from oxidizing and is found to be stable for up to 30 minutes in air [28]. Since the gate dielectric is typically deposited at elevated temperatures, the surface passivation also needs to be stable up to 300-400oC. The sulfur bonding was verified to be stable and prevented oxidation even after vacuum annealing at 400oC for 15 minutes. At 400oC there is the added benefit of As desorption, as observed by the removal of both As-S and As-As peaks. Details of the exact chemical cleaning and passivation procedure for GaAs and InGaAs substrates used in this thesis are provided in the Appendix.

Ga 3d HCl

h=120eV Ga 3d HCl+(NH4)2S Ga-As Bulk Ga-As Bulk

h=120eV Ga 3d HCl+(NH4)2S o +400 C Anneal Ga-As Bulk

h=120eV

No Ga-O
Ga-SX GaX-S Ga-SX GaX-S

Intensity (a.u.)

90

As 3d HCl

91

92

93

94

h=120eV As 3d HCl+(NH4)2S Ga-As Bulk

95

93

94

95

96

97

Elemental As

h=120eV As 3d HCl+(NH4)2S o +400 C Anneal

98

94

95

96

97

98

99

h=120eV Ga-As Bulk

No As-O

Ga-As Bulk

Elemental As Elemental As As-S

68

69

70

71

72

73

71

Kinetic Energy (eV)

72

73

74

75

76

72

73

74

75

76

77

Figure 2.3. Deconvoluted SRPES Ga 3d and As 3d spectra of the GaAs surface after a surface clean and passivation with (a) HCl, (b) HCl + (NH4)2S, and (c) HCl + (NH4)2S + 400 C 15 min in situ vacuum anneal. Figure from Ref#[28].

10

2.2 ALD Dielectrics

As CMOS devices scale down and gate dielectrics become thinner, it becomes necessary to control the film thickness and surface roughness at the atomic level. Atomic layer deposition (ALD) serves as a solution for depositing high quality ultrathin oxides, a single atomic layer at a time by self-terminating surface reactions.

2.2.1 Operation Principle

ALD is a self-limiting vapor-phase thin film deposition method based on the spatial separation of precursors [29]. The layer by layer process provides ALD films with the benefit of great film thickness control, large area thickness uniformity, and excellent repeatability. The films are also atomically flat and smooth and can conformally coat high aspect ratio patterns. A single cycle consists of: (1) exposure to the first precursor, (2) purge period, (3) exposure to the second precursor, and (4) purge period. For metal oxide depositions, the sequence between the metal and oxidant precursors depends on their reactivity with the substrate. In the case of Al2O3 on III-V using trimethylaluminum (TMA) and water as the precursors, TMA would be the starting precursor. In the first step, TMA is introduced into the reactor (Figure 2.4a) and adsorbed on the substrate or reacts with the surface functional groups (Figure 2.4b). Since the TMA precursor does not react with itself, the process is self-limiting and stops with one layer (Figure 2.c). Ideally there would be a perfect monolayer coverage of the substrate surface, but in reality the coverage is slightly less. In the subsequent purge step, the reaction chamber is purged with an inert gas to remove the unreacted precursors and the gaseous reaction by products. During the second pulse (Figure 2.4d), the water vapor oxidant precursor is introduced and reacts with the new functional groups formed in the previous pulse (Figure 2.4e). After the reaction is completed, the excess precursors are then purged from the chamber so the excess reactants do not contribute to additional film growth (Figure 2.4f).

11

(a) Introduction of TMA

Trimethyl aluminum Al(CH3)3(g) Methylgroup (CH3)

(b) TMA reaction with surface

Methanereaction productCH4 Reactionof TMAwithOH

(c) Self-limiting TMA

ExcessTMA Methanereaction productCH4

(d) Introduction of H2O

H2O

(e) H2O Reaction

Methanereactionproduct Newhydroxylgroup Oxygenbridges

(f) Single Atomic Layer of Al2O3

Figure 2.4. ALD Al2O3 using TMA and H2O precursors. (a) TMA as the first pulse, (b) Reaction of TMA with the surface, (c) TMA reaction is self-limiting, (d) After purging excess TMA, H2O is introduced as the second pulse, (e) Reaction of H2O, (f) Single atomic layer of Al2O3 remains after purging out excess H2O. Figures are from Ref# [29].

12

2.2.2 Process Development

To develop a new ALD dielectric process you need to: (1) Check the film is uniform and (2) Ensure the deposition rate is linear. It is good to start by using very long pulse and purge times to ensure the substrate surfaces are saturated with the precursors and that the chamber is completely purged after each reaction. The initial test for the film is uniformity across an entire wafer (Figure 2.5). Make sure the wafer is loaded in a specific orientation so the directions the precursors come from are known. If the film is non-uniform, it means the pulse and purge time are not sufficiently long. If the film is measured to be uniform, then the cycle time can be minimized by slowly reducing the pulse and purge times one by one until the film becomes non-uniform and the deposition rate starts to drop. At this point, the pulse and purge times should be increased back to where the film was last uniform. The exact pulse and purge times of different chambers can vary a lot depending on the chamber setup and dimensions, so typically following a particular recipe reported in literature is not very helpful. In general, larger chambers tend to require longer times, but the setup is also a factor. For example, ALD chambers where the precursors are inject from the side versus the center will require longer pulse times.

PurgingN2

65.1 65.0

H2O

64.9

64.9

65.1

65.4

65.4

avg =65.1A stdev =0.19A stdev /avg =0.3% GR=1.02A/cycle

TMA
65.2

65.0

Figure 2.5. Thickness (in ) measured across a 4 wafer after 65 cyles of ALD.

13

After uniformity is achieved the linear d, rity of the deposition r rate needs t be to ch hecked to ve erify true ato omic layer de eposition. In the case of short purge times, if the first n f e pr recursor is not complete purged o and the s n ely out second precu ursor is intro oduced, then with n th two precu he ursors presen in the cha nt amber at the same time t depositio would bec the on come ch hemical vap depositio (CVD) rat por on ther than AL Figure 2 illustrate the examp of LD. 2.6 es ple a linear grow rate of 0. wth .93/cy for ALD Al2O3 deposited a 250oC. Fro the meas at om sured hicknesses, there is sometimes an of t ffset of 10-2 20 either du to the for ue rmation of n native th ox xide or an er in the m rror measurement This can d t. depend on th materials system, but often he ti imes it is just due to the inaccurate d dielectric mo odels used, so the offset c be subtr o can racted to estimate th actual film thickness. o he m An el llipsometer such as W Woollam in the SNF ca be used to measure the an e th hickness thro ough change in the po es olarization of light as it reflects or transmits fr rom a material [30]. The polariz m . zation chang is represen as an am ge nted mplitude rat and a p tio phase difference , where the measured response d e depends on the optical properties and s th hickness of the material. There are s t . several diffe erent models for interpre s eting the a and data. For thin films below 10nm, it is better to en a refracti index an to calculat the n w s nter ive nd te th hickness bec cause in suc thin films the refract ch s tive index d does not affe the thick fect kness ca alculation as much. For thicker film it is bett to calculate both the refractive i s r ms, ter e index an thickness since ALD films tend t have lowe refractive i nd s to er index values s.
35 30 MeasuredTh hickness ModifiedThickness y=0.928x+12.222 R=0.997

Thickness()

25 20 15 10 5 0 0 5 10 15

y=0.928 8x+0.022 R=0 0.997

20

25

NumberofCy ycles Figure 2.6. ALD A 2O3 thicknes vs. number of cycles. e Al ss r

14

2.2.3 Tem 2 mperature Depend e dence

The growth rate p ALD cyc typically varies with the deposit g per cle y h tion tempera ature. The T change with temper w rature also d depends not only on the material its e self, but also the ch hosen precu ursor because the effect depends on the number of reaction sites present on e r n th surface [3 At highe temperatu he 31]. er ures, precurso can begi to decomp ors in pose and ma not ay ad dsorb well on the subst o trate sturfac which w ce, would decrea the growt rate. It is also ae th s possible thou that at h ugh higher tempe eratures som energy ba me arriers may b overcome and be e llow reaction that do not occur at l ns lower tempe eratures. At l low tempera atures, precu ursors al

(a) (
Thickness()

50 40 30 20 10 0 0

HfO2(150C) HfO2(250C)

y=1.228x+0.6 673 R=0.999

y=0.679x+0.231 1 R=0.998

10

20

30

40

50 0

NumberofCycles

(b b)
Thickness()

50 40 30 20 10 0 0

ZrO2(20 00C) TiO2(20 00C) HfO2(250C)

y=0.859x+ +0.443 R=0.9 998 y=0.6 663x+0.560 R =0.999

y= =0.359x+0.40 04 R=0.996

20

40

60

80

00 10

NumberofCycles Figure 2.7. Thick e kness vs. AL cycles me LD easurements to calculate the ALD growth rate to see th effect of (a deposition temperature, and (b) mate h he a) erial.
15

adsorb better on the surface which would increase the growth rate, but with a lower thermal budget, the film tends to be less dense and may have more by products present in the film that act as defect sites. On the other hand, at lower tempreatures it is also possible to have a lower deposition rate if there is insufficient energy for the precursors to dissociate or react with the previous layer. To investigate how temperature affects the ALD growth rate in our experiments, thickness vs. ALD cycles are measured in Figure 2.7 for various materials between 150oC and 250oC, with the extracted growth rates summarized in Table 2.2Table 2. The HfO2 growth rate decreases rapidly with temperature, suggesting the precursors are not adsorbing to the surface or are beginning to decompose. For the investigted temperature range, the Al2O3 and TiO2 growth rates did not change much. 150oC 1.228 200 oC 1.01 0.997 0.359 0.859 250 oC 0.928 0.663 0.362

Al2O3 HfO2 TiO2 ZrO2

Table 2.2. Growth rate in /cycle for several ALD films at different deposition temperatures. The temperature dependence varies with the precursor chemistry.

2.3 Atomic Stoichiometry by XPS

X-ray Photoelectron Spectroscopy (XPS), also known as Electron Spectroscopy for Chemical Analysis (ESCA), utilizes the photoelectric effect to identify chemical species from the surface of a sample [32]. XPS spectra are obtained by irradiating the sample surface with an x-ray beam while simultaneously measuring the kinetic energy and number of electrons emitted from the top 0.5 to 7 nm of the sample. The exact penetration depth is governed by the electron escape depth and varies with material. From the measured kinetic energy of the emitted electrons and the known energy of the x-ray, the binding energy of electrons can be determined. The atomic concentration of a material can then be calculated by measuring the area of the characteristic core level
16

peaks and after accounting for differences in the relative sensitivity factors, a ratio can be taken to measure film stoichiometry. The stoichiometry of the ALD films was measured using the PHI-XPS in the SNL using a photon energy of 1486eV. To analyze our samples, we start with a surface scan over a wide range of energies between 0 and 600eV using a coarse 1eV step. This allows for a verification of the sample and to see what energy ranges are required for each elemental peak. As shown in Figure 2.8, the surface scan of HfO2 shows the expected Hf and O peaks, but also contains a carbon peak around 287eV. This C1s peak is critical for determining exact binding energies and quantifying chemical shifts. Chamber conditions or tool calibration can allow the measured binding energies to vary from tool to tool, so the C1s peak is typically used as a reference point. However, the C1s peak arises from undesirable carbon contamination on the sample surface and can affect the resulting atomic concentration values, so the sample is sputtered using Ar at low energies for 30 to 60sec until the C1s peak is minimized. The most gentle Ar etch available on the PHI-XPS has an energy of 500eV and area of 2x2um, expected to etch SiO2 at ~1nm/min. High
X 104

O1s

9 8

Counts / sec

6 5 4 3 2 1 0 600

Hf4p1

Hf4p3

C 1s

Hf4d3

Hf4d5

Surface Scan
500 400 300 200 100 0

Binding Energy (eV)

Figure 2.8.. Surface scan of as-deposited HfO2 showing the presence of carbon.
17

Hf5s

Hf5p

Hf4f

10

energy Ar sputtering should be avoided because re-sputtered species can be picked up in the XPS scans and affect the accuracy of future scans. The Ar etch also helps in removing any surface oxygen that may be present. After the surface carbon is removed, detailed scans of individual peaks are performed with more cycles and much finer 0.1eV energy steps (Figure 2.9).

(a)
10000

(b)
11000 O1s peak 531.87 eV

Hf4f peak

20.20 eV 18.47 eV

Counts / sec

8000 6000 4000 2000 0 25

Counts / sec
15

9000 7000 5000 3000

20

536

534

532

530

528

Binding Energy (eV)

Binding Energy (eV)

Figure 2.9. Detailed scans of the (a) Hf4f peak and (b) O1s peak in HfO2.

In evaluating the ALD films deposited by the Cambridge Nanotech Savannah tool in SNF, the films were mostly found to be non-stoichiometric, leaning on the oxygen rich side. Table 2.3 summarizes the measured atomic concentrations for the various films, with the ideal and measured film stoichiometries given as a ratio of the oxygen to metal atomic concentrations. In the case of Al2O3, instead of the ideal crystalline O to Al ratio of 1.5, the ratio was measured to be 1.82 with 35.4% Al2p and 64.6% O1s. However, these measured atomic concentrations are only valid for a given deposition temperature, since the film stoichiometry can change with temperature. Hemmen et al. [33] found the Al2O3 films had a higher H-content and were oxygen rich at lower deposition temperatures, which suggests that there is a significant amount of hydroxyl groups incorporated in the films at low temperatures due to insufficient thermal energy to dissociate the hydroxyl groups. Since H2O is used as the oxidant precursor in all the investigated films, excess hydroxyl groups in the films are a possibility.
18

Film HfO2 Al2O3 ZrO2 TiO2

Temp 250oC 250oC 200oC 250oC

% Metal Hf4f = 32.80% Al2p = 35.40% Zr3d = 36.80% Ti2p = 31.30%

% Oxygen O1s = 67.20% O1s = 64.60% O1s = 63.20% O1s = 68.70%

Ratio 2.05 1.82 1.72 2.19

Ideal Ratio 2.0 1.5 2.0 2.0

Table 2.3. Summary of measured atomic concentrations of various ALD films. The stoichiometry is given in terms of a ratio of the oxygen to metal atomic concentrations.

2.4 Density Measurements by XRR

To further characterize the physical structure of the ALD films, specular X-ray Reflectivity (XRR) was used to measure the film density. XRR is a non-destructive surface sensitive analytical technique used to characterize the density, thickness, and roughness of crystalline or amorphous single and multi-layer thin film structures [34]. This method measures the changes in intensity of the x-ray beam reflected from the sample as a function of angle (). X-ray scattering at very small diffraction angles allows for the accurate measurement of thicknesses between 5 and 400 nm. After the intensity vs. angle is measured, the reflectivity pattern of the expected structure is simulated and film thickness, interface roughness, and density are then used as fitting parameters. Surface and interface roughness can reduce the accuracy of XRR since it damps the intensity fringes, but fortunately ALD results in smooth surfaces. This measurement also does not work effectively if there is not a large difference in density between different layers, but this is also not an issue for our samples. To measure the density of our ALD Al2O3, HfO2, and TiO2 films, roughly 15nm was deposited on HF-dipped silicon substrates. The film density should not have a significant dependence on the substrate, so silicon wafers were used for simplicity. The XRR measurements were taken immediately after ALD deposition to minimize any

19

Measured Simulated

Intensity(arb.units)
0.1

2.1

4.1

6.1

8.1

2 (deg) Figure 2.10. XRR measured reflected intensity and simulated intensity for ALD Al2O3 deposited at 250oC.

Layer Si SiO2 AlOx

(g/cm3) 2.33 2.14 3.04

(g/cm3) 0.07 0.10

t(nm) inf 1.10 13.62

t (nm)

0.03

Roughness (nm) 0.00 0.30 0.47

Table 2.4. Summary of the fitted density (), thickness (t), and roughness for the Al2O3 / SiO2 / Si structure corresponding to the measurement shown in Figure 2.7.

surface contaminants or oxidization that could affect the measurements. Figure 2.10 shows the experimentally measured and simulated intensity vs. 2 for Al2O3, with the fitted parameters given in Table 2.4. The silicon wafer, silicon native oxide, and high- film are all included in the simulated structure. Despite a 30 sec native oxide etch in HF immediately prior to loading samples into the ALD, there was still roughly 1nm of SiO2 present in all the high- films on Si. Table 2.4 summarizes the measured density (), thickness (t), and roughness of the films, and provides a comparison with reported crystalline densities and thicknesses measured by ellipsometry. These films are all deposited at 250oC, and the properties are expected to change for different deposition temperatures. The thicknesses measured by
20

the two methods agree well and differ only by 1nm. Since film thickness is one of the fitting parameters for the simulated XRR data, agreement with the ellipsometer measured thickness provides some confidence in the density values. The HfO2 and TiO2 film densities measured by XRR were found to be close to the reported crystalline values, but the Al2O3 density was measured to be significantly lower than the bulk crystalline density. This lower density can be due to the low temperature ALD process, where the density may increase with higher deposition temperatures. The effect of the temperature on density can vary from material to material, depending on the adsorption, dissociation, and reaction of the precursors.

AlOx HfOx TiOx

ALD Ellipsometer Crystalline cycles thickness(nm) (g/cm3) 140 200 380 14.5 15.7 16.3 3.9 9.8 4.2

(g/cm3)

t(nm)

Roughness (nm) 0.47 0.52 0.85

3.040.10 13.620.03 9.840.37 4.020.16 14.280.03 16.030.21

Table 2.5 Summary of ALD cycles, measured thicknesses, density, and roughness.

2.5 Band Alignment by SRPES

To better understand the electrical behavior of devices, it is necessary to know the bandgap and band alignment between materials. In this case it is between the various high-k dielectrics and the GaAs or InGaAs substrate. Synchrotron Radiation Photoemission Spectroscopy (SRPES) was used to determine these band parameters. The SRPES experiments were performed at beamline 8-1 of the Stanford Synchrotron Radiation Lightsource (SSRL), which provides a tunable range of monochromatic photons up to 160eV. The use of the low energy synchrotron radiation results in increased surface sensitivity and allows measurement of the top 2-3 monolayers of the surface with great accuracy. The valence band (VB) offset between the dielectric/GaAs and dielectric/InGaAs were measured by determining the binding energy difference between the VB spectra of
21

the substrate and dielectric [35-37]. For more accurate measurements, the energy shift induced by the surface charging during photoemission must also be accounted for by aligning the VB spectra to a reference peak. In this case the Ga 3d core level peak was chosen as the reference. Using Al2O3/GaAs as an example, Figure 2.11a illustrates a measured valence band offset of EV = 3.2 eV. The Al2O3 band gap was extracted to be 6.4 eV from the Al 2p energy loss spectrum (Figure 2.11b) and the conduction band offset calculated to be EC = 1.8 eV. As with the stoichiometry and density, the measured Al2O3 bandgap is lower than the ideal crystalline value [38] of 8.7eV. Though this is less than the ideal value, it is comparable to those measured by other researchers [39] for similarly deposited ALD Al2O3. The measured band offsets of other dielectric/GaAs interfaces were measured in the same way, with values summarized through band diagrams in Figure 2.12.

(a)
Intensity (a.u)

VB GaAs VB Al2O3/GaAs

(b)
Intensity (a.u)

h = 120 eV Al2p

3.2eV
-2 0 2 4

6.4eV
70 75 80 85

Binding Energy (eV)

Binding Energy (eV)

Figure 2.11. (a) Aligned valence band spectra of Al2O3/GaAs and the GaAs substrate, illustrating a EV of 3.2eV. (b) Al2p energy loss spectrum showing the Al2O3 band gap to be 6.4eV.

22

(a)
1.8 eV
Al2O3 6.4eV EC =

(b)
0.5 eV
TiO2 3.5eV EC =

(c)
EC =

(d)
2.3 eV
EC =

2.2 eV
ZrO2 5.7eV

1.4 eV
EV =

1.4 eV 1.6 eV
EV =

HfO2 5.9eV

1.4 eV 2.2 eV
EV =

1.4 eV 2.1 eV
EV =

3.2 eV

Figure 2.12. Measured band gap and band offsets of (a) Al2O3, (b) TiO2, (c) HfO2, and (d) ZrO2 on GaAs. The band diagrams are all aligned to the GaAs (EG = 1.42eV) to better illustrate the differences between the dielectrics.

2.6 Summary
In this chapter we provided an overview of the III-V materials and ALD dielectrics that will be used throughout the rest of this thesis for the gate stack and source/drain contacts. The III-V native oxides cause severe Fermi level pinning so surface passivation treatments and special precaution to minimize oxygen exposure prior to ALD are critical. Understanding the ALD operation principle, recipe development, and temperature dependencies are also necessary to optimize the material properties. From the atomic concentration measurements by XPS, density calculation by XRR, and band alignment measurements by SRPES it is apparent that the dielectric properties can differ greatly from the ideal crystalline properties. As a result, knowledge of the actual material properties is important in understanding the electrical characteristics and will be helpful in the following chapters.

23

Chapter 3 MOS Gate Stack

In this chapter, we investigate the effect of forming gas annealing (FGA) on ntype and p-type In0.53Ga0.47As MOS capacitors with ALD Al2O3 high- dielectric. The asdeposited samples have a significant amount of fixed charge in the bulk of the gate dielectric and at the dielectric/semiconductor interface, but through FGA, we successfully: (1) reduce the amount of bulk and interface fixed charge in the Al2O3, and (2) improve the Al2O3/InGaAs interface. The effect of the annealing temperature (300 - 400oC) and ambient (N2 and forming gas (FG)) are investigated in detail. We find that there exists a tradeoff where higher annealing temperatures result in a lower DIT, but comes at the cost of higher gate leakage. Furthermore, by comparing the effect of annealing in inert N2 versus FG, we discover that hydrogen passivation of dangling bonds and border traps is responsible for reducing the DIT, while the thermal budget is responsible for minimizing the fixed charges. Finally, we study the benefit of FGA on InGaAs nMOSFET device performance and demonstrate that the on-current increases by 25% after annealing at 350oC for 30 min. A thorough understanding of the impact of FGA is crucial for threshold voltage tuning and improvement of the InGaAs MOSFET gate stack.

3.1 Introduction
High mobility III-V compound semiconductors are strong contenders for extending high performance CMOS logic beyond the limitations of silicon [40]. InGaAs surface channel MOSFETs have demonstrated high performance devices [11, 41, 42] with fairly good interfaces due to the self-cleaning benefit of ALD Al2O3 and HfO2
24

high- dielectrics on III-V semiconductors [43]. In III-V MOSFET fabrication, post deposition anneals (PDA) in O2 or N2 are often employed, but annealing in forming gas (FG) ambient is rarely used. Recently, there have been reports on the benefit of hydrogen annealing in passivating the defects in ALD Al2O3 and HfO2 on InGaAs [44-46]. Kim et al. [45] first reported that hydrogen anneals can greatly reduce the frequency dispersion of the accumulation capacitance in Pt/Al2O3/n-In0.53Ga0.47As MOS capacitors (MOSCAPs) and attributed the dispersion to border traps. These results were confirmed by Shin et al. [46] who used density functional theory to calculate the energy levels of Al and O dangling bonds that correspond with the observed fixed charges in the oxide, and further suggested that hydrogen from FGA can passivate these dangling bonds. Building upon these reported results, we find that instead of attributing all the benefits of FGA to hydrogen alone, both hydrogen passivation and the thermal budget together contribute to the improvement of the interfacial properties. In previous studies of the Al2O3/In0.53Ga0.47As interface, MOSCAPS with only one metal workfunction was investigated under a single annealing condition of FGA at 400oC without a control study in an inert ambient. Also, studies were limited to n-type MOS capacitors and no work has been done on the p-type InGaAs MOSCAPs that are used to fabricate InGaAs nMOSFETs. Furthermore, these MOSCAPs have only been electrically characterized through capacitance-voltage measurements and the impact of FGA on the leakage current has not been reported. For III-V MOSFETs, the gate leakage is an important performance metric for determining the ION/IOFF ratio, off-state power consumption, and scalability of the effective oxide thickness (EOT). In this work, we investigate the effect of FGA on n-type and p-type In0.53Ga0.47As MOS capacitors with Al2O3 high- dielectric across a wide range of metal workfunctions (M) from Al (M = 4.1 eV) to Pt (M = 5.65 eV). The as-deposited gate dielectric was found to contain a considerable amount of bulk and interface fixed charge which causes the MOSFET flat band voltage (VFB) to change significantly with dielectric thicknesses, leading to undesirable changes in the threshold voltage. We first demonstrate the benefit of FGA through an alignment of the VFB across MOSCAPs with different oxide thicknesses, which indicates the successful reduction of fixed charges in the Al2O3. This
25

was achieved for a range of metal workfunctions, so the effect was dependent on the gate metal used. We then investigate in more detail the effect and tradeoffs of the annealing temperature (300 - 400oC) and ambient (N2 and FG) on the capacitance-voltage (C-V), current-voltage (I-V), and interface trap density (DIT). Finally, we apply the optimized annealing conditions to InGaAs nMOSFETs to demonstrate the benefit of FGA at the transistor level.

3.2 III-V MOSCAP

3.2.1 Device Fabrication Process
We study both n-type and p-type MOS capacitors to better understand the effect of FGA on InGaAs pMOSFETs and nMOSFETs. The p-type MOSCAPs were fabricated on MBE grown 300nm thick p-In0.53Ga0.47As (Be doped 6x1015 cm-3) lattice matched to the p+-InP substrate and in-situ capped with 50nm of arsenic to prevent oxidation. The samples are organically degreased then loaded into the ALD chamber for As-decapping at 400oC for 5 min, followed by in-situ ALD Al2O3 deposition. The n-type MOSCAPs were fabricated on 40nm thick n-In0.53Ga0.47As (Si doped 1x1018cm-3) epitaxially grown on n+-InP substrates. The samples underwent an organics degrease and NH4OH pre-clean treatment immediately prior to loading into the ALD chamber. For both types of MOSCAPs, 50, 75, 100, and 125 cycles of ALD Al2O3 were deposited at 300oC using trimethylaluminum (TMA) and H2O precursors, with TMA being the starting pulse. The film thicknesses were measured to be 4.7nm, 7.0nm, 9.2nm, and 12.0 nm. Metal top electrodes were then e-beam evaporated through shadow masks, followed by the deposition of Ti/Pt backside ohmic contacts. Post metallization annealing at near atmospheric pressure was performed in a quartz tube furnace in FG (5%H2 + 95%N2) and N2 ambients. The samples were organically degreased in acetone, methanol, and isopropanol immediately prior to loading into the furnace at room temperature. FG (or N2) is first flown at 5L/min for 15 min to clear the gas lines and to ensure that there is no oxygen present in the quartz tube prior to annealing. The furnace is then baked at 100oC for 30 min to desorb any moisture and
26

oxygen from the samples and quartz tube that may be present from the opening/closing of the tube. Next, the FG (or N2) flow rate is reduced to 2L/min, and the samples are annealed at 300, 350, and 400oC for 30 min. After annealing, the furnace is cooled down to room temperature, and samples are not removed until the furnace is below 50oC. Annealing in FG and N2 were carried out in the same furnace following the exact experimental procedure.

3.2.2 Electrical Characterization

A. VFB Alignment and Reduction of Frequency Dispersion with FGA
Figure 3.1a shows the as-deposited C-V characteristics for Pt/Al2O3/n-InGaAs at

1MHz for different oxide thicknesses. The shift in VFB with Al2O3 thickness indicates the presence of fixed charge in the film. After a FGA at 400oC for 30min these charges were successfully minimized, as illustrated in Figure 3.1b by the alignment of the VFB. It is interesting to note that after FGA, the thinner 50cy Al2O3 samples had a negative shift in VFB, while the thicker 100cy samples had a positive shift in VFB. This confirms the presence of charge in both the bulk of the dielectric and at the oxide/semiconductor interface and indicates that the charge at the Al2O3/InGaAs interface is negatively charged, while the charge throughout the oxide is positively charged. This non-uniform distribution of fixed charge was also observed by Shin et al. [46] despite having MOS capacitors fabricated using different surface pre-clean treatments and ALD films. Through an in-situ XPS characterization during ALD, Shin et al. [46] discovered that the Al2O3 is oxygen rich near the interface and aluminum rich away from the interface, which offers a good explanation for the nature of the change in charge across the oxide. In the inset of Figure 3.1b, a direct comparison of measurements taken between before and after FGA shows a clear reduction in C-V stretch out, indicating a decrease in the DIT. This is achieved while maintaining a near-constant accumulation capacitance, so there is no interfacial oxide formed and no change in the dielectric constant. However, the sharper C-V transition comes at the cost of an increase in hysteresis from 120mV to 140mV and an increase in leakage current. Both observations will be discussed in detail
27

in the next section. In measuring C-V across a range of frequencies from 1kHz to 1MHz, there is a sharp contrast between before and after FGA measurements (Figure 3.2). After FGA there is a noticeable decrease in the frequency dependent VFB shift and frequency dispersion in the accumulation regime. The C-V dispersion in the inversion regime is also smaller after FGA, possibly due to the reduction of trap assisted inversion in the asdeposited sample. DIT measurements by conductance and high frequency low frequency (HF-LF) methods [47] confirm a decrease in the DIT from midgap to valence band, where after FGA, the as-deposited midgap DIT of 5.3x1012 was reduced to 1.6 x1012 cm-2eV-1. It is important to note that when the samples were annealed in a furnace that is kept at 400oC, the leakage current was a few orders higher. The difference can be that in opening the furnace and loading samples at the elevated temperature of 400oC, any impurities or oxygen will be incorporated into the sample. Also, the purging of the gas lines at room temperature, tube furnace baking at 100oC prior to sample loading, and cooling down to < 100oC prior to sample unloading all appear to be critical steps in maintaining cleanliness in the annealing process.
(a) As-Deposited
f = 1 MHz HYS= 120mV

1.0 0.9 0.8

(b) After FGA Annealing

t = 4.7 nm t = 6.7 nm t = 9.2 nm

Capacitance / Cmax

0.7 0.6 0.5 0.4 0.3 0.2 -3 -2 -1 0

HYS= 140mV

Before FGA

After FGA
2V

Ideal VFB
1 2 -3 -2 -1 0 1

2V

Voltage (V)

Figure 3.1. (a) C-V for Pt/Al2O3/n-InGaAs with 50, 70, and 100 cycles of ALD. The as deposited samples have an oxide thickness dependent VFB shift which indicates the presence of significant oxide charge. (b) After a FGA at 400oC for 30 min there is VFB alignment across all thicknesses. Inset: C-V for 100cy of Al2O3 showing a steeper C-V transition after FGA.
28

0.8 0.7

(a) As-Deposited
1 kHz

(b) FGA 400 C for 30 min

1 kHz

Capacitance ( A / cm )

1 MHz

0.6
380 mV

1 MHz 100 mV

0.5 0.4 0.3 0.2 -3

Pt/Al2O3/n-InGaAs Al2O3=9.2nm
-2 -1 0 1 2 -3 -2 -1 0 1 2 3

Voltage (V)

Figure 3.2. MOSCAP C-V of Pt/Al2O3/n-InGaAs across many frequencies from 1kHz to 1MHz. (a) As deposited, there is significant frequency dependent VFB shift. From the HF-LF method [32], we measured a midgap DIT of 5.3x1012 cm2

eV-1. (b) After FGA at 400oC for 30 min, the frequency dependent VFB shift is

greatly reduced from 380mV to 100mV, along with a factor of three reduction in the midgap DIT to1.6 x1012 cm-2eV-1 (Figure 3.6).

By investigating different metal gates, we find the alignment of VFB and reduction of frequency dispersion by FGA is not limited to MOSCAPs with hydrogen catalyst metals (Ni, Pd, and Pt), since these same effects were also observed in MOSCAPs with Al and Ti metal gates. To quantify the effect, VFB was extracted using several methods from the theoretical flat band capacitance, integration of the quasi-static C-V for surface potential, and second differentiation of the inverse capacitance, which all resulted in the same general trend. The VFB reported here was extracted from the 1MHz high frequency C-Vs (CHF) by taking the second derivative of (1/CHF)2 with respect to the gate voltage [32]. For the as-deposited 100cy case, VFB is fairly close to the ideal VFB = M- , indicating minimal Fermi level pinning (Figure 3.3).

29

1.0 Capacitance / Cmax 0.9 0.8 0.7 0.6 0.5 0.4 -3 -2

Ti ( M = 4.3 eV) Pt ( M = 5.65 eV) Al ( M = 4.1 eV)

f = 1 MHz

-1 0 1 Voltage (V)

Figure 3.3. As deposited MOSCAP C-Vs for different metal gates, with the metal work functions (M) indicated in the legend. The C-Vs are normalized to the maximum accumulation capacitance. For 100cy or 9.2nm Al2O3, the VFB is close to the ideal, suggesting minimal Fermi level pinning.

B. Effect of Post Metal Annealing Conditions on n-type InGaAs To better understand the effect of annealing temperature and ambient on the VFB and DIT, we look into the detailed electrical characterization of Pt/Al2O3/n-InGaAs MOSCAPs with varying oxide thicknesses (50, 75, 100, and 125cy of ALD Al2O3) after annealing in FG and N2 ambients at 300, 350, and 400oC for 30 min. Temperatures below 300oC were not investigated because it is the deposition temperature and at such low temperatures hydrogen diffusion would be significantly reduced. Temperatures above 400oC were also not investigated because arsenic out-diffusion or intermixing at the Al2O3/GaAs interface could deteriorate the interface properties [5]. Figure 3.4 shows the resulting C-V characteristics of the samples at 1MHz. Part A highlights the effect of fixed charge on the shift in VFB with oxide thickness, and parts B through F shows an alignment of the VFB after annealing. Its interesting to note that even the samples annealed in inert nitrogen ambient show a reduction in the VFB shift and an increase in the steepness of the C-V transition, which indicates that the previously observed benefits of FGA [44-46] cannot be attributed only to hydrogen passivation of dangling bonds. There are several other mechanisms that may contribute to the reduction

30

of fixed charge without requiring the presence of H2 or a reducing environment. Instead, these mechanisms are independent of the annealing environment and solely depend on the thermal effects of annealing. One possibility is that annealing the oxide between 300 to 400oC for 30 min may provide enough thermal energy to re-arrange the bonds to fill vacancies and dangling bonds throughout the film. The reduction of the C-V stretch out can be explained by re-arrangement of bonds at the high-/InGaAs interface. Another possibility is the presence of sufficient thermal energy to dissociate the O-H hydroxyl groups that are present as a by-product of TMA + H2O deposited Al2O3. The free hydrogen from the broken O-H group can be used to fill dangling bonds in a similar way as the hydrogen present in FGA. But under this scenario, the amount of hydrogen available would be limited by the number of O-H bonds in the film. In comparing the similarity between the C-V of N2 and FG annealed samples, it is clear that thermal energy plays an important role and the improvement might be due to a combination of the two effects discussed above. However, the effect of hydrogen cannot be neglected, and will be discussed further, in conjunction with leakage and DIT. The shifts in the C-V curves for both FG and N2 annealed samples are in the same direction, so the thermal effects appear to be responsible for the reduction in both the positive fixed charge throughout the oxide and the negative interfacial fixed charge. But despite the similarities, the samples annealed in N2 have significantly higher leakage current. Since the gate current is added or subtracted from the displacement current, the gate leakage can be seen in the C-V through an increase or decrease in the inversion and accumulation capacitance. The high leakage in the 50cy sample after annealing at 350oC in N2 can be inferred from the loss of capacitance at positive gate biases beyond 2V (Figure 3.4b). Annealing the same 50cy sample at 400oC in N2 ambient resulted in extremely high leakage current such that a proper C-V curve could not even be measured (Figure 3.4c).

31

1.2

Capacitance (F/cm )

(a) As-Deposited
t = 4.7nm t = 7.0 nm t = 9.2 nm t = 12 nm

1.0 0.8 0.6 0.4 0.2

-4 -3 -2
o

(b) 350 C in N2

(c) 400 C in N2

Increasing thickness
Voltage (V)
-1 0 1 2 3 -4 -3 -2
o

1.2

Voltage (V)

-1

-4

-3

-2
o

-1

Voltage (V)

Capacitance (F/cm )

(d) 300 C in FGA

1.0 0.8 0.6 0.4 0.2
-4 -3 -2 -1 0 1 2 3 -4

(e) 350 C in FGA

(f) 400 C in FGA

-3

-2

-1

-4

-3

-2

-1

Voltage (V)

Voltage (V)

Voltage (V)

Figure 3.4. Pt/Al2O3/n-InGaAs MOSCAP C-V measurements for 50, 75, 100, and 125 cycles of ALD Al2O3 before and after annealing for 30 min under various conditions. These samples correspond to thicknesses of 4.7, 7.0, 9.2, and 12 nm. (a) As deposited, there is a VFB shift with thickness that indicates the presence of significant oxide charge. (b) Post metallization annealing in N2 ambient at 350oC reduces the fixed charge, but also increases the leakage current as indicated by the loss in capacitance for the 50cy sample. (c) After a post metal anneal in N2 ambient at 400oC, leakage becomes so severe that the C-Vs on 50cy samples were no longer measureable. (d) Annealing in FG at 300oC aligns the VFB across all thicknesses. (e) FGA at 350oC appears similar to results at 300oC. (f) 400oC FGA created a hump in the depletion region of the 50cy C-V, and a small additional VFB shift over the 300 and 350oC annealing. This hump may be due to the formation of defective interfacial oxide between the Al2O3 and InGaAs that acts as interface traps with energies between the midgap and valence band

In Figure 3.5a, the I-V for 50cy of Al2O3 shows a significant increase in leakage current with higher annealing temperatures. Samples annealed at 400oC also have a noticeably lower breakdown voltage where the current begins to increase sharply around 1.5V. Comparing annealing ambients at a given temperature, the leakage current is a few orders higher for the N2 ambient, which supports the trend observed in the C-V
32

measurements. Figure 3.5b shows the leakage currents for 75cy of Al2O3, and in this case there is a very pronounced increase in only the nitrogen annealed samples. All other samples annealed in FG had leakage currents comparable to the as-deposited samples.
(a) 4.7 nm Al2O3 (b) 7.0 nm Al2O3
As-Deposited o 300 C in FGA o 350 C in FGA o 400 C in FGA o 350 C in N2 400 C in N2
o

10 1 10 0 10 -1 10 -2 10 -3 10 -4 1x10 -5 1x10 -6 10 -7 10 -8 10 -9 10 -10 10

Current (A/cm )

-3

-2

-1

2 -3 -2 Voltage (V)

-1

Figure 3.5. Current-Voltage leakage measurements of Pt/Al2O3/n-InGaAs MOSCAPs for all annealing conditions. (a) Within a given annealing ambient, the leakage of the 50cy sample s increased with annealing temperature. At a given temperature, annealing in N2 resulted in much higher leakage than in FG. (b) For the 75cy samples, FGA between 300 and 400oC did not significantly change the leakage from the as-deposited case, but annealing in N2 at the same temperatures resulted in up to six orders of magnitude higher leakage.

From the similarities in the leakage for the samples with 50 and 75cy of ALD, it seems the leakage mechanism is not very dependent upon the oxide thickness. This alludes to possible tunneling current through filament conduction [48, 49], similar to that observed in transitional metal oxide based resistive random access memories (RRAM). ALD Al2O3 has been used in literature for RRAM applications, and it seems possible that oxygen vacancies can be formed through the re-arrangement of bonds during thermal annealing. When a positive or negative bias is applied across the film, the oxygen vacancies would then drift according to the electric field to form a conductive path. Annealing in FG may be able to reduce the number of oxygen vacancies if hydrogen
33

terminates the dangling bonds by forming O-H and Al-H bonds. As a result, the N2 annealed samples would have more oxygen vacancies in the film so conductive filaments could be formed at much lower voltages than in the FGA samples. As for the increase in leakage with annealing temperature, this can be caused by densification of the film which results in a thinner tunnel barrier and thus higher current. The densification would be greater with higher temperature annealing, and the trend in Figure 3.5 supports this. Annealing can also cause a reduction in the band offset [50] if the oxide properties are changed or an interfacial layer is formed at the Al2O3/semiconductor interface. Although leakage along polycrystalline grain boundaries can be very large, it is unlikely that polycrystalline Al2O3 is formed because the crystallization temperature is closer to 850oC [51] and thin films have a lower probability of nucleation seeds so the thermal budget required to form crystalline grains is even higher than for thick films. However, despite the increase in leakage current, there is still the added benefit of an improved high-k to InGaAs interface with annealing temperature, and we quantify this through DIT, interface sheet charge (QIT), and fixed charge (QF) measurements. Figure 3.6 summarizes the midgap DIT extracted from the HF-LF method [32] for samples with 125cy of Al2O3. The HF-LF method compares the difference between 1MHz high frequency and quasi-static low frequency C-V curves. The assumption is that the interface traps cannot follow the ac probe frequency but can follow the dc gate voltage sweep, so the difference between the two measurements is related to the DIT. Interface and bulk fixed charge densities were calculated assuming a sheet charge at the interface and constant fixed charge density throughout the oxide. By plotting the product of VFB and oxide capacitance vs. oxide thickness and using a least squares fit allows the extraction of QIT from the intercept and QF from the slope of the best fit line. The results are summarized in Figure 3.6.

34

1 x10 13 1E+13

MidgapDIT , InterfaceCharge

9 x10 12 9E+12 8 x10 12 8E+12 7 x10 12 7E+12 6 x10 12 6E+12 5 x10 12 5E+12 4 x10 12 4E+12 3E+12 3 x10 12 2E+12 2 x10 12 1E+12 1 x10 12 0E+00

1019

1018

1017
o o o o o As AsDep 300 C350 C400 C350CC400 C 300C 350C 400C 350 400C N DepFGAFGAFGAN2 N22 FGA FGA FGA N2

Figure 3.6. The midgap DIT is plotted in green with values corresponding to the left y-axis. The absolute value of the interface sheet charge (QIT) is shown in red on the left y-axis, with the sign of the charge indicated by a + or - sign. In all cases, the QIT remains negatively charged. The fixed charge density (QF) is shown in blue, with values corresponding to the right y-axis. The as-deposited, 300oC FGA, and 350oC FGA samples all have positively charged QF, with the rest negatively charged. Each of the different post metallization annealing conditions resulted in DIT, QIT, and QF lower than the as-deposited case, with 400oC FGA resulting in the lowest values.

For samples annealed in FG, there was a progressive reduction in DIT with increasing annealing temperature, which can be explained by the greater dissociation and diffusion of hydrogen in Al2O3. The important factor is the total thermal budget, so we should be able to achieve the same effect at lower temperatures if we anneal for a longer period of time. The DIT measurements help quantify the benefit of the presence of hydrogen during the annealing process. Annealing in FG at 400oC for 30 min had the greatest improvement in the interface, where the as-deposited midgap DIT of 6.2x1012 cm2

eV-1 was reduced by more than an order of magnitude to 5.9 x1011 cm-2eV-1. Samples

annealed at the same temperature but in nitrogen ambient also saw a reduction in DIT, but it is a significantly smaller reduction by only a factor of two to 3.5x1012 cm-2eV-1. This difference where the N2 annealed samples have a small change in DIT despite a large change in VFB indicates that the underlying mechanism of the changes in fixed charge
35

FixedChargeDensity(cm3 )

MidgapDit(cm2eV1) MidgapDIT (cm2 eV1 ) Interface ChargeQIT (cm2 ) Qi/q FixedChargeDensityQF (cm3 ) QF/q

1020

and interface charge/traps are different. Since DIT measures the traps at the interface only, the significantly lower DIT in the FGA samples demonstrates that hydrogen is responsible for passivating the dangling bonds at the interface. However, since the reduction in the VFB shift is very similar for both ambients, it tells the reduction in the fixed charge in the film is mostly due to the previously explained thermal effects responsible for the rearrangement of bonds to effectively self-heal defects. In looking at QF and QIT, the as-deposited sample indeed has a negative charge at the interface and positive charge throughout the oxide, which is the reason behind the negative shift for the 50cy and positive shift for the 125cy samples after FGA (Figure 3.1). With higher temperature annealing in FG, both QIT and QF are significantly reduced from the as-deposited values. In all annealing conditions, the interface charge remains negative and FGA typically did not change the sign of the charge. However, annealing in N2 ambient converted the as-deposited positive fixed charge into a negative charge, highlighting the difference in the two ambients and the effect on the bulk material. C. Effect of Post Metal Annealing on p-type InGaAs We also studied the effect of annealing at 300oC and 350oC in FG and N2 on ptype InGaAs MOSCAPs because this understanding is critical in the application of n-type inversion MOSFETs. From the larger VFB shifts across thickness in the as-deposited CVs (Figure 3.7a), it appears that the interface and fixed charge have a much greater effect on p-InGaAs than n-InGaAs. This difference can be explained through evaluating the asdeposited QF and QIT. In both cases, roughly the same QF is expected since the amount of fixed charge in the film should be independent of the substrate doping. However, QIT is dependent upon the energy levels of the dangling bonds and defects and their occupancy would change with the Fermi level. The as-deposited QIT for n-InGaAs was measured to be -9.1 x 1012 cm-2 and -4.8 x 1012 cm-2 for p-InGaAs. The bulk fixed charge in the film is positively charged, so the negative interface fixed charge effectively cancels and reduces the overall total fixed charge. With a lower QIT, p-InGaAs MOSCAPs have a greater total fixed charge than n-InGaAs.

36

(a) As-Deposited

(b) 300 C in FGA

Capacitance (F/cm )

1.2 1.0 0.8 0.6 0.4 0.2

t = 4.7nm t = 7.0 nm t = 9.2 nm t = 12 nm

Increasing thickness

0.0 -6 -5 -4 -3 -2 -1

Voltage (V)
o

-3

-2

-1
o

Voltage (V)
(d) 350 C in N2

(c) 350 C in FGA

Capacitance (F/cm )

1.2 1.0 0.8 0.6 0.4 0.2 0.0 -3 -2 -1 0 Voltage (V) 1 2 -3 -2 -1 0 1 2

Voltage (V)

Figure 3.7. Pt/Al2O3/p-InGaAs MOSCAP 1MHz C-V measurements for 50, 75, 100, and 125 cycles of ALD Al2O3 after annealing for 30 min under various conditions. (a) The as deposited samples have an oxide thickness dependent VFB shift which indicates the presence of significant oxide charge. (b) Annealing in FG at 300oC reduces the oxide charges and aligns the VFB across all thicknesses. (c) FGA at 350oC appears similar to results at 300oC. (d) Post metallization annealing in N2 ambient at 350oC also reduces the fixed charge, but has a drop off in capacitance due to a large leakage current comparable with the capacitive displacement current. The 125 cycle sample has an extra shift towards the positive direction, and the reasoning behind this is still currently not understood. The sample was re-fabricated and annealed, but still yielded the same results.

37

As with the n-InGaAs MOSCAPs, annealing in FG significantly improved the dielectric to semiconductor interface and reduced the fixed charge so the VFB of the samples with different thickness were aligned (Figure 3.7b-d). From the 1MHz C-V curves there is no noticeable difference between the 300 and 350oC FGA samples, but the 350oC N2 annealed sample showed a drop in capacitance at high bias voltages. This capacitance roll-off is due to high gate leakage, where the leakage current becomes comparable to the capacitive displacement current. The gate leakage trends shown in Figure 3.8 also agree with those for the n-InGaAs MOSCAPs. The FGA samples had very similar I-V curves as the as-deposited samples for both 50cy and 75cy of Al2O3, but the N2 annealed samples had orders of magnitude higher current, pointing again to a filament conduction [48].
10 10 10 10
2 1 0

(a) 4.7 nm Al2O3

(b) 7.0 nm Al2O3

As-Deposited o 300 C in FGA o 350 C in FGA o 350 C in N2

-1 -2 -3 -4 -5 -6 -7 -8 -9

Current (A/cm )

10 10

1x10 1x10

10 10 10 10

10

-10

-3

-2

-1

2 -3 -2 Voltage (V)

-1

Figure 3.8. Current-Voltage (I-V) leakage measurements of Pt/Al2O3/p-InGaAs MOSCAPs for all annealing conditions. (a) For the 50cy ALD Al2O3 samples, annealing at 300 and 350oC in FG did not significantly change the leakage from the as-deposited case. However, annealing in N2 at 350oC resulted in several orders of magnitude higher leakage. (b) The 75cy samples had the same leakage trend, but with a smaller difference between the FG and N2 annealed samples.

38

The reduction in DIT from post metallization annealing summarized in Figure 3.9 is not as large as in the n-InGaAs MOSCAP case, but QF and QIT are still greatly reduced. This is expected as there was a much larger change in VFB for the p-InGaAs case. The DIT is lowered from the as-deposited 6.2 x1012 cm-2eV-1 to 2.1x1012 cm-2eV-1 in the best case of 350oC FGA. However, even though the DIT only changed by a factor of three, the calculated interface sheet charge was reduced by an order of magnitude and changed from negative to positive charge. The density of fixed charge throughout the Al2O3 is also greatly reduced by two orders of magnitude, so it appears the main cause of the large shifts in VFB in the as-deposited C-Vs is due to QF rather than QIT.

8 x10 12

MidgapDIT , InterfaceCharge

7 x10 12 6 x10 12 5 x10 12 4 x10 12 3 x10 12 2 x10 12 1 x10 12

10 19

10 18

As 300oC350oC 350oC AsDep 300CFGA 350CFGA 350CN2 DepFGAFGA N2

10 17

Figure 3.9. The midgap DIT is plotted in green with values corresponding to the left y-axis. The absolute value of the interface sheet charge (QIT) is shown in red on the left y-axis, with the sign of the charge indicated by a + or - sign. The as-deposited QIT is negative, but become positively charged after annealing. The fixed charge density (QF) is shown in blue, with values corresponding to the right y-axis. QF starts out positive in the as-deposited case, but become negative after annealing. Overall, annealing in FG resulted in DIT, QIT, and QF lower than the asdeposited case, with 350oC in FGA resulting in the lowest values.

39

FixedChargeDensity(cm3 )

MidgapDitm MidgapDIT (cm2 eV1 ) Qi/q Interface ChargeQIT (cm2 ) abs(Qf) FixedChargeDensityQF (cm3 )

10 20

2.4 III-V MOSFET

2.4.1 Device Fabrication Process
Finally, to see the effect of FGA at the transistor level, In0.53Ga0.47As nMOSFETs with a Ni/Al2O3/InGaAs gate stack were fabricated using a gate last process flow (Figure 3.10). The channel material was MBE grown p-type In0.53Ga0.47As (Be doping of 6x1015 cm-3) in-situ capped by 50nm of arsenic to prevent oxidation. Samples were first loaded into an ALD chamber and then the arsenic layer was decapped by annealing at 400oC for 5 min, followed by ALD of 30nm Al2O3 at 300oC using TMA and H2O precursors. The samples were then patterned and wet etched to define mesas for device isolation. Source/Drain regions were dual implanted with Si at 30keV and 80keV using a dose of 2x1012cm-2, then activated by RTA at 600oC for 30 sec in N2. Afterwards, the sacrificial implantation oxide was stripped off in 2% HF and the native oxide removed in NH4OH immediately prior to loading in the ALD chamber for 10nm Al2O3 gate oxide deposition. Next, a 75nm Ni gate electrode was formed using e-beam evaporated lift-off process. A 50nm Al2O3 field oxide was used for further device isolation and contact area definition. Finally, S/D contacts were patterned by lift-off of 150nm Al. The samples were measured, then the exact same devices were re-measured after atmospheric pressure annealing in FG (5%H2 + 95%N2) for 30 min at 350oC.

Isolation Oxide

G
pInGaAs (6x1015 cm3)

10nmAl2O3 GateOxide 300nm 200nm

pInGaAs (Bedoped1x1017 cm3) p+InP Substrate

Figure 3.10. Schematic diagram of the fabricated InGaAs MOSFET with 10 nm ALD Al2O3 gate oxide. Cross-hatched area represents the implanted regions.

40

2.4.2 Electrical Characterization

(a)
Drain Current ( ID ) [A/m]

50 40 30 20 10 0 0

L = 10 m VGS = 0 to 4 V VGS= 0.5 V

44 A/m 35 A/m

(b)

1 2 3 Drain Voltage ( VDS ) [ V ]

L = 10 m VDS = 1 to 4V

10 10 10

Drain Current ( ID ) [A/m]

10 10 10

-1

-2

-3

Before Annealing : VTH = 0.88 V After Annealing : VTH = 0.80 V

10 -1

-4

1 2 3 Gate Voltage ( VGS ) [ V ]

Figure 3.11. Transfer and output characteristics of a surface channel enhancement mode InGaAs nMOSFET with L=10 m and W = 320 m. The asdeposited I-V is indicated by the dotted lines, and the after FGA at 350oC is indicated by the solid lines. (a) After FGA, the ID-VDS characteristics show a 25% increase in the drive current. Contact and sheet resistances did not change much, so the current increase is believed to be due to the improved dielectric/channel interface. (b) On a log scale, the ID-VGS is the roughly the same before and after FGA, indicating the observed increase in current is not due to a change in the threshold voltage.

41

Transfer characteristics of the MOSFET in Figure 3.11 show an enhancement mode device with fairly good gate control and low gate leakage that is five orders of magnitude lower than the drain current at VGS = VDS = 4V. In comparing the before (dotted line) and after FGA (solid line), it is clear that there is a significant enhancement in drive current, where the peak current increases 27% from 35A/m to 44A/m. Part of this enhancement is due to a slight decrease in the threshold voltage (VTH) from 0.88V as deposited to 0.80V after FGA. However, even at the same overdrive (VGS-VTH) there is still a 24% increase in the drive current from annealing. This change is not due to a reduction in contact resistance because in fact the contact resistance increased slightly from 1.3x10-4 to 1.7x10-4 ohm-cm2 after annealing. The authors believe the enhanced MOSFET characteristics are due an improvement of the interface for better gate control, and possibly an improvement of the channel mobility from reduced interface scattering. For a 10nm Al2O3 gate oxide, the effect of the FGA on the increase gate leakage is minimal. The subthreshold slope before annealing is 147mV/dec, and after FGA is increased slightly to 151mV/dec. This reported subthreshold slope is fairly high because there is considerable leakage at the source/drain pn junction from the high energy implantation damage that has not been completely removed through the dopant activation anneal. The pn junction leakage could be reduced through the use of optimized lower implant energies combined with higher activation temperatures.

2.5 Summary
In summary, we have shown the benefit of FGA on n-type and p-type In0.53Ga0.47As MOSCAPs. After FGA, the bulk and interface fixed charges are minimized, allowing for a steeper transition in the C-V and a VFB that is roughly independent of the oxide thickness. This is beneficial for VTH tuning of FG annealed InGaAs MOSFETs. The effect of different annealing temperatures and ambients were thoroughly investigated through I-V, C-V, DIT, QF, and QIT electrical measurements. We discover that as we increase the annealing temperature, a tradeoff exists between lower DIT and higher gate leakage, where the optimal annealing temperature depends on the amount of gate leakage
42

that can be tolerated. Also, contrary to previous reports that attribute all annealing benefits to hydrogen passivation of dangling bonds and border traps, we conclude that some of the reduction in QF and QIT are due to thermal effects. However, FG is still the better annealing ambient since N2 annealing resulted in a substantial increase in the gate leakage. Finally, an In0.53Ga0.47As nMOSFET was fabricated, and FGA at 350oC for 30 min was demonstrated to improve the gate stack interface properties and to increase the on-current by 25%. We believe FGA is crucial for tuning the threshold voltage and improving the InGaAs MOSFET gate stack, and hope our study has advanced the understanding of the effect of post metallization annealing.

43

Chapter 4 Single Dielectric MIS Contacts

In this chapter we provide an overview of a novel contact technique to reduce the effective Schottky barrier height on III-V high mobility semiconductors. Single metals are used in combination with an ultrathin dielectric to tune the metal/semiconductor barrier height towards zero by shifting or suppressing the strong Fermi level pinning. Barrier height reduction in the metal-insulator-semiconductor (MIS) contact structure is deduced from increased diode current and reduced contact resistance. Current demonstrations of the single dielectric MIS contact have barriers as low as 0.18 eV for Al/Al2O3/n-GaAs. The dependence of the minimum achievable contact resistance and barrier height on the metal, dielectric material, dielectric thickness, and substrate doping are studied in detail. For III-V semiconductors, the MIS contact allows for the use of a non-alloyed contact that is crucial for the scalability of III-V MOSFETs.

4.1 Introduction
As we reach the end of the silicon technology roadmap, alternative materials such as high mobility Ge [52, 53] and III-V compounds [7, 13, 54] have proven to be strong contenders for extending high performance logic beyond the 22nm technology node. However, before these technologies can be implemented, a few of the existing problems must be solved. These include the gate dielectric to channel interface [55-58], integration on silicon [57], small device footprint in line with the device density improvement expected of each successive technology node [6], and low-resistance source/drain contacts [57], where the latter is related to the formation of Schottky barriers.
44

In the case of Ge metal oxide semiconductor field effect transistors (MOSFETs), high performing p-MOSFETs have already been demonstrated [59, 60], but Ge nMOSFETs still have much room for improvement. Ge n-MOSFET performance is currently limited by high interface trap density at the gate dielectric which causes inversion charge loss through trapping [52], and large source/drain parasitic resistance (RSD) which results in the measured extrinsic performance falling far behind the intrinsic performance. The high RSD is a combined result of low n-type dopant solubility and Fermi level pinning in the source/drain (S/D) regions. Strong Fermi level pinning at the metal/semiconductor interface is observed when metal work functions are varied from 2.8eV (Ce) to 5.6eV (Pt), but the Schottky barrier height was found to only vary from 0.49 to 0.64 eV [61], which is far from the near zero barrier needed for good ohmic contacts. Recent work on sulfur passivated Ni germanide contacts to n-Ge [62] have demonstrated barrier heights as low as 0.15eV, which is promising, but the currentvoltage characteristics remain rectifying. For III-V compound semiconductors, Fermi level pinning also results in high Schottky barrier heights, and in materials with large bandgaps such as GaAs (1.42eV), the pinned barrier can be fairly large, ranging from 0.7 to 1.0eV [4]. Without the silicidation technology available to Si and germanide technology for Ge, III-V materials typically rely on multi-layered alloyed structures, for example Au/Ge/Ni in the case of GaAs, to form ohmic contacts. These S/D contact materials can then diffuse up to hundreds of nanometers during alloying, so in order to prevent electrical shorting, most III-V FET/HEMTs demonstrated with promising performance have S/D spacings in the micron scale despite nanometer scale gate lengths. In recent work on non-alloyed contacts to HEMTs, Waldron et al. [9] had a 60nm contact-to-gate separation using W to contact In0.65Ga0.35As with a doping density of 2x1019cm-3. Singisetti et al. [63] achieved a 1.3-m2 low resistance using in-situ Mo on n-In0.53Ga0.47As with a doping of 8x1019cm-3. However, in both studies the contacts were made to very highly doped MBE-grown substrates with considerable tunneling current to facilitate the contact. A challenge remains in making a non-alloyed ohmic contact to

45

lower doped materials, which is a long-standing problem for III-V MOSFETs due to poor S/D dopant activation in ion implanted S/D. Higher temperature annealing is needed for greater dopant activation, but temperatures above 700oC also causes arsenic to desorb from the surface and induces negative charges and interface traps, degrading the InGaAs surface and therefore the mobility of III-V surface channel MOSFETs [64]. As CMOS scaling continues, S/D junction depths are increasingly shallower in order to control short channel effects. However, the shallow junction adversely results in a rapid increase in parasitic resistance, which could then degrade the overall device performance [65]. Metal S/D Schottky barrier transistors (SB-FET) offer a solution, but they require low barriers (<0.1eV) at the S/D for sufficient on-current. Until recent work by Connelly et al. [66] which showed reduction of the metal/Si Fermi level pinning through the use of an ultrathin Si3N4, the formation of large Schottky barrier heights had limited the implementation of Ge SB-FET and III-V SB-FET. In this chapter, we will discuss the use of thin dielectrics to alleviate metal/semiconductor Fermi level pinning of high mobility III-V materials. We then examine the contact design parameters involved to minimize the resulting effective barrier height and contact resistance for S/D contacts. The ability to reduce the III-V Schottky barrier also allows for the use of a non-alloyed S/D contact, which is critical in the scalability of III-V MOSFETs for the application of future generations.

4.2 Background
According to the Schottky-Mott theory [67], when a metal and semiconductor are brought into contact, the two Fermi levels align, so the semiconductor band bending and interface Fermi level are modified. The potential barrier B between the two should ideally be set by the metal work function M and semiconductor electron affinity e, where B = M e for an n-type semiconductor. However, in reality, this dependence is not experimentally observed. Schottky barrier heights tend to be pinned at a value roughly independent of the metal work function, as shown in Figure 4.1.

46

(a)

(b)

qM

qS
EC EF

qM,eff qB

qS
EC EF

EV

EV

Figure 4.1. (a) Band diagram of an ideal unpinned Schottky barrier. (b) Band diagram of a pinned Schottky barrier where the effective metal work function M,eff is modeled as differing from the work function in vacuum M.

Currently, there exist several theories for Fermi level pinning. The origin of the pinning states varies with the model. Two of the more popular ones are the metal induced gap states (MIGS) [68, 69] and bond polarization theories [70], which will be discussed in detail in the next chapter. In general, for the application of MOSFET S/D ohmic contacts, Fermi-level pinning is undesirable since it takes away the ability to use metal work functions to tune to the barrier height, but there are some cases where the pinning is beneficial. In Ge, the Fermi level pins close to the valence band so most metals form negative barriers to p-Ge, making ohmic contact formation extremely simple because there is no barrier for the majority carriers. Similarly, the InAs Fermi level pins within the conduction band, which simplifies the formation of ohmic contacts to n-InAs. However, simplifying ohmic contacts for p-type typically means complicating ohmic contacts for n-type, and vice versa, since the barrier height may now be even larger than the entire bandgap. Figure 4.2 summarizes the ECNL and typical n-type and p-type Schottky barrier heights for a range of semiconductors.

47

3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0

Si

Ge

GaAs InGaAs InAs InSb

InP

GaN
0.95eV

Band Alignment (eV)

Typical n-type B
0.7eV 0.6eV 0.8eV 0.2eV 0.06eV 0.4eV 0 eV 0.40.7eV0.33eV 0.5eV

EC ECNL

Typical p-type B

0.50.65eV

EV

Figure 4.2. Band information (EC, EV, ECNL) for high mobility semiconductor materials, with ECNL indicated by the dashed line. Numbers near EC represent typical pinned n-type Schottky barrier height B, and numbers near EV represent typical pinned p-type Schottky B.

For the application of high mobility MOSFET S/D contacts, we need a near zero barrier height for minimal contact resistance, so the strong metal/semiconductor Fermilevel pinning needs to be reduced. Connelly et al. [66] first claimed to depin the metal/Si Fermi level by inserting an ultrathin silicon nitride (Si3N4) in between the metal and Si to create a metal-insulator-semiconductor (MIS) contact. In accordance with the MIGS theory, the ultrathin insulator was cited to physically separate the two materials, allowing the metal electron wavefunction to be attenuated in the insulator prior to penetrating the semiconductor. The attenuated metal states result in fewer charges available to drive EF towards ECNL, as shown in Figure 4.3. After depinning the Fermi level, the metal work function M can then be used to tune the effective barrier height. For n-type ohmic contacts, metals with a low M near the semiconductor conduction band should result in a near zero barrier height. For p-type ohmic contacts, metals with a high M near the semiconductor valence band would be desirable.

48

(a)
B,eff
Penetrated Deep States EC EF

(b)
B,eff
Tunneling States Blocked Deep States

Metal

Semiconductor

EV

Metal Semiconductor Insulator

Figure 4.3. (a) Schematic band diagram of a pinned Fermi level. The metal and semiconductor are in direct contact, allowing the tail of the metal electron wavefunction to decay into the semiconductor bandgap, creating MIGS that pin the Fermi level. (b) Metal/semiconductor Fermi level depinning, where with an insulator, the metal wavefunction is attenuated in the gap states.

After the initial demonstration on Si, the MIS contact structure has been studied by several research groups on both n-type and p-type Ge using a variety of dielectrics ranging from Ge3N4 to AlOx [71-74]. The first Ge MIS contact was demonstrated by Lieten et al. [73] using a thin Ge3N4 layer to form an ohmic n-Ge contact and a rectifying p-Ge contact. Following the nitridation technique used by Connelly et al. [66] on Si, the authors exposed Ge(001) and Ge(111) to nitrogen plasma in UHV at temperatures between 550-600oC to form 0.7nm of amorphous and (poly)crystalline Ge3N4. Metal was deposited immediately following the nitridation to suppress oxide formation, and no post deposition annealing was performed. In contrast to the rectifying behavior of the control samples without Ge3N4, the current conduction through n-Ge samples with Ge3N4 was found to be ohmic for low work function metals Al (4.1eV), Cr (4.5eV), and Co (5.0eV). For higher work function metals Au (5.4eV) and Pt (5.6eV), the current remained rectifying. This difference is promising for MIS contacts because it indicates a sufficient reduction in the Fermi level pinning to allow barrier height tuning through metal work function. However, it should be noted that that the surface is not completely unpinned because B,eff M e. Table
49

4.1 summarizes the changes in the B,eff. Through this, Ge3N4 is shown to have a twofold benefit: (1) passivates the dangling bonds of Ge for a low trap density at the Ge3N4/Ge interface, and (2) has fewer surface states than Ge or effectively a larger pinning factor S.

Metal Al Cr Co Au Pt

Metal Work Function (eV) 4.17 4.50 5.00 5.38 5.64

Barrier Height without Ge3N4 (eV) 0.61 0.52 0.55 0.59 0.64

Barrier Height with Ge3N4 (eV) < 0.3 < 0.3 < 0.3 0.51 0.54

Table 4.1. Summary of effective barrier heights calculated from I-V measurements for several metal work functions with and without an ultrathin 0.7nm Ge3N4 dielectric [73]. In cases where no barrier was observed, the barrier height is estimated to be less than 0.3 eV.

Next, Nishimura et al. [72], explored the use of thin oxides rather than nitrides for the MIS contact on n-type and p-type Ge(100) substrates, studied the effect of oxide thickness on barrier height, and successfully fabricated a Ge SB-FET. After native oxide removal, GeOx and AlOx were RF sputtered at room temperature and then annealed at 400oC in N2. From the current-voltage characteristics shown in Figure 4.4, as the oxide thicknesses is increased from 0 to 2.2 nm, n-Ge diode behavior was transformed from rectifying to ohmic, while p-Ge diode behavior was transformed from ohmic to rectifying. For the p-Ge MIS contact, the reverse current is interestingly asymmetrically suppressed by the oxide, which differs from the typical tunneling limited current behavior that would reduce the current in both forward and reverse biases. These results are important in demonstrating that the reduction in barrier height is not limited to the use of nitrides, but can also be extended to oxides despite the strong pinning nature of the Ge native oxide. Also, it illustrates that the dielectric deposition method is not very critical and is not limited to the gentle thermal nitridation process since even sputtered oxides that could potentially damage the surface can be used.
50

(a)
Current(A/cm2)
102 100 102

n Ge

(b)
Current(A/cm2)

p Ge

102 100 102 104 10.500.51

104 10.500.51 Voltage(V)

Voltage(V)

Figure 4.4. Current-voltage characteristics for Al/GeOx/Ge diodes. (a) For n-Ge, the reverse bias current increases with GeOx thickness indicating a reduction of the barrier height. (b) For p-Ge, the current is asymmetrically suppressed by the oxide. Figures are from Ref#[72].

The change in barrier height with oxide thickness is summarized in Table 4.2. The roughly same B,eff of 0.45eV extracted for Al (M=4.1eV) and Au(M=5.1eV) despite a 1.0eV difference in metal work function suggests that Fermi level pinning is just reduced, but not removed. Furthermore, a B,eff of 0.44-0.46eV was found for both n-type and ptype Ge, where if there was true Fermi level depinning, the barrier heights should add up to be the bandgap (B,n + B,p = Eg).
GeOx Thickness (nm) 0 0.6 1.1 1.6 2.2 Al SBH on n-Ge (eV) 0.57 0.53 0.45 Ohmic Ohmic Au SBH on n-Ge (eV) 0.59 0.56 0.55 0.44 Ohmic Al SBH on p-Ge (eV) Ohmic Ohmic Ohmic 0.50 0.46 Au SBH on p-Ge (eV) Ohmic Ohmic Ohmic Ohmic 0.46

Table 4.2. Summary of effective barrier heights for Al and Au MIS contacts for varying thicknesses of GeOx [72]. Ohmic denotes cases where the on/off current ratio at 1V is less than 10.
51

Kobayashi et al. [71] further explored the MIS structure though the use of a thin RF sputtered silicon nitride (SiN), and reported the lowest barrier height of 0.05eV on Er/SiN/Ge, reduced from the Er/Ge Schottky barrier of 0.45 eV. In addition to B,eff measurements, the contact resistance (RC) as a function of the insulator thickness (tINS) was studied for the first time. The overall RC vs. tINS curve (Figure 4.5) is a tradeoff between reduced B,eff and increased RT, where there exists an optimal tINS for minimal RC. For Al/SiN/Ge, the minimum RC was found to be 2 nm.
106 105 104 103 102 101 100

ContactResistance(cm2)

Al/SiN/nSi,nGe Schottkydiode

101 102

RC

MinRC inGe

01234

SiN Thickness(nm)
Figure 4.5. Measured contact resistance versus SiN thickness for the Al/SiN/Ge MIS diode. The minimum RC occurs at 2nm. From Ref# [71].

Through these various examples of Ge MIS contacts, it is clear that the MIS contact structure has great flexibility in both the material choice and deposition method. As Kobayashi et al showed, the optimal dielectric thickness and the minimum achievable B,eff depends on both the metal and dielectric materials, where there are many more possible metal and dielectric combinations to be studied. Table 4.3 summarizes the existing MIS literature at the beginning of our study.

52

Semiconductor

Dielectric Si3N4

Deposition Method Thermally Grown Thermally grown SiO2 and ALD high- Sputtering Sputtering Plasma Nitridation ALD

Reference [66] [75] [71] [72] [73] [74]

Si

SiO2 /AlOx SiO2 /LaOx SiOxNy

Ge

GeOx AlOx Ge3N4 TiO2

Table 4.3. Summary of Si and Ge MIS contact literature.

Prior to our work, the MIS contact structure has only been investigated for elemental semiconductors Si and Ge, and as described in the beginning of this section, III-V semiconductors would also benefit from the ability to reduce the Schottky barrier height. We demonstrate for the first time the use of MIS contacts on compound semiconductor materials GaAs and In0.53Ga0.47As, and implement an optimized contact to the source/drain of an InGaAs MOSFET. Furthermore, in the Ge MIS literature each research group focused on only one or two combinations of dielectric and metal materials so there was no comprehensive study of how these two parameters affect the minimal achievable contact resistance. In this chapter, we investigate the use of SiN, Al2O3, HfO2, ZrO2, TiO2, and ZnO dielectrics, along with a study of how the deposition temperature can affect the contact behavior. Substrate doping and a wide range of metal work functions from Y (M = 3.1eV) to Pt (M = 5.65eV) were also studied to provide a more complete understanding. Although the results are based on III-V semiconductors, the understanding can also be extended to Si and Ge MIS. The results from this chapter will aid in the elucidation of the underlying physical mechanism behind the reduced barrier heights discussed in the next chapter.

53

4.3 Device Fabrication

For the initial III-V substrate, GaAs is chosen for its large bandgap to facilitate B,eff extraction, and also as a baseline III-V material to develop a contact structure that can be extended to other more technologically relevant III-V materials such as InGaAs, GaSb, and InSb for future CMOS. The MIS contact fabrication started with the use of lightly doped (2x1016cm-3) MBE grown n-GaAs to emphasize the thermionic emission current over the barrier and to more accurately extract barrier height values. For GaAs, the native oxide forms a low density, high surface states interface which causes strong Fermi level pinning. Therefore, great care needs to be taken in minimizing the formation of native oxide during contact fabrication. The samples underwent an organics degrease by sonication in a 1:1 acetone and methanol solution, followed by rinsing in deionized (DI) water for 1 minute. The native oxide was then removed by soaking the samples in a dilute HCl solution (1:1 = DI water : 29% HCl) for 3 minutes, followed by a 20sec DI water rinse with agitation. Immediately after the rinsing step the samples were immersed in 5% ammonium sulfide (NH4)2S solution for sulfur passivation. After soaking for 15min the samples were removed and rinsed well in DI water and dried by nitrogen gun and immediately loaded into the ALD chamber to minimize native oxide formation. Sulfur passivation in (NH4)2S has been shown to terminate the substrate with Ga-S and As-S bonding[27] which helps prevent further oxidation. The bonding is stable for up to 30 minutes in air, however, the time between passivation and dielectric deposition were still minimized and kept under 5 minutes. The dielectric films were deposited by RF sputtering in the AJA tool and ALD in the Cambridge Nanotech Savannah tool. Amorphous SiN was sputtered from a stochiometric Si3N4 target at 200oC under Ar/N2 ambient, where bias and heat were applied to achieve a dense and uniform film. Al2O3, HfO2, ZrO2, TiO2, and ZnO were ALD deposited using standard pulse and purge times. Table 4.4 summarizes the precursors used and the deposition temperature. The deposition temperatures were mostly higher than in the standard recipe for higher quality, denser films. The maximum temperature of 250oC was used in most cases, except for ZrO2 and ZnO were at higher
54

temperatures the precursors would no longer adsorb well on the sample surface. To minimize GaAs native oxide formation, the metal organic precursor was used as the starting pulse, to follow with the self-cleaning [43] observed in Al2O3 and HfO2. After the dielectric deposition, the samples were loaded into shadow mask holders and the diodes were defined by metal evaporation in Innotec. The metal thickness depended on the material and varied from 75nm for Pt to 150nm for Al. When the front metal is finished, the shadow mask holders were flipped and the backside of the samples were lightly scratched using a diamond scriber in crosshatch patterns to remove the native oxide immediately prior to loading the samples for the 50nm Ti + 150nm Au back contact deposition in Innotec. The final device structure along with a cross sectional TEM is shown in Figure 4.6.
Film Al2O3 TiO2 HfO2 ZrO2 ZnO Metal Precursors TMA TDMAT TDMAH TEMAZ DEZn ALD Reaction (CH3)3 Al + H2O [(CH3) 2N]4 Ti + H2O [(CH3) 2N] Hf + H2O (CH3C2H5)4 Zr + H2O (C2H5) 2Zn + H2O Temp. 250oC 250oC 250oC 200oC 160oC

Table 4.4. Summary of the ALD precursors and deposition temperature.

Metal

Insulator

Al SiN 2.1 nm

2e16 cm-3 n-GaAs

300 nm

n+ GaAs

10 nm

n-GaAs

Figure 4.6. (a) Schematic diagram of the contact structure. (b) Cross sectional TEM image of the Al/SiN/n-GaAs contact, illustrating an amorphous, uniform SiN film of the expected 2nm thickness.

55

4.4 Electrical Characterization

4.4.1 Contact Resistance Measurement
The contact resistance (RC) of the MIS can be modeled as two resistances in series: (1) RT, a tunneling resistance through the insulator, and (2) RSB, a resistance associated with the barrier. With no insulator, the highly pinned Schottky barrier causes RSB to dominate RC. With a thin insulator present, assuming a reduced B,eff, the lower RSB would reduce the overall RC. However, as the insulator thickness is further increased, the current becomes tunneling limited and the increasing RT begins to dominate, resulting in a high RC. Figure 4.7 illustrates the overall expected RC vs. tINS curve provided that the effective barrier height is successfully reduced. A tradeoff exists between a reduced B,eff and an increased RT, where there exists an optimal tINS to minimize RC.
Contact Resistance (log)

(a)

RSB Branch

RT Branch

Insulator Thickness

Contact Resistance (log)

(b)

RSB Branch
Barrier Height Dominates

RT Branch
Insulator Tunneling Dominates

Optimal Thickness Insulator Thickness

Figure 4.7. (a) The RSB branch decreases with insulator thickness as B,eff reduces, while the RT branch increases with thickness due to tunneling limitations. (b) Schematic of RC vs. tINS after RT and RSB are connected in series. There exists an optimal insulator thickness for minimal contact resistance, which arises from the tradeoff between a reduced barrier and and an increased tunneling resistance.
56

RC was measured using the contact end resistance method [32] with the setup shown in Figure 4.8a. Since this is not a simple two terminal method, the absolute current and voltages used in the measurement will change with the contact resistance. In the contact end resistance method, current is forced through two contacts and the voltage drop is measured across another two, where the contact resistance is given by : RC = V/I. According to Schrder [32], the applied current should be varied such that the voltage drop is only a few tens of mV. The measured contact resistance of a Al/SiN/n-GaAs diode is shown in Figure 4.8b, and is found to display the expected RC vs. tINS curve. One key point is the existence of a minimum RC for tINS > 0, which proves successful reduction in B,eff, or else RC would only increase with tINS. The optimal tINS is found to be about 2nm, but this could depend on the metal, dielectric, and semiconductor used.

Contact Resistance Ratio

(a)
V

(b)
I Metal pad

10 10 10 10

Al/SiN/GaAs

-1

Rc Rsh

Rc

SiN Substrate

-2

-3

1 2 3 Dielectric Thickness (nm)

Figure 4.8. (a) RC measurements using the contact end resistance method [32]. Figure from Ref#[71]. (b) RC ratios are taken relative to the Schottky case. The Al/SiN/n-GaAs MIS shows the expected RC tradeoff with dielectric thickness.

It should be noted that these MIS contacts have been made on low doped substrates to minimize the tunneling current through the barrier and to emphasize the thermionic emission current over the barrier. This allows for a more accurate extraction of the barrier height and highlights the effect of changes in B,eff. However, low doping results in higher RC, so RC ratios taken relative to the Schottky case, are reported here. Much lower absolute RC can be achieved by simply increasing the doping.
57

4.4.2 Diode Current Measurement

Diode current was measured for back-to-back Schottky diodes to eliminate the large resistance contributions from the series resistance and the back contact resistance due to the lightly doped substrate. The back-to-back diode measurement is illustrated in Figure 4.9a, where in both positive and negative biasing only the reverse current is measured. Fortunately, the B,eff modulation is mostly reflected through changes in the reverse current, where maximum reverse current is desired for ohmic contacts. As shown in Figure 4.9b for an Al/SiN/n-GaAs diode, by simply increasing the SiN thickness, the reverse current is transformed from rectifying Schottky behavior, to increased conduction, to tunneling limited, where the arrow indicates the direction of change. In fact, the reverse current for a Al/SiN(3.6nm)/n-GaAs is greater than that of a Al/n-GaAs Schottky diode, clearly indicating a reduction in B,eff with a non-zero SiN thickness. Otherwise, with no change in the effective barrier height, the reverse current should only decrease with increasing SiN thickness, due to the thicker SiN tunnel barrier.

(a)
V

(b)
2 |Current| (A/cm )

10

-2

Increasing Thickness

10

-4

10

-6

Al/SiN/GaAs
-1 -0.5

tSiN = 0 tSiN = 1.2 nm tSiN = 1.6 nm tSiN = 1.8 nm tSiN = 2.1 nm tSiN = 3.6 nm

Voltage

0.5

Figure 4.9. (a) Illustration of the back-to-back diode measurement setup where only the reverse current is measured. (b) Back-to-back Al/SiN/n-GaAs diode measurements demonstrate the effective modulation of B,eff by the SiN thickness.

58

4.4.4 Effect of Semiconductor Doping

In Figure 4.10a, we investigated the effect of substrate doping and found there is a slightly wider tINS process window for achieving low contact resistance in higher doped substrates (doping density of 2x1017cm-3). The reasoning lies in the reduction of the depletion width with higher doping, which causes the Schottky barrier tip to become thinner (Figure 4.10b). This effectively thinner tunneling barrier increases the tunneling current significantly and reduces the tunneling resistance penalty. This can be viewed as shifting the RT curve towards the left and the RSB curve towards the right, as illustrated in Figure 4.10c. Overall, increased doping lessens the tunneling penalty in RC.

Contact Resistance Ratio

(a)

10 10 10 10 10

Al/SiN/GaAs : 2x10 cm 17 -3 Al/SiN/GaAs : 2x10 cm

16

-3

-1

-2

-3

1 2 3 4 SiN Thickness (nm)

Contact Resistance (log)

(b)

Low Doping

(c)

Nominal RSB

Lower RT : Doping

Tunnel Current High Doping

Insulator Thickness

Figure 4.10. (a) RC vs. tINS for different substrate dopings. (b) Higher doping

increases the tunneling through the semiconductor. (c) Higher doping effectively shifts the RT curve towards the left and the RSB towards the right.
59

To investigate the effect of higher substrate doping, the tunneling currents in the Al/SiN/n-GaAs contact structure were simulated with a fully self-consistent NEGF (nonequilibrium Greens function) using the effective mass approximation [76]. Taking our minimum achieved specific contact resistivity C of 2.0 -cm2 for 2 x 1017 cm-3 as the reference point, it is projected that we can achieve C of 10-5 -cm2 by increasing the doping to 1x1019cm-3 (Figure 4.11a). Further reduction of RC is possible taking into account the thinner optimal tINS needed for higher substrate dopings. Reducing tINS from 2nm to 1.1 nm reduces C to 10-7 -cm2 (Figure 4.11b).

(a)
Specific Contact Resistivity Ratio
10
0

Assumes a constant optimal insulator thickness of 2nm

(b)
Specific Contact Resistivity Ratio
10 10 10 10 10
0 -1

Assumes a constant barrier height

At 1019cm-3, 1.1nm C = 10-7 -cm2

10

-2

Our result at 1017cm-3 C = 2.0 -cm2 At 1019cm-3, tSiN=1.5nm C = 2.0x10-5 -cm2

-2

-3

10

-4

-4

1 x 10 1 x 10

18 19

cm cm

-3 -3

Doping Doping
1.4 1.6

10 16 10

-6

Substrate Doping (cm )

10

18

10

20

-3

10

22

0.4

0.6

SiN Thickness (nm)

0.8

1.2

Figure 4.11. Dependence of the tunneling limited contact resistance on substrate doping is simulated by a fully self-consistent NEGF simulation of Al/SiN/nGaAs. (a) Ratios are taken relative to RC at 1017 cm-3 doping. Specific contact resistivity is reduced by 5 orders of magnitude when the doping is increased from 1017 to 1019cm-3. (b) Increasing the doping decreases the optimal insulator thickness, where the specific contact resistivity further decreases exponentially.

4.4.3 Effect of Metal Work Function

To study how the work function of the metal M affects the MIS contact, metal/SiN/GaAs samples were fabricated using Y (M = 3.1eV), Er (M = 3.1eV), Al (M = 4.1eV), and W (M = 4.3eV). For samples of the same thickness the SiN was sputtered together, therefore the only difference should be in the metal deposition. Er and Y are very reactive and oxidize easily, so a 50nm Pt capping layer was deposited in-situ.
60

The RC vs. tSiN plot for various metals (Figure 4.12a) confirms the B,eff reduction is not limited to Al metals. Samples with higher work function metals became tunneling limited earlier on, and the optimal thickness is inversely dependent upon the metal work function. This can be understood by looking at the band alignment (Figure 4.12b) to see that higher M results in larger tunnel barriers T, which can be modeled as an inwards shift of the RT branch (Figure 4.12Figure 4.c). The lowest achievable contact resistance also has a dependence on M, where low work function metals (Al or Ti) are desired for n-type contacts to push out the onset of the tunneling resistance domination. The reverse is also true for p-type contacts where high M metals (Pt or Au) are desired to minimize RC.

Contact Resistance Ratio

(a)

10 10 10 10

-1

-2

-3

10

-4

Y (3.1 eV) Er (3.1 eV) Al (4.1 eV) Ti (4.3 eV)

1 2 3 SiN Thickness (nm)

Contact Resistance (log)

(b)
T
Tunnel Current

(c)

Nominal RSB

Higher RT : M

Insulator Thickness
Figure 4.12. (a) RC ratio of metal/SiN/GaAs MIS using different metal materials. The optimal SiN thickness is found to depend on the metal work function M. (b) High M materials will have higher tunnel barriers. (c) The higher T

61

translates into a larger tunneling resistance penalty from the insulator.

Next, effective electrical barrier heights are measured to see if B,eff has any dependence upon M. In the absence of a model that accurately captures both thermionic and tunneling currents in the MIS, the term B,eff is used to represent the overall electrical behavior of the MIS structure, modeled as a simple metal-semiconductor. This simplification is used since an ohmic contacts performance is ultimately determined by the electrical behavior. We note that this is not equal to the difference in Fermi levels of the metal and semiconductor since the insulator is not accounted for. The thermionic emission model [32] is used to extract B,eff through diode measurements between -40 and 60oC using the Cascade Micotech probe station and Temptronic temperature controller set up. The ideality factor n is first extracted from simple room temperature diode measurements. Considering biases in the range where the series resistance is negligible (V << I*Rseries), a very linear relation can be plotted, with the equations and sample data shown in Figure 4.13. All the measured data is verified to have a good linear fit to give confidence in the extracted ideality factors.
Al/GaAs Schottky
Data Linear Fit

-4

log [I/(1-exp(-qV/kT))]

-6 -8 -10 -12 -14

I = AA * T 2 e q B /kT e qV/nkT 1 e qV/kT

I q q ln V = ln AA * T 2 B + qV/kT kT nkT 1 e
slope

n = 1.04
0 0.05 0.1 0.15 0.2

Voltage
Figure 4.13. The equation and linear fitting used to calculate the ideality factor.

To calculate B,eff, the diode current change with temperature is measured and plotted to verify a consistent trend across the entire temperature range (Figure 4.14a). Using a bias between 0.1 and 0.2 V where the series resistance is negligible and V >>

62

kT/q, the corresponding current is plotted against temperature to generate the Arrhenius plot to extract B,eff (Figure 4.14b).

(a)
|Current| (A/cm )

(b)
Er/SiN/GaAs , V=0.2V
-22

10 10 10 10

Decreasing Temperature
T = 60oC T = 40oC T = 20oC T = 0oC T = -20oC T = -40oC

-2

ln(I/T2) [A/K2]

-24 -26 -28 -30 3

-4

Bias where V >> kT/q

3.2 3.4 3.6 3.8 4 4.2

-6

-1

-0.5

Voltage (V)

0.5

1/T [K ]

-1

(c)

I = AA* T 2eqB/kTeqV/nkT 1 eqV/kT

qV/n q B 1 I ln 2 = ln (AA *) + k T T slope V k B = slope n q

) For V >> kT/q

Figure 4.14. (a) Diode current measurement over a range of temperatures. (b) B,eff extraction from the Arrhenius plot. (c) Equations used in the calculation.

Figure 4.15a shows the measured B,eff with tSiN for Er, Y, Al, Ti, and W. The measurements confirm a highly pinned metal/n-GaAs Schottky barrier with a significant reduction in B,eff at the optimal SiN thickness. The ideality factor for the Schottky barrier is 1.04, close to that of a pure thermionic emission (n=1), shown in Figure 4.15b. When n > 1, the current flow can be due to mechanisms other than thermionic emission, including tunneling or field emission, and there can be the presence of interface damage or interfacial layers. As expected, the ideality factor increases with tSiN since conduction becomes limited by tunneling through the SiN, which causes the change in current per unit change in voltage to decrease. Similar to our definition of B,eff, our extracted ideality factor n should not be interpreted in exactly the same way as in a conventional

63

Schottky barrier equation, due to the presence of an insulator or RT. Also, any error in the ideality factor would be propagated to the barrier height value.

(a)
0.8 Barrier Height (eV) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1 2 3 SiN Thickness (nm) 4
Er Y Al Ti W (3.1 eV) (3.1 eV) (4.1 eV) (4.3 eV) (4.5 eV)

(b)
2.4 2.2 Ideality Factor 2.0 1.8 1.6 1.4 1.2 1.0 0 1 2 3 SiN Thickness (nm) 4
Er Y Al Ti W (3.1 eV) (3.1 eV) (4.1 eV) (4.3 eV) (4.5 eV)

Figure 4.15. The B,eff are extracted from diode measurements between 233 and 353K using the thermionic emission model[32]. (a) B,eff is found to decrease with increasing SiN thickness. (b) The ideality factors increase with SiN thickness roughly independent of the metal, as the current becomes limited by tunneling through SiN.

1.2

Barrier Height (eV)

1.0 0.8 0.6 0.4 0.2 0.0

Metal/nGaAsSchottkyDiode(Pinned) n Metal/SiN/nGaAs(Unpinned) n

0.38 eV 0.51 eV 0.41 eV 0.40 eV W Y, Er Al Ti

3.5 4 4.5 Metal Work Function (eV)

64

Figure 4.16. Effective barrier height vs. metal work function for Schottky diodes and MIS contacts. There is a roughly parallel shift in B,eff independent of M.

The overall change in the barrier heights of Schottky barriers (without SiN) and MIS contacts (with SiN) are summarized in Figure 4.16Figure 4.. Initially, the GaAs surface is strongly pinned between 0.6 to 0.8 eV, but after inserting SiN, B,eff is reduced to 0.2 to 0.4 eV. However, even though B,eff is reduced, the surface is still strongly pinned because M varies by 1.5 eV but B,eff only changes by 0.2 eV. The reasoning behind the change in barrier height will be discussed in detail in the following chapter. The lowest achieved barrier height is 0.18eV using Er, and even though it is a significant reduction from the pinned 0.75eV, it is still far from the desired near zero barrier height. As mentioned in the beginning of this section, the reported B,eff is related to the electrical behavior and not the actual difference in the Fermi level between the metal and semiconductor, as traditionally defined for Schottky barriers. In fact, the measured effective barrier height is actually larger than the actual barrier height, and this can be understood by looking at how B,eff is extracted. From the equations in Figure 4.14c, B,eff is measured through how much the current changes with temperature. For a greater change per change in temperature, B,eff is smaller. However, MIS contacts have a tunneling current through the insulator component that doesnt change with temperature. In this case, if the tunneling resistance dominates and the current is attenuated, then there is less change with temperature and B,eff is larger. When the tunneling current is small, the extracted value should not be affected.

4.4.5 Effect of Insulator Material

The effect of the dielectric on the MIS contact is studied first by comparing the use of Al2O3 and SiN. Figure 4.17 explores the RC and tINS tradeoff, where SiN appears to be the better candidate for contact applications due to its lower achievable RC. The one order of magnitude lower RC of SiN suggests it may be possible to achieve an even RC with the use of alternative dielectrics. The results also highlight the large effect of the band offset on the tunneling resistance RT in the MIS structure. The band offsets of Al2O3
65

(EC=2.75eV) and SiN (EC=1.5eV) only differ by 1.25eV, but the intrinsic exponential dependence of the tunneling current on the potential barrier amplifies this difference.

Contact Resistance Ratio

10 10 10 10 10

Al/Al2O3/GaAs Al/SiN/GaAs

-1

-2

-3

1 2 3 Dielectric Thickness (nm)

Figure 4.17. Comparison of the RC vs. tINS tradeoff for SiN and Al2O3. SiN appears to be the better candidate for contact applications due to its lower EC of 1.5eV.

To further understand the RC tradeoffs involved, additional dielectrics (HfO2, ZrO2 and TiO2) are investigated in Figure 4.18a. It is rather surprising that all of the MIS formed using these dielectrics show a reduction in RC and B,eff. It appears that the GaAs effective barrier height can be tuned by using many different dielectrics, broadening the applicability of these contacts. However, each of the dielectrics has a different RC tradeoff, so the minimum achievable contact resistance depends on how the dielectric material affects the RSB and RT branches. The RT branch is limited by tunneling through the dielectric barrier, where the tunnel barrier height depends on the dielectric to semiconductor EC (Figure 4.18). Materials with a lower EC can reduce the slope and shift the RT branch outwards to the right (Figure 4.18c). The EC for these materials are provided in Chapter 2. The effect of the dielectric on RSB depends on the amount of reduction in B,eff, so if the underlying mechanism is due to an interface dipole, then a larger dipole would give RSB a steeper slope and shift outwards towards the left. The ideal dielectric would be one that has a larger B,eff and zero or even negative band offset (EC for n-type and EV for p-type) to reduce the tunneling penalty on RC. Of the investigated materials, TiO2 formed the best single dielectric MIS because it has both a
66

large dipole and a small conduction band offset.

(a)
ContactResistanceRatio

102 101 100 101 102 103 104 105 0

Al2O3 Al2O3 SiN SiN TiO TiO22 HfO HfO22 ZrO2 ZrO2

DielectricThickness(nm)
Contact Resistance (log)

(b)
EC Tunnel Current

(c)

RSB Branch
Dipole

RT Branch
EC

Insulator Thickness

Figure 4.18. (a) RC vs. tINS tradeoff between different dielectrics for Al/dielectric/GaAs MIS. (b) The tunneling barrier height depends on the dielectric/semiconductor conduction band offset. (c) Dielectric materials affect both the RSB and RT branches, so the tradeoff for each dielectric depends on the dipole magnitude and the EC. See Chapter 2 for the measured EC values.

4.4.6 Summary
Figure 4.19 summarizes how changing the various material parameters affects the overall RC vs. tINS tradeoff. For an ultra low contact resistance on n-type substrates, a

67

combination of high electrically active doping, low metal work function, and low tunnel barrier heights area necessary for an overall low effective barrier heights.
Nominal RSB Higher RT : M or EC Lower RT : Doping

Contact Resistance (log)

Insulator Thickness

Figure 4.19. Schematic of RC vs. tINS. The effect of different metals, dielectrics, and substrates on the tradeoff between RC and insulator thickness is shown.

4.5 III-V MOSFET S/D Contacts

After studying the MIS contact on GaAs, we turn to more technologically relevant higher electron mobility material InGaAs. The substrate composed of a 300nm thick (doping density of 1x1016 cm-3) MBE grown In0.53Ga0.47As that is lattice matched to the InP wafer (Figure 4.20a). The MIS is fabricated in a similar fashion to the GaAs MIS contacts, with the exception of an ammonium hydroxide NH4OH passivation using 1:1 DI water diluted solution for 5 min rather than the HCl + (NH4)2S step. Although sulfur also passivates the InGaAs surface, the use of HCl is undesirable because it etches the InP substrate rather quickly and can significantly roughen up the back of the samples making it difficult to use the substrate for a back contact. The etch products could also potentially redeposit on the InGaAs surface. The RC vs. tSiN for the InGaAs MIS (Figure 4.20b) shows a similar trend as the GaAs MIS in contact resistance and barrier height reduction. However, the contact resistance is only reduced by one order of magnitude because InGaAs is a more conductive material with a smaller bandgap of 0.75eV as compared to the 1.42eV of

68

GaAs. The Fermi level of InGaAs also pins closer to the conduction band than GaAs which pins closer to midgap (Figure 4.2).
Insulator

Contact Resistance Ratio

(a)

(b)
300 nm 100 nm

10

Al/SiN/In0.53Ga0.47As

1e16 cm-3 n-InGaAs 1e16 cm n-InAlAs

-3

n+ InP

10

-1

2 3 4 SiN Thickness (nm)

Figure 4.20. (a) MBE grown n-InGaAs substrate on InP. (b) RC tradeoff indicates the successful reduction in barrier height.

Since the InGaAs MIS has been shown to shift the metal/semiconductor Fermi level, the next step is to apply this non-alloyed, highly scalable MIS contact to an In0.53Ga0.47As MOSFET and demonstrate the compatibility of the non-alloyed contact technique with existing III-V MOSFET fabrication. This is an important step forward as any proposed process module must have a demonstrated path for being incorporated in a fully integrated device process flow. For the implementation of this MIS S/D contact structure, gate last In0.53Ga0.47As MOSFETs with a Ni/Al2O3/InGaAs gate stack were fabricated (Figure 4.21). The channel material was MBE grown p-type In0.53Ga0.47As (Be-doping of 6x1015 cm-3) insitu capped by 50nm of arsenic to prevent oxidation. After an organics degrease, samples were loaded into an atomic layer deposition (ALD) chamber and the As capping layer was desorbed at 400oC for 5 min, followed by 30nm of Al2O3 deposited at 300oC using trimethyl-aluminium (TMA) and H2O precursors to serve as a sacrificial implantation oxide. The samples were then patterned and wet etched to define mesas for device isolation and fabrication of contact resistance structures. S/D regions were selectively implanted with Si at 30keV and 80keV with a dose of 2x1012cm-2, then rapid thermal annealing (RTA) activated at 600oC for 30s in N2. The 30nm thick Al2O3 capping layer is critical in preventing arsenic desorption from the InGaAs surface. The sacrificial
69

implantation oxide was then stripped in 2% HF, followed by native oxide removal in NH4OH immediately prior to loading in the ALD chamber for 10nm of Al2O3 gate oxide.
S/DtoGspacing =1,2,or4m Isolation Oxide

G
pInGaAs (6x1015 cm3)

10nmAl2O3 GateOxide 300 nm 200nm

pInGaAs (Bedoped1x1017 cm3) p+InP Substrate

Figure 4.21. Schematic view of the fabricated InGaAs MOSFET with 10 nm ALD Al2O3 gate oxide. Cross-hatched area represents the implanted regions.

Next, a 75nm Ni gate electrode was lift-off patterned and e-beam evaporated. A 50nm Al2O3 field oxide was used for further device isolation and contact area definition. After a (NH4)2S sulfur treatment, an ultrathin amorphous silicon nitride was sputtered from a Si3N4 target at 200oC, followed by Al evaporation for S/D contacts. Circular transmission line method (TLM) structures were used to characterize the contacts because they have the advantage of self isolation [32] so current can only flow from the central contact to the surrounding contact. The TLM was fabricated together with the MOSFET Source/Drain contacts and should reflect the behavior of the S/D contacts. Different gap sizes between contacts pads were used with dimensions of 5, 10, 15, 20, 25, 30, 40, and 60 m. The results were quite linear, as shown in Figure 4.22a. Contact resistance measurements of the different MIS contacts show a similar RC vs. tINS trend as observed in the diode structure (Figure 4.22b). However, the lowest achieved C of 2.9x10-3 -cm2 still remains fairly high due to the low S/D doping implied from the large parasitic resistance (RSD) of 90 -mm, extracted by plotting total resistance (RTOT) vs. gate length (LG), where RTOT = VD/ID in the linear operation [32] (Figure 4.22c). The S/D active doping is calculated to be between 1.6x1016 and 2.5x1016 cm-3 using the measured sheet resistance of 1300 /, simulated junction depth of 200 300nm from SRIM (Stopping and Range of Ions in Matter)[77] , and doping dependent
70

mobility from a Caughe m m ey-Thomas based mode el[78]. This level of electrically a active dopants is in nsufficient, but as men ntioned earl lier, higher temperatur annealing can re g im mprove dopant activatio but will also cause arsenic desorption in the InGaAs that on, l e s in nduces nega ative charges and interf face traps w which degra the mob ade bility. Simul lation using a fully self-consist tent NEGF s showed that there can b continual reduction i RC t be l in with w higher doping, partly due to the thinner optim tINS for h d y mal higher subst trate dopings s[76].

(a)
Total Resistance ()

1.5x10 0 1.2x10 0 9.0x10 0 6.0x10 0 3.0x10 0

3
2

(b)
Contact Resistivity (-cm )

1.5x10 1.0x10

-2

-2

5.0x10

-3

0. .0

10 20 30 40 50 60 0 0 Dis stance (m)

0.0

Al A Schottky Al/2nm SiN Al/1.5n SiN nm

Ni/Al2O3/In0. Ga0.47As .53

(c) (

(d)
Capacitance (uF/cm2)

0.4 MOSCAP 4 0.3 3 0.2 2

0.1 f = 2 kHz 1
to 1 MHz

tOX = 10 nm

-2

Volta age

Figure 4.22. (a) Ci e ircular TLM d data illustrati linearity. (b) TLM me ing easurement

results show similar RC trends as from diodes (c) RTOT vs. L plot from MOSFETs s r s s. . of diff ferent dimensions. (d) MO OSCAP C-V fr from 2kHz to 1MHz demonstrating a fairly good gate stack with a mid g dgap DIT of 1.6 x1012 cm-2e -1. eV

Electr rical charact terization of the fabrica f ated MOSFE gate sta through C-V ETs ack measurement of MOSCA (Figure 4.22d) illus m ts APs e strates a fair good gate dielectric w a rly e with
1 midgap inter m rface trap de ensity (DIT) of 1.6 x1012 cm-2eV-1 measured by the high 0 h-low

71

frequency method [32]. The DIT matches those of simple MOSCAPS fabricated using shadow masks, which suggests that the gate stack was not degraded through fabrication. MOSFET measurements of ID-VG in Figure 4.23a show an enhancement mode device with good gate control and low gate leakage that is almost three orders of magnitude lower than the on-current. The ID-VD in Figure 4.23b shows linear behavior in low VD. In the case of severe current degradation by series resistance, the current behavior at low drain biases would become quadratic because the series resistance would overshadow any changes in the channel resistance.

(a)
I D [A/m]

10 10 10

2 1 0

Al/2nm SiN Contact L = 10 m

(b)

15 10 5 0

VG = 0 to 4V

10 10 10

-1 -2 -3 -4

10

VD = 0 to 4V VT = 0.2 V

I D [A/m]

-1

1 2 VG [ V ]

2 3 VD [ V ]

Figure 4.23. Implementation of the Al/2nm SiN contact in a surface channel enhancement mode InGaAs nMOSFET with L=10 m and W = 320 m. (a) The ID-VG does not show significant gate leakage. (b) The ID-VD shows linear behavior in low VD, whereas for severe series resistance it would be quadratic.

In our III-V MOSFET fabrication process, the processing temperature is a limiting factor as there is a trade off with higher Si dopant activation and lower channel effective mobility. This thermal budget limit in the dopant activation of InGaAs results in our low active source/drain doping concentration. If the dopant activation were to increase, the contact resistance would decrease from the larger tunneling current component. Dopant activation may be improved by using different dopants such as Ge, carbon, and sulfur, but we have not studied this and instead used Si because it is the most common donor element. Another possibility is the use of metastable laser annealing to

72

achieve doping levels that exceed the solid solubility limit. By using a reflective gate metal, higher activation can be achieved without damaging the gate stack. This has been studied recently on InGaAs [79] and Ge [80], and could greatly improve our MOSFETs. The purpose of this work is not to demonstrate the lowest possible RC on the highest performing III-V MOSFET, but rather to prove the concept and implement this scalable MIS contact structure for III-V MOSFETs. The scalability is a physical scalability that arises from the absence of contact alloying. The physical contact sizes demonstrated here are large due to equipment restrictions of a contact mask aligner for lithography and a sputtering tool to deposit the ultrathin silicon nitride, but in principle, with the use of better lithography tools and an ALD to deposit the silicon nitride, very small dimensions can be achieved. We show that the MIS contact structure can be implemented in a MOSFET structure. With our work as a starting point, there are still many more metal and dielectric materials to be explored, and a much lower contact resistance could be achieved using this structure with the optimal material combination.

4.6 Summary
The MIS contact structure has demonstrated great promise on Si, Ge, and III-V materials through the use of a variety of thin dielectrics to reduce the effective electrical barrier height and contact resistance of a pure metal-semiconductor contact. The effect of the metal work function, semiconductor doping, and insulator material have been investigated, where the overall minimum achievable contact resistance and barrier height depend on the material properties. For a low contact resistance, both heavy doping and low barrier heights are required. The single dielectric MIS contact demonstrated barrier heights as low as 0.27eV using SiN, but this can most likely be further reduced with the use of different combinations of materials. There exists great flexibility in the choice of dielectrics and metals for the contact design. This MIS contact structure has been successfully demonstrated on InGaAs nMOSFETs, which can be applied to make scalable non-alloyed ohmic contacts for other III-V semiconductor MOSFETs, and also

73

tunable barrier heights for III-V Schottky barrier FETs.

Chapter 5 Physical Mechanism of Single Dielectric MIS Contacts

Expanding on the experimental results of the single dielectric MIS contacts in the previous chapter, we discuss in detail the underlying physics for the observed barrier height reductions. The Fermi level is discovered to be shifted rather than unpinned as reported in Si and Ge MIS literature and summarized in Chapter 4. The effect of bulk fixed charge in the ALD dielectric films are also studied for the first time and found to contribute to barrier height lowering. Fixed charge in combination with interface dipoles provide a more thorough understanding of the MIS contacts. Though this study is based on III-V MIS, the results can be extended to the understanding of Si and Ge MIS contacts.

5.1 Introduction
In the previous chapter, we demonstrated a reduction of the effective barrier height of metal/n-GaAs and metal/n-In0.53Ga0.47As junctions using MIS contacts with a variety of metals (Y, Er, Al, Ti, W) and dielectrics (SiN, Al2O3, TiO2, ZrO2, HfO2, ZnO). The barrier height lowering was verified through direct measurements and deduced from increased diode current and reduced contact resistance. The MIS contact structure allows us to engineer non-alloyed ohmic contacts for the source/drain of III-V MOSFETs. However, in order to do so, we need a thorough understanding of how the dielectric is
74

able to reduce B,eff. Despite of efforts by several research groups, there is still no complete understanding of how these MIS contacts work. Two possible explanations for the observed reduction in B,eff have been reported in the Si and Ge MIS contact literature, but there has not been a clear consensus. The explanations are heavily dependent upon the chosen Fermi level pinning theory, where the origin of the pinning varies with the model. The two considered here are the metal induced gap states (MIGS) and bond polarization theories. Studying how these theories can explain the MIS contact behavior will allow us to gain a better in depth understanding of the underlying mechanism.

5.2 Fermi-level Pinning Theories

According to the Schottky-Mott theory [67], when a metal and semiconductor are brought into contact, the two Fermi levels align so the semiconductor Fermi level at the interface is modified. The potential barrier B between the two should ideally be set by the metal work function M and semiconductor electron affinity e, where B = M e for an n-type semiconductor. However, in reality, this dependence is not experimentally observed. Schottky barrier heights tend to be pinned at a value roughly independent of M.

ND = 1 x 1016 cm-3

0.3 eV

3 eV

Figure 5.1. Experimentally measured Schottky barrier heights on n-GaAs for different metal work functions. The metal/GaAs interface appears strongly pinned. Figure from Ref# [4].
75

As illustrated in Figure 5.1 from the experimentally measured Schottky barrier heights vs. metal workfunction plot, the metal/GaAs Fermi level is strongly pinned between 0.7 and 0.9 eV. Even though M varies by 3eV, the barrier height only varies by 0.3 eV, indicating the barrier height is almost independent of the metal workfunction. Currently, there exists several Fermi level pinning theories, where the origin of the pinning states varies with the model. Two popular theories are the metal induced gap states (MIGS) and bond polarization theories.

5.2.1 Metal Induced Gap States Theory

The MIGS theory was first proposed by Heine [68] in 1965, and later supported by Tersoff [69]. The basis of this theory is that the tail of the electron wave functions from the metal can decay into the semiconductor in the forbidden band gap energy range, creating intrinsic states known as the metal-induced gap states. Near the valence band, these states are found to be mostly donor-like, and near the conduction band they are mostly acceptor-like. The charge neutrality level (ECNL) is then the energy level at which the interface states change from mostly donor-like to acceptor-like. In a metal/semiconductor junction, the charging of these states by the penetrating electron wave function from the metal creates a dipole charge which causes the Fermi level to align to minimize the dipole charge towards zero, effectively pulling the EF at the interface towards ECNL. For example, if the metal EFM is initially above ECNL, then as they are brought into contact a dipole with a negative charge on the semiconductor side would be created, as shown in Figure 5 Figure 5.2. Since filled acceptor-like interface states result in negative charges and empty donor-like interface states result in positive charges, the shaded area represents the total negative charge on the dielectric side while the light-gray region represents the total positive charge. After the metal and semiconductor are in contact, charge transfer through emptying the acceptor states or filling the donor states will proceed until the net charge is zero.

76

total positive charge (empty donor-like)

total negative charge (occupy acceptor-like)

Figure 5.2. Distribution of the metal induced gap states. The left side shows the energy band diagram and the right side shows the charging of the interface. Figures from Ref# [81].

From experimental measurements, the barrier heights of large bandgap ionic semiconductors were found to have much more dependence on M than small bandgap covalently bonded semiconductors. This was explained by the dependence of the states on the asymptotic charge decay length . Ionic semiconductors have shorter decay lengths, so there is negligible DOS away from the interface. A short decreases the ability for MIGS to screen the effect of metal electronegativity, which allows M to have some modulation of the barrier height. This dependence of the Schottky barrier height on can be modeled using a pinning factor S [82], where materials with a shorter would lead to a larger S, and vice versa. S is empirically found to be inversely related to the dielectric constant and for 1 S 0, a smaller S indicates stronger pinning. As shown in Figure 5.3, semiconductors tend to have smaller S than oxides and dielectrics, which explains why there generally does not exist Fermi level pinning in metal/oxide junctions. To calculate the barrier height B, the pinning effect can be thought of as an effective barrier metal work function M,eff in contrast to the normally referenced metal work function in vacuum M. The equations are shown below:

S =

1 1 + 0.1( 1) 2

M,eff = S M + ( 1 S ) CNL B = M,eff e

77

(a)

(b)

Figure 5.3. (a) Illustration of the relation between S and . (b) The pinning factor S ranges from 0 to 1. The slopes show that a smaller S leads to a higher degree of pinning of EF to ECNL. Figures from Ref# [81].

5.2.2 Bond Polarization Theory

Tungs bond polarization theory [70] is similar to the MIGS theory in the idea of gap states being the source of Fermi level pinning. The difference in Tungs theory from the MIGS theory is in the idea that the gap states arise from the bond polarization of the chemical bonds at the metal semiconductor interface, while in MIGS, it is assumed that the distribution of gap states is determined entirely by the semiconductor with no dependence on the metal. In actuality, there must be a rearrangement of charge in forming the chemical bonds between the metal and semiconductor in order to satisfy thermodynamics and the minimization of interface energy. When a semiconductor comes into contact with a metal, the two wavefunctions interact, forming new wavefunctions at the interface where the electronic states are not fully metal or semiconductor-like, but rather a mixture of the two. This transition layer or interface specific region (ISR) is illustrated in Figure 5.4. The width of the ISR is dependent upon the screening length which is usually a few lattice spacings. An assumption of this model is that charge transfer is limited only to atoms on the immediate interface planes. However, in reality, there is some additional chemical shift due to the second and third neighboring planes, but it is smaller in comparison with the first neighboring plane.
78

Metal

Semiconductor

Interface Specific Region (ISR)

Figure 5.4. Energy band diagram and crystal potential distribution at a metalsemiconductor interface, illustrating the concept of the interface specific region. Figure from Ref#[70].

When in contact, minimization of the total interface energy causes the metal and semiconductor charge density to relax, creating an interface dipole that pins the Fermi level. Looking more closely at ISR in Figure 5.4, M represents the internal chemical potential of the metal, and S represents the internal ionization energy of the semiconductor, both internal bulk properties. The interface dipole is represented by eISR, which is the difference between the averaged potential across the interface. The Schottky barrier height is related through B,p = EFINT - EVBINT = M S eISR .

5.3 Fermi-Level Depinning vs. Shifting

When we apply these two Fermi level pinning theories to the MIS contact, each theory has a different effect on the Fermi level. These two differ mainly in the choice of the ideal dielectric material, how you form ohmic contacts to n-type and p-type semiconductors, and how the metal work function affects the MIS barrier height. In accordance with the MIGS theory, by inserting a thin insulator between metal and semiconductor, the metal electron wave function is attenuated in the insulator prior to penetrating into the semiconductor. This would result in fewer charges available to drive the interface EF towards ECNL, which unpins the Fermi as shown in Figure 5.5. This
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reasoning was used to explain the observed depinning of metal/Si [66] and metal/Ge Fermi levels [71, 72]. The ideal dielectric would be: (1) sufficiently thick to allow the wavefunction to decay, (2) have a large pinning factor S=1 to be more effective in depinning the Fermi level and to minimizing potential pinning of the metal/insulator, and (3) have EC = 0 to eliminate the tunneling penalty of the dielectric. From the bond polarization theory, by inserting a thin insulator an electronic dielectric dipole is created between the insulator and the semiconductor or native oxide that induces a barrier shift (Figure 5.5) that shifts the Fermi level. This dipole can be visualized as modifying the effective metal work function (M,eff) and the interface specific region, where for a given semiconductor the magnitude of the dipole effect depends mainly on the insulator material. The ideal insulator for n-type ohmic contact applications would be one that forms: (1) a large positive dipole equal to the pinned B, and (2) has EC = 0 to reduce the tunneling penalty on RC.

(a)
Pinned Fermi level

(b)
Unpinned Fermi level by MIGS reduction

(c)
Shifted Fermi level by dipole formation
Tunneling Current

B
EC EF

B,eff
+-

EC

Metal
EV

EV

Semiconductor

Metal

Semiconductor
Insulator

Figure 5.5. Schematic band diagrams: (a) Schottky barrier with a pinned Fermi level, (b) Fermi level umpinning through MIGS reduction, (c) Fermi level shifting through dipole formation at the interface

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The MIS contact behaviors under the two theories differ in how the ohmic contacts to n-type and p-type semiconductors are made (Table 5.1). In the case of Fermilevel depinning, the same dielectric that unpins the Fermi level would be used, followed by low M metals such as Al and Ti for n-type contacts to tune the barrier height towards 0, and high M metals such as Au and Pt for p-type contacts. n the case of Fermi-level shifting, the metal work function is not as critical. Instead, the dielectric properties are more important in creating n-type and p-type contacts. Different dielectrics are needed to create dipoles pointing to opposite directions to either shift the Fermi level towards the conduction or valence bands.
Fermi-Level Depinning
Theory Ohmic contact for n-type and p-type n-type p-type Effect of M on
B,eff

Fermi-Level Shifting
Bond Polarization Same metal, different dielectric. Dielectrics that shift E towards E
F F C V

MIGS Different metal, same dielectric. Low WF metals (Al, Ti) High WF metals (Au, Pt)
B,eff

Dielectrics that shift E towards E Roughly constant change in

is modulated by the

metal workfunction.

that is independent of the metal.

B,eff

Table 5.1. Summary of how Fermi level depinning and shifting affect the MIS contact behavior.

To test the MIGS Fermi level depinning theory, p-type MIS contacts are fabricated using high M metal Pt with dielectrics known to reduce B,eff in n-type MIS contacts. Figure 5.6 shows the Rc vs. insulator thickness plot for Pt/TiO2/p-GaAs and Pt/HfO2/p-GaAs MIS contacts. Unlike the n-type MIS contacts, RC only continuously increases with insulator thickness which indicates there is no reduction in the barrier height. If there were a B,eff reduction, there would be a decrease in RC resulting in an optimal insulator thickness. Since Pt with a high M near the GaAs valence band edge was used, the surface does not appear to be unpinned. Although the difference in EC amd EV could be a factor, it is possible that there is a dipole created at the dielectric/semiconductor interface that shifts the Fermi level towards the conduction band. This can explain the favorable n-type and unfavorable results on p-type MIS contacts.
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1.E+05

ContactResistanceRatio

Pt/TiO2/pGaAs Pt/HfO2/pGaAs

1.E+04 1.E+03 1.E+02 1.E+01 1.E+00 0 0.5 1 1.5 2 2.5

DielectricThickness(nm)
Figure 5.6. P-type MIS contacts do not reduce B,eff, suggesting the Fermi level is shifted towards the conduction band by the dielectrics, rather than depinned.

To further investigate the differences between the two theories, the effect of the metal work function on the effective barrier height is studied. If the Fermi-level is depinned, then the MIS B.eff should be tuned by M through the relation B,eff = M - e,. On the other hand, if the Fermi-level is shifted in the MIS contact, then there would be a roughly constant change in the Schottky barrier and B,eff that is independent of M. To study this, metal/SiN/n-GaAs MIS using Y (M = 3.1eV), Er (M = 3.1eV), Al(M = 4.1eV), Ti(M = 4.3eV), and W (M = 4.5eV) were fabricated, and the effective barrier heights measured as described in the previous chapter. Figure 5.7 plots the measured barrier height vs. metal work function for the Schottky and MIS contacts. The B,eff reduction appears to be roughly 0.4eV to 0.5eV for all samples independent of the pinned B and M used, which agrees with the expectation of a constant dipole magnitude that is independent of the metal, and only dependent upon the insulator/semiconductor interface properties. The shift for Er and Y metals is slightly greater at 0.51eV, but this may be due to the high reactivity of the metals, where possible oxidation may alter the interface. It is important to note that despite a reduction in B,eff, the surface is still strongly pinned since M varies by 1.5eV but B,eff only changes by 0.2eV. The surface is now pinned at a location closer to the conduction band.

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1.2
Barrier Height (eV)

1.0 0.8 0.6 0.4 0.2 0.0

Y, Er

Metal/nGaAsSchottkyDiode Metal/SiN/nGaAs

0.38 eV 0.51 eV 0.40 eV 0.41 eV

W Ti

Al

3.5 4 4.5 Metal Work Function (eV)

Figure 5.7. The roughly parallel shift in B,eff independent of M confirms the dielectric dipole induced shift of roughly 0.4 to 0.5eV.

The extracted B,eff for different M do suggest the formation of an electric dipole, and this dipole could arise from differences in oxygen density as reported in Si MIS [75]. For the sputtered SiN on GaAs, the structure is more accurately represented by metal/SiON/native oxide/GaAs. Through XPS, the SiN film was found to contain roughly 15% oxygen due to the residual oxygen present in the chamber and in the Ar/N2 gases used in sputtering. The sulfur passivation may lead to a reduction of the oxygen density at the direct interface, in which case differences in the oxygen density can lead to charge transfer from SiON to the GaAs native oxide, creating the observed positive dipole. However, the similarity in the reduction of B,eff in Al/Al2O3/GaAs and Al/SiON/native oxide/GaAs structures despite very different interfaces suggests a possible alternative mechanism. ALD Al2O3 has been found to have a self-cleaning effect on the III-V native oxide where As2O3 and GaO are removed through a ligand exchange process, so very minimal native oxide remains at the Al2O3/GaAs interface [43]. The same is true for ALD HfO2 on GaAs. In contrast, sputtered SiN most likely leaves the surface with native oxide and some sputtering damage. ALD TiO2, ZrO2, and ZnO may have surfaces in between the two cases. For these dissimilar interfaces essentially with and without oxygen to have the same positive dipole, both need transfer of oxygen atoms from the dielectric to GaAs or native oxide. The considerably different interfaces therefore suggests that there may be another reason for the observed B,eff reduction.
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5.4 Fixed Charge

Even though the MIS contact behavior appears to be due to Fermi-level shifting, the exact origin of this shift in Fermi level is not well understood. A dipole at the dielectric/semiconductor interface is a possibility, but from the bond polarization theory, the dipole should only be created at the interface and determined by only a few atomic planes. If the dipole is determined by a few layers of material, then the optimal thicknesses should be much smaller than the experimentally found 2nm. Furthermore, the MIS contacts behavior appears to be independent of the different pre-ALD surface passivation (Figure 5.8). Al/TiO2/n-GaAs MIS fabricated using ammonium hydroxide and ammonium sulfide surface passivation have very different interface properties, yet they display nearly the same RC vs. insulator thickness tradeoff. (NH4)2S passivation leaves the surface As rich and with Ga-S termination [27], while NH4OH leaves the surface fairly stoichiometric. If the Fermi level shifting were due to only a dipole at the interface, then the interface properties should have a large effect on the dipole magnitude, barrier height reduction, and contact resistance.

ContactResistanceRatio

100 101 102 103 104 105

0 1

Al/TiO2/nGaAs
250CNH42S (NH4)2S Passivation NH4OHPassivation 250NH4OH

TiO2 Thickness(nm)
Figure 5.8. The RC vs. TiO2 thickness tradeoff plot for Al/TiO2/n-GaAs MIS contacts appears to be independent of the surface passivations.

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The combined reasoning of : (1) optimal thickness more than a few atomic planes, (2) similar behavior of MIS with different dielectric/semiconductor interfaces, and (3) barrier height reduction independent of native oxide presence all suggest that dipole formation at the dielectric/semiconductor interface cannot be the sole reason for the Fermi level shift. This implies there is another element that has not yet been considered. From the material properties studied in Chapter 2, the ALD dielectrics were mostly found to be non-stoichiometric throughout the film. In the case of Al2O3, instead of the ideal crystalline O to Al ratio of 1.5, the ratio was measured to be 1.82 with 35.4% Al 2p and 64.6% O 1s atomic concentrations. The film density of 3.04 g/cm3 is also significantly lower than the reported 3.9 g/cm3 of bulk crystalline Al2O3 [83]. As with the stoichiometry and density, the measured bandgap of 6.4eV is also smaller than the ideal crystalline value [38] of 8.7eV. These structural non-idealities can affect the electrical properties of the film through the presence of defects that leave the film oxygen rich and electrically behave as fixed charge. It seems that the dielectric properties itself can be an important factor. Since it is not possible to extract QF in ultrathin MIS, MOSCAPs with thicker dielectric were used as a vehicle to extract these values. To investigate the electrical non-idealities caused by fixed charge present at the insulator-semiconductor interface and inside the film, C-V characteristics of as-deposited Pt/Al2O3/n-InGaAs MOSCAPs with 50, 75, and 100 cycles of ALD Al2O3 were measured in Chapter 3. Fixed charge densities were extracted from the VFB dependence on oxide thickness. As deposited ALD film had a significant amount of positive bulk fixed charge (QF = 1.9x1019 cm-3), and after FGA annealing at 300oC for 30min, the dangling bonds were passivated and the fixed charges were minimized (QF = 4.1x1018 cm-3). To understand how the positive fixed charge in the oxide would affect the MIS contacts, Al/Al2O3/GaAs MIS were also annealed in FGA to remove QF. Al metal spiking through the ultrathin Al2O3 was a concern, but it didnt appear to be an issue. If there were metal spiking, the contacts would have a Schottky behavior independent of the Al2O3 thickness, but a dependence on the thickness was observed. Figure 5.9 illustrates how the RC vs. Al2O3 thickness tradeoff changed after annealing. As deposited, there

85

exists an optimal thickness for minimal RC which indicates a reduction in B,eff. After FGA, the MIS contact behavior changed entirely. There is no longer a decrease in RC which implies that there is also no reduction of B,eff in the annealed MIS. The monotonic increase of RC after annealing is due to the tunneling limitation the oxide imposes on the current conduction, but the slope of the tunneling resistance limited branch in the RC trade-off appears less steep after annealing. This is possibly due to a change in the tunneling barrier either by changes in the band structure or densification of the film. The presence of fixed charge appears to be responsible for the observed reduction in the barrier height using ultrathin insulators.

ContactResistanceRatio

(a)

103 102 101 100 101 102 103 0.0

FGAAnnealed

AsDeposited
0.5 1.0 1.5 2.0

Al2O3 Thickness(nm)

(b)
|Current|[A/cm2]

1000 10
-2

10 10-2

As Deposited 10 Al2O3 As Deposited Schottky FGA 300oC 10 Al2O3

10 10-4

-4

10 10-6

-6

10 10-8

-8

-1

-1

-0.5

-0.5

Voltage[V]
Figure 5.9. After removing the positive fixed charge in Al/Al2O3/n-GaAs MIS by annealing in FGA at 300oC for 15 min (a) there is no longer a reduced barrier height so the tunneling resistance branch dominates, and (b) the current decreases.
86

0 Voltage [V]

0.5

0.5

To verify the effect of QF, MIS contacts were fabricated using different ALD Al2O3 deposition temperatures, where lower temperature film results in more positive fixed charge [84]. In comparing the 250oC and 300oC samples (Figure 5.10), the 250oC film with higher QF achieved an overall lower RC. This further supports the idea of QF modulating the barrier height on the semiconductor side. However, it is unlikely that all the observed MIS contact behavior is due to positive/negative bulk or interface fixed charge since materials can have a wide range of defects and impurities.
100 ContactResistanceRatio

101

102

T=300oC LessFixedCharge T=250oC MoreFixedCharge

103 0.0 0.5 1.0 1.5 2.0 2.5 Al2O3 Thickness(nm) Figure 5.10. Al/Al2O3/n-GaAs RC vs. tINS comparing samples with ALD deposition temperatures of 250 and 300oC. The lower RC in the 250oC sample with more fixed charge further verifies the importance of positive QF in the B,eff reduction.

For example, in the case of HfO2, the flatband voltage of as-deposited MOSCAP C-Vs with different oxide thicknesses are aligned (Figure 5.11a), which shows a minimal amount of fixed charge is present in the HfO2 film. However, after annealing the Al/HfO2/GaAs MIS in FGA, there is also a sharp increase in RC (Figure 5.11b) even though there is no significant amount of fixed charge to be removed by the FGA. From the MOSCAP studies in Chapter 2, FGA reduces not only QF but also DIT. In the case of MIS, during FGA annealing, hydrogen could also be passivating the dangling bonds at the dielectric/semiconductor interface which would change or remove the interface dipole. The overall mechanism of MIS contacts seems to be a combination of fixed charge and dipoles, dependent upon the specific dielectric material used.
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(a)
Capacitance / Cmax

1 Pt / HfO2/InGaAs 0.8 MOSCAP

As Deposited

0.6 7.5 nm 10 nm 12.5 nm -2 0 2 4

0.4

0.2 -4

Voltage

ContactResistanceRatio

(b)

103 102 101 100 101 102 103 0

FGA300oC

AsDeposited Al/HfO2 /nGaAs

1 2 3 DielectricThickness(nm)

Figure 5.11. (a) Pt/HfO2/InGaAs MOSCAP C-Vs for different oxide thicknesses. The VFB does not have a thickness dependent shift so there should be minimal amount of fixed charge in the film. (b) After annealing in FGA at 300oC for 15 min, the Al/HfO2/n-GaAs MIS contact resistance increased greatly.

Band diagrams are used to illustrate the overall effect of dipoles and fixed charge on Schottky (Figure 5.12a) and MIS contacts (Figure 5.12b). The current reported MIS interface dipole models [75, 85] can explain the observed reduction in B,eff by modeling the dipoles as changes in the vacuum level (Figure 5.12c), where in the case of extremely large dipole magnitudes the surface will be in accumulation (Figure 5.12d). However, this same effect on B,eff can also be achieved using positive fixed charge to increase the amount of potential that is dropped across the insulator to reduce the semiconductor
88

(a) Schottky Barrier

(b) MIS Contact

(c) Small Dipole

(d) Large Dipole

EVAC

+ ++ B +++ ++ +

++ ++ ++++

EC EF EV

B,eff

+ ++++ + +++ +

B,eff

+-

+++ ++

B,eff +-

(e) Small Fixed Charge

(f) Large Fixed Charge

(g) Moderate Charge + Dipole

B,eff + + +
+ + + +

+++

B,eff

+ + + + + + + + + + + +

B,eff

+ + + + + + ++ + + + + + +

Figure 5.12. Schematic band diagrams illustrating how the presence of electronic dipoles and fixed charge can affect B,eff. (a) A Schottky barrier with a large depletion width in the semiconductor. (b) In the MIS structure, some of the potential is dropped across the insulator, which reduces the depletion width and semiconductor barrier height. (c) A small electronic dipole at the insulator/semiconductor interface can cause a change in the vacuum level. (d) A larger dipole can in fact push the semiconductor surface to be in accumulation. (e) With fixed charge in the oxide, more potential is dropped across the insulator and the barrier height is reduced. (f) A larger amount of fixed charge amplifies the effect and can induce negative charge in the semiconductor. (g) If both fixed charge and interface dipole are present, then there is a further reduction in B,eff.

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depletion charge (Figure 5.12e). In the case of extremely large amount of positive fixed charge, the effect is amplified and electrons can be induced to the surface, bringing the semiconductor into accumulation (Figure 5.12f). For the cases of large dipole or large fixed charge where the surface is in accumulation, the tunneling distance through the semiconductor is greatly reduced from the Schottky barrier case, particularly for low doped substrates. Depending on the depletion width and Schottky barrier height, by reducing the tunneling distance through the semiconductor, the tunneling penalty through the insulator is reduced, which further increases the overall current and decreases RC. From the known non-idealities in the dielectric, the Al/Al2O3/GaAs MIS behavior appears to be due to the presence of QF, whereas the Al/HfO2/GaAs MIS behavior is due to dipole formation. The situation for other dielectrics is unclear as each material needs to be studied in detail. The overall effect of dipoles and fixed charge can be additively or subtractively combined, depending on the direction of the dipole and the sign of QF, so the MIS behavior can also be due to a combination of the two (Figure 5.12g).

5.5 Discussion
In efforts to elucidate the B,eff reduction, the MIS contact has been modeled and compared with reported experimental results [86, 87]. Lin et. al modeled the mechanism as a combination of Fermi level depinning and the presence of an interfacial dipole due to polar/non-polar surfaces [86], and Wagner et al. used the MIGS theory to model two dipoles at both the metal/insulator and insulator/semiconductor interfaces [87]. These explanations can provide the basis for an initial understanding of the experimental observations, but the dielectrics in these theoretical works were assumed to be ideal, crystalline structures. In reality, as illustrated in this chapter, these dielectrics are nonideal, non-stoichiometric amorphous materials that could have a significant amount of defects and impurities. These structural non-idealities of the film: oxygen rich stoichiometry, low density, and smaller bandgap indicate that the material properties are difficult to model, whereby use of the ideal crystalline properties may result in very different electrical behavior of MIS contacts.

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5.6 Summary
We investigated how the two Fermi level pinning theories would affect MIS contacts. Under the MIGS theory the Fermi level would be unpinned by the MIS, and under the bond polarization theory the Fermi level would be shifted by the creation of an interface dipole. Looking at n-type versus p-type MIS contacts, it was discovered that the lack of a barrier height reduction in p-type contacts could be due to a shift in the Fermi level towards the conduction band. Fermi level shifting was further confirmed through a study of MIS B,eff vs. M where inserting the ultrathin dielectrics reduced the barrier heights by a constant amount across all M, so B,eff was not tuned by M. Across all the studied dielectrics, the presence of native oxide or use of different surface passivations did not seem to affect the MIS contact behavior, alluding to a missing factor. After evaluating the physical non-idealities of the ALD Al2O3 film through stoichiometry, density, and bandgap measurements, the structural non-idealities were found to electrically manifest as bulk and interface fixed charges that contribute to the observed barrier height reduction. The effect of fixed charge has not been considered before and combined with interface dipoles provides a more thorough understanding of the MIS contacts. Though this study was based on III-V MIS, the results can be extended to the understanding of Si and Ge MIS contacts.

5.7 Future Work

To better understand the underlying mechanisms behind the barrier height reduction in MIS, further materials characterization of dielectrics would be helpful to understand which MIS are dominated by fixed charge and which are dominated by electronic dipoles. A thorough study of the effect of the deposition temperature for different dielectrics on MIS and MOSCAPS for the different dielectrics would also be helpful in quantifying and distinguishing between bulk and interface fixed charges. The exact origin of the dielectric/semiconductor dipole is still unknown, and study of the interface dipoles in GaAs MOSCAPs can assist in the understanding.

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In this chapter, the effect of thermal annealing on MIS was studied for the first time. These results show that FGA annealing which is commonly used in CMOS fabrication to improve the gate stack can drastically increase the RC of MIS contacts. This can potentially limit the application of MIS contacts to MOSFETs, so a more detailed study of the allowed thermal budget is necessary in order to understand how these contacts could be integrated into CMOS. Also, a thermal annealing study of a wider range of dielectrics could be helpful in finding if there are any dielectrics where the contact resistance reduces with annealing.

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Chapter 6 Bilayer Dielectric MIS Contacts

In this chapter, we expand on the previous chapters use of single dielectric MIS contacts to include bilayer dielectric MIS to continue to shift the Fermi level and to reduce the contact resistance. ALD HfO2, Al2O3, TiO2, and ZrO2 are chosen to form the bilayer high dielectric stacks. In studying high-/high- interfaces, we find that despite a thicker dielectric, there is further reduction in B,eff beyond that of a single dielectric, which can be explained by the formation of a high-/high- dipole. This MIS structure provides great flexibility in the design of source/drain contacts for III-V transistors.

6.1 Introduction
The single dielectric MIS has been investigatred in the previous chapter to alleviate the metal/semiconductor Fermi level pinning on Ge [71-74], GaAs [85], InGaAs [85, 88], and GaSb [89] using a variety of high- dielectrics. More recently, Coss et al.[75] used bilayer dielectrics AlOx/SiOx and LaOx/SiOx to shift the Fermi level towards the valence band and conduction band to reduce the metal/n-Si and metal/p-Si effective barrier heights (Figure 6.1). The authors explained this was due to electronic dipole formation between the high- and SiO2, where the AlOx/SiOx and LaOx/SiOx form dipoles pointing in opposiite directions. These bilayer MIS contacts were integrated on FinFETs as a single metal dual dipole source/drain contacts for NMOS and PMOS. From the ID-VD curves the samples with the MIS contacts had much higher current indicating lower contact resistance than the control contacts without dielectrics. The use of bilayer dielectrics to create electronic dipoles to further shift the Fermi level pinning seems
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promising is obtaining ohmic contacts. Prior to this work, the use of bilayer dielectrics had not been studied on III-V semiconductors.

(a)

TaN LaOx SiO2 Si

10 - 20 10

TaN AlOx SiO2 Si

(c)

Evacuum SBH TaN p-Si dtunneling AlOx SiO2 EC EF EV

m,eff

(b)

(d)

Figure 6.1. (a) Schematic of the investigated bilayer dielectrics. (b) Illustration of how the high-/SiO2 dipoles affect the band alignments. (c) Extracted barrier heights for varying dielectric thicknesses show the Si Fermi level is tuned towards the conduction and valence bands. (d) ID-VD of FinFETs comparing the effect of MIS and the control contacts. The lower contact resistance of the MIS translates into higher drive current. Figures are from Reference#[75].

6.2 Background
Electronic dipoles at high-/SiO2 were first discovered when high- dielectrics were integrated into the Si CMOS gate stack to scale down the effective oxide thickness while increasing the physical thickness to reduce gate tunneling leakage [90-92]. Since high- materials do not passivate the Si surface and inevitably form a SiO2 interfacial layer after thermal processing, high-/SiO2 bilayer dielectrics are typically used for the gate stack. In studying the use of different high- materials, it was observed that there were uncontrollable flatband and threshold voltage shifts that would affect the CMOS operating voltages [91, 93, 94]. These VFB shifts were present for a wide range of high-

94

dielectrics, and found to arise from the high-/SiO2 interface itself rather than from the bulk of the high-k material [95]. As shown in Figure 6.2a, when the SiO2 thickness is fixed and the high- GeO2 thickness varied, the VFB shift occurs when the GeO2 is first introduced and did not change with further increase in the GeO2 thickness, indicating the VFB shift is not due to fixed charges in the GeO2. In performing a survey of materials, Kita et al. [96] noticed that the high- materials that resulted in a positive VFB shift were ones that had a greater oxygen density than SiO2 (Figure 6.2b). The reverse was also true, where materials with a lower oxygen areal density resulted in a negative VFB shift. The idea of oxygen areal density () comes from the volume difference in the oxide molecules, where different volumes lead to differences in the areal density of the oxygen. The number of oxygen atoms per unit area is approximated by Vu-2/3 where Vu is defined as the volume of the structure containing a single oxygen atom. Differences at the high/SiO2 interface can drive an equalization of where the oxygen atom from the higher density material moves to the lower density material, leaving behind a positively charged oxygen vacancy and a dipole that shifts the MOSCAP VFB (Figure 6.2c).

(a)

(b)

(c)

Figure 6.2. (a) C-V of MOSCAPs with and without high- GeO2. A constant VFB shift was observed regardless of the GeO2 thickness, implying the shift is due to a dipole at the GeO2/SiO2 interface rather than fixed charge in the GeO2. (b) Survey of high- materials and their corresponding VFB shifts. (c) Illustration of the equalization of the oxygen areal density through oxygen transfer at the interface and dipole formation. Figures are from Reference#[95].
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However, despite electronic dipoles being formed at high-/SiO2 due to differences in , researchers found there was no dipole present at high-/high- interfaces even though there are also differences in [91, 92]. To pinpoint the location of the dipole, trilayer high-/high-/SiO2 gate stacks were fabricated, and the thicknesses of the two high- layers were separately modified to see the effect on VFB (Figure 6.3). No VFB shift was observed in changing the thickness of the upper high- in contact with the gate electrode (blue line), and a VFB shift was only observed when the thickness of the lower high- in contact with the SiO2 was changed (red line). Fixed charge was eliminated as a reason for the VFB changes because if fixed charge were responsible, as the dielectric thickness is increased and more fixed charge is incorporated in the film, there would be a more significant effect on VFB. From these findings it was concluded that electronic dipoles only exist at high-/SiO2 interfaces. This was true for the A12O3/HfO2/SiO2 [91],
HfO2/Y2O3/SiO2 [91], and HfO2/Al2O3/SiO2 [91, 92] material systems.

It was concluded that there are no dipoles at high-/high- interfaces, but this appears to contradict their reasoning of dipole formation by differences in the oxygen areal density. Their results may be unique to the particular material systems studied, so to investigate this, we studied the properties of bilayer MIS to see if it is possible form dipoles at high-/high- interfaces to further shift the Fermi level and to minimize B,eff.

(a)

(b)

Figure 6.3. (a) VFB shift of NiSi/A12O3/HfO2/SiO2/Si MOSCAPs with varying dielectric thicknesses. The blue line indicates the effect of change the bottom high dielectric, and the red shows the effect of changing the upper high- thickness. (b) VFB shift of NiSi/HfO2/Y2O3/SiO2/Si MOSCAPs. Figures are from Reference#[91].
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6.3 Device Fabrication

The high-/high- bilayer MIS contacts were fabricated in the same way as the single dielectric MIS contacts. We used lightly doped (2x1016cm-3) MBE grown n-GaAs to emphasize the thermionic emission current over the barrier and to more accurately extract barrier height values. The samples underwent an organics degrease by sonication in a 1:1 acetone and methanol solution, followed by rinsing in deionized (DI) water for 1 minute. The native oxide was then removed by soaking the samples in a dilute HCl solution (1:1 = DI water : 29% HCl) for 3 minutes, followed by a 20sec DI water rinse with agitation. Immediately after the rinsing step the samples were immersed in 5% ammonium sulfide (NH4)2S solution for sulfur passivation. After 15min the samples were removed and rinsed well in DI water and dried by nitrogen gun and immediately loaded into the ALD chamber to minimize native oxide formation. The bilayer ALD films were deposited in the Cambridge Nanotech Savannah ALD using standard pulse and purge times. Table 6.1 summarizes the precursors used and the deposition temperature. The deposition temperatures were mostly higher than in the standard recipe for higher quality, denser films. The maximum temperature of 250oC was used in most cases, except for ZrO2 and ZnO were at higher temperatures the precursors would no longer adsorb well on the sample surface. To minimize GaAs native oxide formation, the metal organic precursor was used as the starting pulse, to follow with the self-cleaning[43] observed in Al2O3 and HfO2. For the bilayer dielectrics, the two ALD materials are deposited in-situ without breaking vacuum. After the ALD deposition, the samples were loaded into the shadow mask holders and the diodes were defined by 150nm Al metal evaporation in Innotec. When the front metal is finished, the shadow mask holders were flipped and the backside of the samples were lightly scratched using a diamond scriber in crosshatch patterns to remove the native oxide immediately prior to loading the samples for the 50nm Ti + 150nm Au back contact deposition in Innotec.

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Film Al2O3 TiO2 HfO2 ZrO2 ZnO

Metal Precursors TMA TDMAT TDMAH TEMAZ DEZn

ALD Reaction (CH3)3 Al + H2O [(CH3) 2N]4 Ti + H2O [(CH3) 2N] Hf + H2O (CH3C2H5)4 Zr + H2O (C2H5) 2Zn + H2O

Temp. 250oC 250oC 250oC 200oC 160oC

Table 6.1. Summary of the ALD precursors and deposition temperature.

6.4 Electrical Characterization

6.4.1 Diode Current
For the bilayer MIS, TiO2 is chosen as the bottom dielectric layer in most of the investigated samples because it achieved the lowest RC in the single dielectric MIS contact. The low RC is most likely due to the combination of a large dipole magnitude and a low conduction band offset for minimal penalty of tunneling through the dielectric. TiO2/Al2O3 was the first bilayer dielectric stack investigated because it had the largest difference in the calculated oxygen areal densities (Figure 6.2B). As a starting point, the TiO2 thickness was first held constant at 13 (30cy of ALD), and the Al2O3 was varied between 0 and 20. Figure 6.4 summarizes the measured Al/Al2O3/TiO2/nGaAs MIS diode currents. In comparison with the single dielectric Al/13 TiO2/n-GaAs MIS diode, by adding Al2O3 to the dielectric stack there was a continuous increase in the reverse current with 3 to 7 Al2O3. This indicates there is an additional B,eff reduction beyond that introduced at the TiO2/n-GaAs interface, because otherwise the addition of Al2O3 should only reduce the current. This result is counter-intuitive in that adding a larger bandgap insulator for an overall thicker dielectric can actually increase the current by more than an order of magnitude and reduce B,eff. However, this can be explained by the presence of dipoles similar to those found in the Si bilayer MIS contacts that further shift the Fermi level. This TiO2/Al2O3 dipole would have to point in the same direction as
98

that of the dielectric/semiconductor interface dipole in single dielectric MIS. When the Al2O3 thickness is increased beyond 7, the current eventually becomes limited by the tunneling current through the dielectric, and the reverse current decreases. This current tradeoff with the Al2O3 thickness is similar to that of the single dielectric MIS contacts, which further suggests a same underlying mechanism. To find the optimal thickness for maximum current and minimal contact resistance, the Al2O3 thickness was held constant at 7 (7cy of ALD) and the TiO2 was varied between 6.5 and 30 (15 to 70cy of ALD). From the measured diode current shown in Figure 6.5, the current continually increased for 6 to 13 and decreased for 13 to 30 of TiO2. This continuous trend demonstrates that the dependence of the current on the ALD thickness is consistent and strengthens the credibility of the data. The overall optimal thickness was found to be 13 TiO2 and 7 Al2O3.

10

Al Al 2O3 TiO2

Current (A/cm )

10

-2

Add Al2O3

13 TiO

2 2 2 2 2 2 2 2 3 2 3 2 3 2 3

GaAs

13 TiO + 3 Al O 13 TiO + 5 Al O

10

-4

13 TiO + 7 Al O

Add TiO2
-6

13 TiO + 10 Al O 13 TiO +15 Al O

2 2

B,eff Al
++-

Tunneling Current

3 3

10

13 TiO + 20 Al O Al Schottky

n-GaAs TiO2

-1

-0.5

Voltage (V)

0.5

Al2O3

Figure 6.4. MIS diode current of Al/TiO2/n-GaAs and Al/Al2O3/TiO2/n-GaAs with a constant 13 TiO2 thickness. The increase in both the forward and reverse currents with the addition of larger bandgap material Al2O3 is counter intuitive and indicates a further reduction in B.eff beyond that achieved by the TiO2 single dielectric MIS.

99

10

10

|Current| (A/cm2)

10

-2

10 Thicker TiO2

-2

Thicker TiO2
TiO2 60cy + Al2O3 7cy

10

-4

TiO2 30cy + Al2O3 7cy TiO2 25cy + Al2O3 7cy TiO2 15cy + Al2O3 7cy Al2O3 7cy Al Schottky

10

-4

TiO2 70cy + Al2O3 7cy TiO2 50cy + Al2O3 7cy TiO2 40cy + Al2O3 7cy TiO2 30cy + Al2O3 7cy Al Schottky

10

-6

10 1

-6

-1

-0.5

0.5

-1

-0.5

0.5

Voltage (V)

Voltage (V)

Figure 6.5. Al/Al2O3/TiO2/n-GaAs MIS diode current with a constant 7 Al2O3

thickness and varying TiO2 thickness. The optimal TiO2 thickness for maximum current is 13 or 30cycles of ALD.

This bilayer MIS contact behavior was also found in TiO2/HfO2 (Figure 6.6) and TiO2/ZrO2 (Figure 6.7) dielectric stacks, suggesting that there is a dipole present at multiple TiO2/high- interfaces. For a constant 13 TiO2, the corresponding optimal thicknesses for maximum current were 8.5 HfO2 (10cy) and 16 ZrO2 (20cy).

10

10

|Current| (A/cm2)

10

-2

Thicker HfO2
Al Schottky TiO2 30cy TiO2 30cy + HfO2 5cy TiO2 30cy + HfO2 7cy

10

-2

Thicker HfO2
Al Schottky TiO2 30cy + HfO2 25cy TiO2 30cy + HfO2 20cy TiO2 30cy + HfO2 15cy TiO2 30cy + HfO2 12cy TiO2 30cy + HfO2 10cy

10

-4

10

-4

10

-6

10 TiO2 30cy + HfO2 10cy

-0.5 0 0.5 1

-6

-1

-1

-0.5

0.5

Voltage (V)

Voltage (V)

Figure 6.6. Diode current of Al/HfO2/TiO2/n-GaAs with a constant 13 TiO2 (30cy) thickness and varying HfO2 thickness. The optimal HfO2 thickness for maximum current is 8.5 or 10cycles of ALD.

100

10

Add ZrO2

Current (A/cm )

10

-2

Al Schottky TiO 30cy

2 2 2 2 2 2

Al
2 2 2 2 2

10

-4

Add TiO2

TiO 30cy + ZrO 5cy TiO 30cy + ZrO 10cy TiO 30cy + ZrO 15cy

ZrO2 TiO2 GaAs

10

-6

TiO 30cy + ZrO 20cy TiO 30cy + ZrO 25cy

-1

-0.5

Voltage (V)

0.5

Figure 6.7. Diode current of Al/ZrO2/TiO2/n-GaAs with a constant 13 TiO2 (30cy) thickness and varying ZrO2 thickness. The optimal ZrO2 thickness for maximum current is 16 or 20cycles of ALD.

In comparing the maximum achievable current using the three bilayer dielectrics (Figure 6.8.), TiO2/Al2O3 resulted in the largest reverse current, 45 times higher than the TiO2 MIS and 4 orders of magnitude greater than the Al/n-GaAs Schottky current. TiO2/ZrO2 had the smallest improvement of only 5 times over that of the TiO2 MIS.
\

10

45X

Current (A/cm )

10

-2

20X 5X

10

-4

> 4 orders of magnitude

Al Schottky 13 TiO2 13 TiO2 + 16 ZrO2 13 TiO2 + 8.5 HfO2 13 TiO2 + 7 Al2O3

10

-6

-1

-0.5

0.5

Voltage (V)
Figure 6.8. Comparison of the maximum current in Al/Al2O3/TiO2/n-GaAs, Al/HfO2/TiO2/n-GaAs and Al/ZrO2/TiO2/n-GaAs bilayer MIS at their optimal thicknesses. TiO2/Al2O3 resulted in the largest reverse current.
101

6.4.2 Contact Resistance

These contacts were further evaluated through RC measurements by modeling the bilayer MIS (Figure 6.9) as two resistances in series: a tunneling resistance through the dielectric (RT) and a resistance associated with the barrier (RSB), where there exists an optimal insulator thickness (tINS) to minimize RC. Figure 6.10 illustrates the measured contact resistance vs. dielectric thickness tradeoff of Al/Al2O3/TiO2/n-GaAs. By holding one dielectric thickness constant and varying the thickness of the other and vice versa, the optimal thicknesses for minimal contact resistance can be found. This point was 13 TiO2 + 7 Al2O3, and the values agree with the optimal point from the diode current.
Contact Resistance (log)
Barrier Height Tunneling Resistance Dominates Dominates (RT) (RSB) Optimal Thickness

RT

RSB

Insulator Thickness

Figure 6.9. Schematic of RC vs. tINS. An optimal thickness exists to minimize RC, arising from the tradeoff between a reduced barrier RSB and an increased RT.
1.0E01
ContactResistanceRatio
VaryTiO2+0.7nmAl2O3 1.3nmTiO2+VaryAl2O3

1.0E02 1.0E03 1.0E04 1.0E05 1.0E06 0

0.7nm Al2O3 1.3nm TiO2

1 2 3 DielectricThickness(nm)

Figure 6.10. Optimization of the TiO2 and Al2O3 thicknesses for minimum RC by holding on thickness constant and varying the other and vice versa.
102

In comparing the measured RC vs. tINS tradeoff of the single and bilayer MIS contacts (Figure 6.11a), it is clear that the bilayer TiO2/Al2O3 contact achieves a lower RC than both the contacts with TiO2 and Al2O3 alone, and the same is true for TiO2/HfO2 (Figure 6.11b). For a fixed 1.3nm TiO2, varying the Al2O3 or HfO2 thickness results in a RC tradeoff very similar to that of a single dielectric MIS. Again, this implies a similar underlying mechanism, with an additional contributing dipole at the TiO2/Al2O3 interface.

(a)
Contact Resistance Ratio

100 10-1 10-2 10-3 10-4 10-5 10-6 0 1 2 1.3nm TiO2

Al2O3 Al2O3 TiO2 TiO2 TiO2 + Al2O3 TiO2+Al2O3

Dielectric Thickness (nm)

Contact Resistance Ratio

(b)

101 100 10-1 10-2 10-3 10-4 10-5 10-6 0 1 2 3 1.3nm TiO2 HfO2 HfO2 TiO2 TiO2 TiO2 + HfO2 TiO2 + HfO2

Dielectric Thickness (nm)

Figure 6.11. (a) RC vs. tINS for MIS contacts using TiO2, Al2O3, and TiO2 + Al2O3. In Al/Al2O3/TiO2/n-GaAs, RC is reduced beyond that of just TiO2. Without the presence of a high-/high- dipole, adding a dielectric material should only increase RC. (b) MIS contacts with TiO2, HfO2, and TiO2 + HfO2 dielectrics show the same trends as TiO2 + Al2O3.
103

These electronic dipoles appear to be present for several high-k/high-k interfaces, since TiO2/HfO2 and TiO2/ZrO2 bilayer dielectrics also have a lower RC than their single dielectric counterparts (Figure 6.12). The TiO2/Al2O3 and TiO2/HfO2 samples performed very similarly, and this is due to the tradeoff between the dipole magnitude (RSB) and conduction band offset (RT). The TiO2/Al2O3 can have the largest dipole from having the greatest difference in oxygen areal density, but Al2O3 is also a material that has a larger bandgap and conduction band offset to TiO2. This would result in a smaller RSB but larger RT, while the TiO2/HfO2 samples would have a larger RSB but smaller RT. The exact RC tradeoff depends on the magnitude of the differences between the two samples.
1.0E+00
ContactResistanceRatio

1.0E01 1.0E02 1.0E03 1.0E04 1.0E05 1.0E06 0 1 2 3 TotalDielectricThickness(nm) 4 1.3nm TiO2

TiO2 TiO2+HfO2

TiO2+ZrO2

Figure 6.12. RC vs. tINS for MIS contacts using TiO2 + HfO2, TiO2 + ZrO2, and TiO2 + Al2O3 bilayer dielectrics.These bilayer MIS contacts result in lower Rc than their single dielectric MIS contact counterparts, which further indicates the presence of a high-/high- dipole. The absolute minimum RC is achieved by the TiO2 + Al2O3 contact.

A summary of the lowest achieved contact resistance for all of the single and bilayer dielectric MIS contacts studied is provided in Figure 6.13. Even with the addition of a larger bandgap dielectric that adds to the tunneling resistance, there is still a drastic reduction in RC over the single dielectric MIS. With the bilayer contacts, there are more material choices in the contact design, and possibly room to continue to reduce RC.

104

ContactResistanceRatio

1.0E+00 1.0E01 1.0E02 1.0E03 1.0E04 1.0E05 1.0E06 AlSiN Schottky TiO2 HfO2 Al2O3 ZrO2 TiO2 +TiO2+TiO2 + Al2O3 ZrO2 HfO2

SingleDielectricMISContact

Bilayer MISContact

Figure 6.13. Summary of minimum RC of single and bilayer MIS.

6.4.3 Effective Barrier Height

In the absence of a model that accurately depicts the behavior of the bilayer MIS contacts and captures both thermionic and tunneling currents, the thermionic emission model [32] is used to extract B,eff through diode measurements between 233 to 353 K. The extracted value is not equal to the difference in Fermi levels of the metal and semiconductor since the insulator is not accounted for, but it is representative of the electrical behavior. The effective barrier height represents MIS contacts that are electrically equal to Schottky diodes with the same B. Figure 6.14 summarizes the measured B,eff and shows the bilayer contacts achieve the best performance with the lowest B,eff, and pose a significant improvement over the single dielectric MIS contacts.
0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1
Schottky

Barrier Height (eV)

SingleDielectricMISContact

Bilayer MISContact

AlSiN Schottky SiN

Al2O3TiO2 Al2O3 TiO2

HfO2 HfO2

TiO2 +TiO + TiO2 + TiO22+ Al2O3HfO2 Al2O3 HfO2

Figure 6.14. Summary of the effective barrier height of single and bilayer MIS.

105

6.4.4 Inverted Dielectric Layers

To verify the existence of a dipole, TiO2+Al2O3 bilayer MIS were fabricated with the two dielectrics layers inverted. If fixed charge were responsible, as discovered in the single dielectric MIS, then RC of Al/TiO2/Al2O3/GaAs and Al/Al2O3/TiO2/GaAs samples would be not too different. If dipoles were responsible, then inverting the two dielectrics would flip the dipole direction and change a low resistance into a high resistance sample. Figure 6.15 illustrates the contact resistance tradeoff of the Al2O3 single dielectric (green line) and bilayer dielectric MIS (red and blue lines) with a fixed TiO2 thickness of 1.3nm and a varying Al2O3 thickness. As discussed in the previous chapter, as the Al2O3 thickness is increased, positive fixed charge begins to accumulate in the film so more potential is dropped across the dielectric and B,eff is reduced. The lower B,eff in Al/Al2O3/n-GaAs is reflected through a reduction in the contact resistance. In the case of Al/TiO2/Al2O3/GaAs, when the Al2O3 thickness is increased from 0.5 to 1nm, there is expected to be a buildup of positive fixed charge or creation of an Al2O3/GaAs dipole to lower B,eff and RC. However, the contact resistance only increases with Al2O3 thickness. This can be explained by the presence of a TiO2/Al2O3 dipole pointed in the opposite direction to cancel the benefit of Al2O3. The magnitude of this TiO2/Al2O3 dipole would have to be greater than that of the Al2O3/GaAs dipole and the fixed charge effect.

102 101

ContactResistanceRatio

100 101 102 103 104 105 106 0

1.3nmTiO2+VaryAl2O3 13TiO2 +VaryAl2O3 VaryAl2O3+ 13TiO2 VaryAl2O3+1.3nmTiO2 Al2O3Only Al2O3Only

Al TiO2 Al2O3 GaAs +

+ + + ++ ++ + Al + + + TiO2 + + Al 2O3 + + ++ + + + +

1.3nm TiO 2
Al Al2O3 + TiO2 + GaAs
Al + + + + + + -+ + + ++ + + + + + + + TiO2 + + + Al 2O3

0.5 1 1.5 Al2O3Thickness(nm)

Figure 6.15. Summary of minimum RC of single and bilayer MIS.

106

These results of the inverted bilayer dielectric Al/TiO2/Al2O3/GaAs increasing the contact resistance of Al/TiO2/GaAs MIS agree well with reports [97] of Pt/TiO2/Al2O3/Ge decreasing the gate leakage of Pt/TiO2/Ge by more than six orders of magnitude at VFB with only 1nm of Al2O3 (Figure 6.16). The large reduction in the leakage current with ultrathin Al2O3 does not appear to be due to just the reduction of tunneling current through the larger band offset material. From our results, the addition of the Al2O3 interlayer would create a TiO2/Al2O3 dipole which in this case would increase the B,eff of the MOS structure. Similar results were also reported for Pt/TiO2/Al2O3/InGaAs structures significantly reducing the gate leakage of Pt/TiO2/InGaAs [98].

Figure 6.16. Gate leakage of Pt/TiO2/Ge MOSCAPs with and without an Al2O3 interlayer. By inserting 30cycles or 3nm of Al2O3 the leakage current is reduced by more than six orders of magnitude. Figures are from Reference#[97].

6.4.5 TiO2 Degradation Over Time

The bilayer MIS studied in this chapter all contained TiO2, and through measurements over time, the TiO2 was found to be unstable and degraded. This change in resistance agrees with results from TiO2 RRAM [99] and TiO2s sensitivity to oxygen [100] and hydrogen [101]. The formation of titanium interstitials or oxygen vacancies has been suggested as the mechanism for changes in the resistance [101]. Figure 6.17 illustrates how the diode currents for several structures changed over the course of a few days. There was no clear trend, as some films became more resistive while others become
107

more conductive. However, for a given sample the trend over time was consistent, as shown through the measured contact resistance in Figure 6.17d. In between the measurements the samples were stored in nitrogen ambient to minimize exposure and reaction with oxygen. With these safe guards, the samples were found to require a few days before the resistances were significantly different. As a precaution, the time between each fabrication step was minimized, and the samples were always measured within an hour after fabrication. The experimental results were found to be repeatable, with overlaying data points from samples fabricated on different days, which demonstrates that the instability of the TiO2 did not affect our reported results. The TiO2 degradation over time can be avoided by capping the surface with a thick SiO2 film to prevent exposure to air, but would require a slightly different device structure (Figure 6.18).

(a)
|Current| (A/cm2)

10

|Current| (A/cm2)

20cy TiO + 2 12cy HfO

(b)

10

30cy TiO + 2 12cy HfO

2

10

-1

10

-1

10

-2

Day 0 Day 3 Day 6 Day 9

10

-2

Day 0 Day 3 Day 6 Day 9

10

-3

-1

-0.5

0 Voltage

0.5

10

-3

-1

-0.5

0 Voltage

0.5

(c)
|Current| (A/cm2)

10

(d)
40cy TiO + 2 12cy HfO
2

10

ContactResistanceRatio

30cyTiO2 +25cyZrO2 20cyTiO2 +12cyHfO2 40cyTiO2 +12cyHfO2 30cyTiO2 +12cyHfO2 30cyTiO2 +7cyAl2 O3

10

-1

10

-2

Day 0 Day 3 Day 6 Day 9

10

-3

-1

-0.5

0 Voltage

0.5

0.1 0 3

Figure 6.17. Diode current measured immediately, 3 days, 6 days, and 9 days after fabrication, with changes saturating by day 9. There was no apparent trend in the resistance change even among the same materials (a) 20cy TiO2 + 12cy HfO2 (b) 30cy TiO2 + 12cy HfO2 (c) 40cy TiO2 + 12cy HfO2 (d) Summary of RC changes for the various bilayer MIS over time.
108

Day

(a)
Al Al 2O3 TiO2 GaAs

(b)
SiO2 Al Al 2O3 TiO2 GaAs SiO2

Figure 6.18. (a) Current device structure. (b) Device structure needed to prevent TiO2 degradation over time.

6.5 Discussion
The exact reasoning for the observed reduction in B,eff in the high-/high- MIS is still being studied. However, it seems possible that it is due to dipoles formation at the high-/high- interface, similar to the dipoles reported at SiO2/high- interfaces that manifest as shifts in the MOSFET VFB [91, 93, 94]. These dipoles are cited to arise from differences in the electronegativity () [90, 102] or oxygen areal density () [96] of the two materials. Interface dipoles are reported to be formed due to discontinuities in the elements electronegativities that generate dipoles at both the high-/SiO2 interface and within the high- material [102]. In the high-, the amorphous structure and the great screening ability prevents buildup of a net dipole. However, at the high-/SiO2 interface there is a difference in the dielectric constant or screening ability of the two materials which allows a net dipole to build up (Figure 6.19a). In studying how doping of HfO2 changes the HfO2/SiO2 dipole, the electronegativity of the dopant atoms were discovered to determine the magnitude of the net dipole and therefore the shifts in VFB (Figure 6.19b). Although interface dipoles induced by differences in dielectric screening and can explain the observed HfO2/SiO2 dipoles the electronegativities and dielectric constants of high- materials are much closer in value (Table 6.2), and it is unclear if the results from ab-initio modeling of doped HfO2/SiO2 (ionic/covalent bonds) interfaces is directly applicable to high-/high- interfaces (ionic/ionic bonds).
109

(a)

(b)

Figure 6.19. (a) Schematic of net dipole build up due to screening ability differences at the interface. (b) Illustration of how the dipole magnitude changes with the electronegativity of the dopant atom. Figures are from Reference#[102].

Pauling Electronegativity Si Ti Zn Al Zr La Hf Y O
Table 6.2. 1.91 1.54 1.65 1.61 1.33 1.1 1.3 1.22 3.61

Work Function (eV)

4.7 4.33 4.3 4.08 4.05 4 3.9 3.1

Dielectric Constant of Oxide Formed

3.9 80 8.3 9 25 27 25 15

Electronegativity, work function, and dielectric constant of the

elements corresponding to the investigated dielectrics.

110

In the case of the oxygen areal density theory [96], when two materials are placed in contact there is a transfer of oxygen from the higher to the lower material, resulting in a positively charged vacancy and a dipole pointing towards the higher material. Kita et al. define as the number of oxygen atoms per unit area, where the unit structure is defined as the structure containing a single oxygen atom. The calculation of the unit volume (Vu) and are shown below:

Molecular Weight of Unit Structure =

Volume of Unit Structure = Vu =

Molecular Weight Number of Oxygen Atoms

Unit Structure Molecular Weight Density

= Vu -2/3
Molecular Weight (g/mol) Y2O3 SiO2 HfO2 Al2O3 TiO2 ZrO2 ZnO SiON
226 60.1 210 102 79.9 123 81.4 40.1

Oxygen Atoms Per Vu

3 2 2 3 2 2 1 1

Vu Molecular Weight (g/mol)

75.3 30.0 105 34.0 39.9 61.6 81.4 40.1

Density 3 (g/cm )
4.8 2.2 9.8 4.0 3.3 5.5 5.6 3.4

Vu

(cm )
15.7 13.7 10.7 8.5 12.1 11.2 14.5 11.9

-2 (cm )
0.160 0.175 0.205 0.240 0.190 0.200 0.168 0.191

/ TiO2
0.841 0.923 1.083 1.266 1.000 1.053 0.886 1.009

Table 6.3. Calculation of and the ratio taken relative to TiO2 for the investigated dielectrics. These values were calculated based on ideal stoichiometry and density values, so the actual value can differ.

In calculating for various dielectrics (Table 6.3), we find that Al2O3 (Al2O3/TiO2 = 1.27), HfO2 (HfO2/TiO2 = 1.08), and ZrO2 (ZrO2/TiO2 = 1.06) all have areal oxygen densities greater than TiO2, so there would be a transfer of oxygen to the TiO2, resulting in a positively charged vacancy in the high- and a dipole pointing towards the high-. This dipole direction agrees with our experimental data, but contradicts the reports in
111

literature citing that dipoles are not formed at high-/high- interfaces. The difference can be attributed to the specific high-k materials studied. Previous reports include Al2O3/HfO2 [92] and HfO2/Y2O3 [91] interfaces, while the dipoles at the TiO2/Al2O3, TiO2/HfO2, and TiO2/ZrO2 interfaces that we report here have not been investigated before. Also, it is possible that the difference can be due to the thermal annealing steps used in the reported literature [91, 92] that could change the dipole or cause some intermixing between the layers. The high temperature annealing between 500-640oC for 30 to 60sec in nitrogen atmosphere was most likely used to improve the SiO2/Si interface for MOSCAPs. In our case, the samples are measured as deposited without any annealing process. To investigate the effect of RTA annealing, we fabricated four MIS samples with Al metal on n-GaAs substrates using TiO2, Al2O3, Al2O3+TiO2, and TiO2+Al2O3 dielectrics. The single and bilayer samples allow us to separate the effects in the high- film and at the high-/GaAs interface from ones at the high-/high- interface. After ALD deposition and prior to metal evaporation, some of the samples underwent RTA anneals at 300oC or 500oC for 60 seconds in nitrogen ambient. As shown below in Figure 6.20, the single layer MIS contact resistances do not change significantly with RTA annealing, indicating there is not a significant change in both the fixed charge and the high-/GaAs dipole. There is a slight decrease in the contact resistance with higher temperature annealing, but this can be explained by densification of the films that increase the tunneling current through the ultrathin dielectrics. On the other hand, RTA annealing had a large effect on the bilayer MIS contacts. By alternating the TiO2 and Al2O3 dielectrics in the bilayer, the as deposited contact resistances are very different. This can be due to several factors: (1) the inverted dipole at the high-/high- interface, (2) the different dielectric/semiconductor dipole, and (3) the change in the fixed charge distribution. RTA annealing at 300oC had only a small effect on the contact resistances. However, after annealing at 500oC, the two bilayer MIS changed significantly and the contact resistances became roughly equal. From the single dielectric MIS results, RTA annealing does not change the dielectric/semiconductor dipole and the fixed charge, so the difference can be attributed to a change at the high/high- interface either through intermixing between the two layers or the removal of
112

the dipole. Typically high thermal budgets tend to cause intermixing of materials, but there are some cases, such as for HfO2/SiO2 where after annealing there is phase separation and the interface between materials becomes more defined[103]. Further materials characterization is needed to difference between the two.
100 101 102 103 104 105 106 AsDepRTAat300oCRTAat500oC AsDep RTAat300C RTAat500C
Al Al 2O3 TiO2 GaAs

ContactResistanceRatio

30cyTiO2 13TiO2 7cyAl2O3 7Al2O3 7Al2O3+ 13TiO2 13TiO2+7Al2O3

Al TiO2 Al 2O3 GaAs

Figure 6.20. Effect of RTA annealing on the contact resistance of Al/dielectric/nGaAs single dielectric and bilayer MIS.

In comparing our results with the reports of the absence of a high-/high- dipole, their annealing step may have significantly changed or removed the interface dipole. There are no measurements of the as deposited samples, so it is difficult to pinpoint the exact effect of annealing in their material structure. In our samples the annealing had a large effect, but this may also be due to the lower crystallization temperature of TiO2 that caused our films to have a greater sensitivity to the thermal anneals. One possible counterargument to our results is the fact that despite the annealing step, Kita et al. [96] still observed dipoles at the high-/SiO2 interface. However, this could be due to differences in bonding where high-/high- (ionic/ionic bonding) and high-/SiO2 (ionic/covalent bonding) layers could have varying thermal stabilities. As a result, the annealing step may have changed the high-/high- dipole, but not affect the high-/SiO2 dipole.

113

6.6 Summary
In summary, we successfully demonstrated RC and B,eff tuning of Al/n-GaAs junctions using ALD TiO2/high- bilayer MIS contacts, where the two high- dielectrics in combination further shift the Fermi level and reduce B,eff beyond that of a single dielectric MIS. The underlying mechanism is believed to be the formation of a high/high- dipole through an equalization of the oxygen areal density at the interface (Figure 6.21). To our knowledge, there is no published literature studying high-/high- dipoles, so this may be one of the first papers suggesting the presence of dipoles at high/high- interfaces. This opens doors to the exploration of a multitude of other high/high- dielectrics to ultimately achieve B,eff

0. The ideal bilayer dielectric stack

would be one that optimizes the tradeoff between the dipole magnitude (RSB) and conduction band offset (RT). Figure 6.22 summarizes how these two parameters change for different dielectric materials. This bilayer MIS structure provides much more flexibility in the design of ideal source/drain contacts for III-V MOSFETs and Schottky Barrier FETs. So far, most reports of MIS contacts on Si, Ge, and GaSb are based on single dielectrics, where the additional of another dielectric material may be able to achieve lower barrier height and contact resistances. Further study of the dipole interaction and effective work function will lead to a better understanding of the physics behind metal/III-V contacts as well as contacts to other semiconductors.

Al2O3

Al2O3
TiO2

Vo2+ O2Dipole

TiO2

Figure 6.21. Schematic of the transfer of oxygen from the higher to lower material, leaving behind a positively charged oxygen vacancy and adding a negatively charged ion on the other side to form the dipole.

114

1.3

3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.5 1.0

ArealOxygenDensityRatio

1.1 1.0 0.9 0.8

/TiO2 ECBandOffset(eV)
Y2O3 ZnO SiO22 TiO2 SiON ZrO2 2 HfO22 Al2O3 3 Y2O3 ZnO SiO TiO2 SiON ZrO HfO Al2O

Figure 6.22. Summary of the conduction band offsets and calculated ratios taken relative to TiO2 for the investigated dielectrics.

6.7 Future Work

Dipole formation through an equalization of the oxygen areal density is one reported explanation that is consistent with our experimental observations, but it may not be the correct explanation. To more conclusively determine the mechanism, we need to study dielectrics that create dipoles pointing in the opposite direction from what we have studied. In particular, TiO2/Y2O3 and TiO2/La2O3 bilayers would be invaluable in verifying the oxygen areal density theory, where Y2O3/TiO2 = 0.84 and La2O3/TiO2 = 0.80 indicate dipoles pointing towards TiO2. Also, the effect of RTA annealing on high- /high- interfaces needs to be further examined to clarify the differences with those reported in literature [91, 92]. It should be determined whether or not there is intermixing at the interface that destroys the dipole after annealing. Low angle XRD before and after annealing of multi-structures would be helpful in seeing whether the XRD peaks are blurred or sharpened [103]. In addition, it would be helpful to study the effects of annealing on other bilayer MIS structures without TiO2 to see if the low crystallization temperature of TiO2 is a contributing factor to our annealing results.
115

EC BandOffset(eV)

1.2

Chapter 7 Conclusions
7.1 Thesis Contributions
The contributions of this thesis include the first demonstration of the MIS contact on III-V compound semiconductors. Prior to this work the MIS contact structure was only studied on elemental semiconductors Si and Ge. However, the behavior of binary and ternary compounds could differ. GaAs and InGaAs MIS contacts were verified to successfully reduce the contact resistance and effective electrical barrier height as compared to their Schottky counterparts. These results are rather counter intuitive in that inserting an ultrathin dielectric layer can in fact reduce the contact resistance. A comprehensive study of how metal workfunction, semiconductor doping, and insulator material affect the electrical behavior was also conducted for the first time. In Si and Ge MIS contact literature only a maximum of one or two dielectric and metal gate materials were studied at a time, so the understanding was limited to the specific materials. Through our study of a wide range of materials, we were able to draw more generalized conclusions. This thesis also elucidates understanding of the strong metal/III-V Fermi level pinning from studying how the MIS contact reduces the effective barrier height. We were able to pinpoint the mechanism to be due to a shift in the Fermi level rather than the previously reported Fermi level unpinning, which suggests the bond polarization theory offers a better explanation of Fermi level pinning than the metal induced gap states theory.
116

Through investigating a wide range of dielectric materials coupled with thermal annealing studies of the MIS contacts, the observed electrical behavior was discovered to be caused by a combination of dipole formation at the dielectric/semiconductor interface and presence of bulk fixed charge in the dielectric materials. Prior to this work, fixed charge was never considered to contribute to the observed MIS barrier height lowering, and we believe the fixed charge results can be applied to the Si and Ge MIS behavior reported in the literature. Further contribution is made in the first use of high-/high- bilayer MIS contacts that demonstrated a significant improvement over the single dielectric MIS contacts. Previously, bilayer MIS contacts have been studied on Si, but they were limited to SiO2/high- dielectric interfaces. The use of a thermally grown ultrathin SiO2 has limited this concept to Si substrates, while the use of two high- dielectrics can be applied to any semiconductor, including III-V and Ge. The underlying mechanism was discovered to be due to the presence of high-/high- dipoles that are reported for the first time. We also provided a comparison between single and bilayer MIS contact resistance and show the evolution of changes across different dielectric thicknesses, whereas SiO2/high- MIS reports only offered a comparison with the Schottky counterpart and did not include the effect of dielectric thickness on the contact resistance. Overall, this thesis provides a more thorough understanding of the reasoning behind the observed MIS contact behavior, which enables a better prediction of optimal material properties for minimal contact resistance.

7.2 Future Directions

In continuing to explore MIS contacts, it would be helpful to study the dielectric properties in more detail through further materials characterization. Also, since ALD material properties can change significantly with deposition temperatures, it would be interesting to see how the deposition temperature affects the MIS electrical behavior and to correlate those changes with changes in the dielectric density, stoichiometry, and band offsets. Similarly, a more comprehensive study of the effect of thermal annealing can
117

offer a deeper understanding of the thermal stability and limitations of these MIS contacts. If the thermal effects on the contact behavior can be predicted, then it may be possible to further optimize and minimize the contact resistance. For bilayer dielectric MIS contacts, it would be beneficial to study a greater number of high-/high- combinations to offer a more generalized summary of electronic dipoles and bilayer contacts. In particular, TiO2/Y2O3 and TiO2/La2O3 dielectrics are interesting in that through simple calculation they should form dipoles pointing in the opposite direction of what was observed in this work. So far in III-V MIS contacts the Fermi level has only been shifted towards the conduction band, while no dielectrics have been demonstrated a shift of the Fermi level towards the valence band. Finally, this MIS contact structure can be applied to more III-V semiconductors and even other semiconductors such as CNT and graphene. Essentially the use of ultrathin dielectrics to shift the Fermi level through fixed charge and dipole formation can be applied to any material that experiences Fermi level pinning.

7.3 Concluding Remarks

In this thesis we demonstrated the use of an inserted insulator for reducing the metal/III-V effective barrier height for a large selection of materials. However, there are still many difficulties in achieving ohmic contacts due to the finite tunneling resistance through the dielectrics. The lack of thermal stability is also a problem, especially as the contact resistance increased several orders of magnitude after a 30 minute forming gas anneal. In current CMOS technology, wafers need to undergo a forming gas anneal to improve the gate stack quality and also need to withstand some thermal cycle processing in subsequent process steps. Therefore, for MIS contacts to become a promising contact technology, it is necessary to: (1) find dielectric materials with zero or negative band offsets, (2) develop the ability to introduce fixed charge, (3) controllably tune dipole direction and magnitude, and (4) use thermally stable materials. Nevertheless, even if these conditions cannot be met, the idea of using ultrathin dielectrics to shift the Fermi level may still have other applications outside of CMOS contacts.
118

Appendix A : Piece Processing

Items to Purchase:

Glassware Purchase your own glassware from the chemistry stock room because most processing steps will require you to use beakers. Outside beakers may be contaminated with some unknown materials or nanoparticles. It is also a good habit to have dedicated glassware for certain groups of chemicals and to use different tweezers for each group. Tweezers Carbon tipped tweezers give much better grip of samples. SNF stock room point tweezers are good for grabbing from the side, but from the top it will chip off pieces. Grip is very useful during litho when timed hotplates are needed Kapton dots Often times for SNF tools you will need to mount your small pieces onto a carrier wafer, such as in Innotec for metal deposition or Matrix for resist removal. The Kapton dots are pre-cut circles so it avoids the mess of kapton tape sticking to scissors.

Lithography Tips:

For contact mask design you should put multiple layers on one mask since for small pieces you will only be using a few dies so there is no need to have one mask per layer. Do not make deep scribe marks on the back because sometimes you can lose vacuum for either the resist coating or contact aligner. For resist spinning on Headway or Laurel, be sure to use blue tape from the stock room on the back of your samples to get better vacuum. However, make sure you
119

remove this take before the resist baking.

Karl Suss Contact Aligner : For alignment use the small single piece chuck. If it is not available you can cut the 4 yellow circular tape from the SNF stock room to block up most of the holes on the 4 wafer chucks. Hot Plates: If there is foil present on the hot plate, unwrap it for small piece processing. The foil does not lie completely flat and with extremely small pieces sometimes the foil can lift upwards and the temperature may be lower.

Silicon Carrier Wafers:

4 Si carrier wafers are useful in tools that only take 4 wafers such as the RTA, FGA, and ALD. These dummy wafer 4 Si wafers have etched down grooves to hold the pieces. Fabrication details: 1. Thermally grow 100nm of SiO2 2. Pattern the wafer with resist. Kapton tape on a blank old mask can be used to design a detailed pattern to be used with Karl Suss. Another option is painting resist directly on the edges of the wafer. 3. Dry etch the SiO2 patter. It is important to use dry etch rather than wet etch so SiO2 remains on the back of the wafer. 4. Use the SiO2 as a mask to wet etch the Si wafer in heated TMAH.

0.5

0.5

120

Appendix B : Test Structures & Mask Design

1. Transistors
RingFETs:
Length Width

RingFETsareselfisolatedanddonot
needamesaetch.

S G D

GatetoS/Dspacing=1,1.5,2,4m
Labelofspacingis=Z,SZ,S,L

S/DDopinghasan1,1.5,2um
overlapwiththegate

RectangularFETs:
Length Width

S D

B G

Greenlayer=mesaetch Purplelayer=activecontact S/DDopinghasan1,1.5,2umoverlapwiththegate

121

2. Contact Resistance

KelvinStructure#1:

KelvinStructure#2:

Currentpathisdefinedby implantation(pinklayer) Numberindicatesawidth of4m Nindicatesancontact

Currentpathisdefinedby
mesaetch(greenlayer)with implantationeverywhere (pinklayer)

Nindicatesancontact

TransmissionLineMethod(TLM):

Spacingbetweencontacts
are5,10,15,20,and40m

Contactpadshavewidthsof
either100or200m

122

CircularTLM(CTLM):

Spacingbetweencontactsare5,
10,15,20,25,30,40,and60m

3. Resistivity

VanDerPauw:

Activecontactarea=4x4m Currentpathisdefinedbythe
mesaetch(greenlayer)

FourPointProbe:

Activecontactarea=4x4m Length=296m
Width=6m

Currentpathisdefinedbythe
mesaetch(greenlayer)

123

4. Other Structures

MOSCAPs:

Numberindicatestheareaofthe
MOSCAPso2.5K=2500m2

Bluelayer=metalgate
pnjunction:
greylayer=bodycontact

Numberindicatestheareaofthe
MOSCAPso2.5K=2500m2

redlayer=S/Dcontacts
greylayer=bodycontact

MOSFETwithS/DTiedTogether:

Numberindicatestheareaso
2.5K=2500m2

redlayer=S/Dcontacts
bluelayer=gatecontact

ChargePumpingFET:

Forchargepumpingmeasurements FETlength=50,75,100m
FETwidth=200m

redlayer=S/Dtiedtogether

blue+purplelayer =gatecontact

124

5. Mask Overview

125

Appen A ndix C : MOSF M FET F Fabrication n

1. 1 Overview
Arse enicCap
Step#0

PR

Al

PR

pInGaAs

p InGaAs
Step#10

Al A 2O3
Step#1

pInGaAs

Diffusion ofimplant

Al A 2O3 overetch o ~15nm ~

Mask Alignm ment ~12um

pInGaAs
Step#11

IIIVMOSF FETwithAll loyedS/DC Contacts

1. AsDeca ap+ALDAl2O315nmat3 oCfor 300 encapsu ulationlayer r 2. Patternalignmentm marksandet tchinto substrat te(Mask#1) ) 3. S/Dpatt terningandSiimplantat tion(Mask#2 2) 4. Striphardenedphot toresistbyO2ashing O 5. S/DactivationbyRT TA(700oCfo or10sinN2) 6. Remove 2O3byBO eAl OE 7. (NH4)2S+ALDregro owth:8nmA 2O3at300oC Al 8. Gatelift toffpattern ning+Ni/Au evap(Mask k#3,8) 9. Gateme etalliftoff 10. PatternS/D+wetetchAl2O3+o ohmicAu/Ge e/Ni evap+liftoff(Mask k#5,7) o 11. Alloying gRTA400 Cfor30secin 2 nN
126

IIIVMOSFETwithMISS/DContacts
Copysteps#19fromflowwithalloyedS/D contactsupthroughgateformation. 10. WetetchAl2O3gateoxide 11. SputterSiN+evaporateS/Dmetalallover 12. PatternandetchS/Dmetal(Mask#5) 13. QuickdipinHFforthinSiN

Notes:

The simplified process flow illustration shown above does not include the isolation oxide deposition and body contact formation. The isolation oxide layer is more for the contact resistance and resistivity measurements such as in the Kelvin and four point probe structures.

127

2. Process Details
ProcessStep
1.ALD15nmOxide

ProcessingDetails
1. 2. 3. 1. 2. 3. 4. 5. 6. 7. 1. 2. 1. 2. 3. 4. 5. 6. 7. 8. 1. 2. 3. Organicscleanaftercleavewafer Arsenicdecapat400oCfor6min ALDAl2O315nmat300oC YESovenforHMDS Headwayspinresist5.5krpmfor30secfor1um Bake90oCfor60sec ExposeKSfor1.01.2secatCh#1(15mV/cm2) Bake115oCfor60sec DevelopMF26Afor40sec Bake110oCfor60sec WetetchAl2O3in20:1BOEdiluted1:1inDIfor1.5min WetetchInGaAsinH2O2:H3PO4:H2O=1:1:10for45sec Removephotoresist YESovenforHMDS Headwayspinresist5.5krpmfor30secfor1um Bake90oCfor60sec ExposeKSfor1.01.2secatCh#1(15mV/cm2) Bake115oCfor60sec DevelopMF26Afor40sec Bake110oCfor60sec Mountsamplesusingresistona4wafer Siimplant20keV/1E14cm2 Removephotoresist

Masking Layer

2.Pattern AlignmentMarks

Mask#1: Alignment Marks+ MesaEtch

3.EtchAlignment MarksintoInGaAs 4.PatternS/D Implantation

Mask#2: S/DImplant Mask

5.S/DImplant

6.Remove hardenedresist 7.S/DActivation 8.ALDGateOxide

MatrixO2asherat150Wfor3min RTA(700oCfor10sinN2) 1. WetetchAl2O3in20:1BOEdiluted1:1inDIfor1.5min 2. NH4OHor(NH4)2Spassivation 3. ALDAl2O38nmat300oC 1. LOL2000spin3krpmfor60sec 2. Bake150oCfor4min 3. Headwayspinresist5.5krpmfor30secfor1um 4. Bake90oCfor60sec 5. ExposeKSfor1.01.2secatCh#1(15mV/cm2) 6. Bake115oCfor60sec 7. DevelopMF26Afor30sec 8. Bake110oCfor60sec Innotec1000ANi

9.PatternGateLift OffResistMasking

Mask#8: LiftoffGate Mask

10.DepositGate

128

11.LiftOffGate Metal

12.DepositField Oxide 13.PatternActive Contact/Gate 14.WetEtchField OxideandGate Oxide 15.DepositS/D Contact 16.PatternS/D ContactEtchMask 17.WetEtchS/D Metal 18.RemoveResist

1. Leavein1165forafewhours 2. Agitatesamplesin1165 3. Rinseinacetoneusingasqueezebottle.Squeezehard forapressurizedstreamtoremoveanyresidual 4. RinseinmethanolandIPA 5. BlowdryinN2 ALD150oC500cycles(usequickcyclesrecipeforafaster cyclesinceuniformityisnotascriticalfortheisolation oxide) SameasforMask#1orStep#2 WetetchAl2O3in20:1BOE 1. NH4OH:DI=1:1for3min 2. AJAsputterthinSiNorotherultrathindielectric 3. Innotecevaporate1000AAl SameasMask#1orStep#2 1. 2. 1. 2. 3. 4. 5. 6. AlEtchant QuickHFdipforSiNremoval HeatPRX127to40oCandleavesamplesfor20min RinseinrunningDIwaterfor5min BlowdryinN2.Ensuresamplesarecompletelydry HeatPRS1000to40oCandleavesamplesfor10min RinseinrunningDIwaterfor5min BlowdryinN2

Mask#4: Active Contact

Mask#5: S/DContact EtchMask

19.PatternBody ContactLiftOff Mask 20.DepositBody Contact 21.LiftOff/ RemoveResist

SameasMask#8orStep#9 1. 2. 3. 1. 2. 3. WetetchthickAl2O3 isolation NH4OH:DI=1:10for30sec Ti/Pt/Aucontact Leavein1165forafewhours Agitatesamplesin1165 Rinseinacetoneusingasqueezebottle.Squeezehard forapressurizedstreamtoremoveanyresidual 4. RinseinmethanolandIPA 5. BlowdryinN2

Mask#6: LiftOffBody Contact

129

3. Tips and Tricks

Wet Etching Recipes:

Wet etch rates can vary from day to day with if there are changes in the temperature or humidity and can also depend on the density and dimensions of the patterns. Dummy samples should always be used to calibrate the etch rate. Dummy samples should be made with the real samples, for example during ALD oxide or metal deposition extra dummy samples should be added. If a metal layer is being patterned, these dummy samples should also be patterned with resist. To calibrate the etch rate of an oxide, measure the initial oxide thickness with the ellipsometer. Etch a few samples with equal time spacings such as 20, 40, and 60 seconds, then measure the thickness and calculate the average etch rate.

Ion Implant Preparation:

To implant small pieces, secure the samples on a 4 Si wafer using SPR3612 resist as a sticking layer. Place small dots of resist and place the samples on then bake the wafer at 100oC for 5 to 10 min. Do not bake the wafer at too high of a temperature because it may cause the resist patterns to crack. For extra precaution kapton tape dots can be used to secure the sample corners.

Resist Removal in JT Baker PRS-1000: PRS-1000 can be used to remove even hardened photoresist. SNF wet benches have the PRS-1000 heated to 40oC, however the manufacturer states the resist stripper should be used between 65-85oC. At these higher temperatures, the PRS-1000 strips most resists in 5-20 min without needing the help of PRX-127. Caution: When heating the solution make sure to continuously monitor the temperature. Be sure not to exceed the flash point of 96oC.

130

Lift-Off Photoresist Patterning:

PR PR LOL2000 substrate
substrate substrate

PR

PR

PR

PR

PR

PR

PR

As illustrated above, the LOL2000 + SPR3612 photoresist dual layer works because the LOL material is not photosensitive, so it uses the developed PR as a mask. During the overdevelopment time an undercut pattern is created in the LOL layer. The undercut profile tends to create a small gap so not only is the metal deposition thinner, but the 1165 remover can also penetrate more easily. When using LOL, make sure not to over develop the pattern because if there is too much undercut the resist may collapse making the pattern a single layer resist. Develop several dummy samples with different development times and check these samples under the optical microscope before proceeding with the real samples. The idea undercut is about 1m, so under a 50X magnification the pattern should look like two very close lines. If there is only one line then the LOL has not begun to develop the undercut. If there are two clear lines with a gap in between then the sample has been developed for too long.

Metal Lift-Off in Shipley 1165 Microposit Remover:

Typically for dual layer lift-off patterning (LOL2000 + resist) the metal will lift off after a few hours of soaking in 1165. If the pattern does not lift off, you can try: 1. Heating up the 1165 to roughly 60oC which will speed up the lift-off process significantly. Make sure you heat it up in the water bath at the solvent wet bench rather than using a hot plate for better temperature control. Make sure not to approach the flash point of 88oC. 2. Sonication of the sample in 1165 or acetone is another option. Turn the sonication power down to the lowest and sonicate in 30 sec intervals and check the patterns under a microscope. Caution: If the metal does not adhere well to the underlying layer the pattern may be roughened or in the extreme case the pattern can be completely lifted off. In this case an ultrathin Ti adhesion layer of 5A can help. 3. Certain metals lift off better than others. For example Pt and Ni lift-off more easily than Au or Al, so it may be helpful to try a different metal.
131

Publications
Journal Publications
J. Hu and H.-S. Philip Wong, Impact of Forming Gas Annealing on the Electrical Characteristics of ALD Al2O3/ In0.53Ga0.47As MOSCAPS and MOSFETs, Journal of Appl. Phys., submitted. J. Hu, K.C. Saraswat, and H.-S. P. Wong, Impact of Fixed Charge on MetalInsulator-Semiconductor Barrier Height Reduction, Appl. Phys. Lett., Vol. 99, accepted Dec 2011. J. Hu, K.C. Saraswat, and H.-S. P. Wong, Metal/III-V Effective Barrier Height Tuning using ALD High-/ High- Bilayer Interfaces, Appl. Phys. Lett., Vol. 99, pp.092107,September 2011. J. Hu, K.C. Saraswat, and H.-S.P. Wong, Experimental Demonstration of In0.53Ga0.47As Field Effect Transistors with Scalable Non-alloyed Source/Drain Contacts, Appl. Phys. Lett., Vol. 98, pp.062107, Feb 2011. J. Hu, H.-S.P. Wong, and K.C. Saraswat, Novel Contact Structure for High Mobility Channel Materials, Materials Research Society (MRS) Bulletin, Vol. 36, pp 112-120, Feb 2011.

132

J. Hu, K.C. Saraswat, and H.-S.P. Wong, Metal/III-V Schottky Barrier Height Tuning for the Design of Non-Alloyed III-V FET Source/Drain Contacts, Journal of Appl. Phys, Vol. 107, pp.063712, March 2010.

Conference Proceedings
J. Hu, K.C. Saraswat, and H.-S.P. Wong, Metal/III-V Effective Barrier Height Tuning using ALD High- Dipoles, IEEE Device Research Conference (DRC) Digest, vol. 69, pp. 135-136, June 2011. J. Hu and H.-S.P. Wong, Impact of Forming Gas Annealing on the Electrical Characterization of ALD Al2O3/ In0.53Ga0.47As MOS Capacitors, IEEE Semiconductor Interface Specialists Conference (SISC), pp.73, Dec 2009. J. Hu, X. Guan, D. Choi, J. S. Harris, K.C. Saraswat, and H.-S.P. Wong, Fermi Level Depinning For the Design of III-V FET Source/Drain Contacts, IEEE VLSI-TSA Tech., pp.123-124, April 2009. J. Hu, D. Choi, J. Harris, K.C. Saraswat, and H.-S.P. Wong, Fermi-Level Depinning of GaAs for Ohmic Contacts, IEEE Device Research Conference (DRC) Digest, vol. 66, pp. 89-90, June 2008. J. Hu, J. E. Park, G. Freeman, and H.-S.P. Wong, Effective Drive Current for Sub-45nm Technologies, Proc. NSTI Nanotech, vol. 3, pp.829 832, June 2008.

133

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