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FEATURES Programmable subcarrier frequency and phase ITU-R1 BT601/BT656 YCrCb to PAL/NTSC video encoder Programmable LUMA delay High quality 10-bit video DACs Individual on/off control of each DAC SSAF (super sub-alias filter) CCIR and square pixel operation Advanced power management features Integrated subcarrier locking to external video source CGMS (copy generation management system) Color signal control/burst signal control WSS (wide screen signaling) Interlaced/noninterlaced operation NTSC M, PAL N2, PAL B/D/G/H/I, PAL-M3 , PAL 60 Complete on-chip video timing generator Single 27 MHz clock required (2 oversampling) Programmable multimode master/slave operation Macrovision 7.1 (ADV7174 only) Closed captioning support 80 dB video SNR Teletext insertion port (PAL-WST) 32-bit direct digital synthesizer for color subcarrier On-board color bar generation Multistandard video output support: On-board voltage reference Composite (CVBS) 2-wire serial MPU interface (I2C compatible and fast I2C) Component S-video (Y/C) Single-supply 2.8 V and 3.3 V operation Video input data port supports: Small 40-lead 6 mm 6 mm LFCSP package CCIR-656 4:2:2 8-bit parallel input format 40C to +85C at 3.3 V Programmable simultaneous composite and S-video or RGB 20C to +85C at 2.8 V (SCART)/YPbPr video outputs APPLICATIONS Programmable luma filters low-pass [PAL/NTSC] notch, Portable video applications extended SSAF, CIF, and QCIF Mobile phones Programmable chroma filters (low-pass [0.65 MHz, 1.0 MHz, Digital still cameras 1.2 MHz, and 2.0 MHz], CIF, and QCIF) Programmable VBI (vertical blanking interval) FUNCTIONAL BLOCK DIAGRAM
TTXREQ TTX M U 10 L T I 10 P L E 10 X E R
ADV7174/ADV7179
VAA RESET COLOR DATA P7P0 8 4:2:2 TO 4:4:4 8 INTERPOLATOR 8 Y 8 YCrCb TO U 8 YUV MATRIX V 8 ADD 9 SYNC 8 ADD BURST 8 INTER- 9 POLATOR 8 INTERPOLATOR 8 PROGRAMMABLE LUMINANCE FILTER 10 PROGRAMMABLE CHROMINANCE 10 FILTER 10 VIDEO TIMING GENERATOR I2C MPU PORT REAL-TIME CONTROL CIRCUIT 10 POWER MANAGEMENT CONTROL (SLEEP MODE) CGMS AND WSS INSERTION BLOCK TELETEXT INSERTION BLOCK YUV TO RBG MATRIX
10 10 10
U V
10 VOLTAGE REFERENCE CIRCUIT VREF RSET COMP
CLOCK
SCLOCK
SDATA
ALSB
SCRESET/RTC
GND
Figure 1.
ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations). 2 Throughout the document, N is referenced to PAL Combination N. 3 ADV7174 only. Protected by U.S. Patent Numbers 5,343,196 and 5,442,355 and other intellectual property rights. Protected by U.S. Patent Numbers 4,631,603, 4,577,216, 4,819,098 and other intellectual property rights. The Macrovision anticopy process is licensed for noncommercial home use only, which is its sole intended use in the device. Contact the sales office for the latest Macrovision version available.
1
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 2004 Analog Devices, Inc. All rights reserved.
02980-A-001
ADV7174/ADV7179
TABLE OF CONTENTS
Specifications..................................................................................... 4 2.8 V Specifications ...................................................................... 4 2.8 V Timing Specifications ........................................................ 5 3.3 V Specifications ...................................................................... 6 3.3 V Timing Specifications ........................................................ 7 Absolute Maximum Ratings............................................................ 9 ESD Caution.................................................................................. 9 Pin Configuration and Function Descriptions........................... 10 General Description ....................................................................... 11 Data Path Description................................................................ 11 Internal Filter Response............................................................. 11 Typical Performance Characteristics ........................................... 13 Features ............................................................................................ 16 Color Bar Generation ................................................................ 16 Square Pixel Mode...................................................................... 16 Color Signal Control .................................................................. 16 Burst Signal Control................................................................... 16 NTSC Pedestal Control ............................................................. 16 Pixel Timing Description .......................................................... 16 8-Bit YCrCb Mode ................................................................. 16 Subcarrier Reset.......................................................................... 16 Real-Time Control ..................................................................... 16 Video Timing Description .................................................... 16 Vertical Blanking Data Insertion.......................................... 17 Mode 0 (CCIR-656): Slave Option....................................... 17 Mode 0 (CCIR-656): Master Option ................................... 17 Mode 1: Slave Option HSYNC, BLANK, FIELD................ 20 Mode 1: Master Option HSYNC, BLANK, FIELD ............ 21 Mode 2: Slave Option HSYNC, VSYNC, BLANK.............. 22 Mode 2: Master Option HSYNC, VSYNC, BLANK .......... 23 Mode 3: Master/Slave Option HSYNC, BLANK, FIELD.. 24 Power-On Reset.......................................................................... 25 SCH Phase Mode........................................................................ 25 MPU Port Description............................................................... 25 Register Accesses ........................................................................ 26 Register Programming................................................................... 27 Subaddress Register (SR7SR0) ............................................... 27 Register Select (SR5SR0) ......................................................... 27 Mode Register 1 (MR1) ............................................................. 29 Mode Register 2 (MR2) ............................................................. 30 Mode Register 3 (MR3) ............................................................. 31 Mode Register 4 (MR4) ............................................................. 32 Timing Mode Register 0 (TR0) ................................................ 33 Timing Mode Register 1 (TR1) ................................................ 34 Subcarrier Frequency Registers 30 ........................................ 35 Subcarrier Phase Register.......................................................... 35 Closed Captioning Even Field Data Registers 10 ................ 35 Closed Captioning Odd Field Data Registers 10 ................. 36 NTSC Pedestal/PAL Teletext Control Registers 30 ............. 36 Teletext Request Control Register (TC07) .............................. 37 CGMS_WSS Register 0 (C/W0)............................................... 37 CGMS_WSS Register 1 (C/W1)............................................... 38 CGMS_WSS Register 2 (C/W2)............................................... 38 Appendix 1Board Design and Layout Considerations.......... 39 Ground Planes ............................................................................ 39 Power Planes ............................................................................... 39 Supply Decoupling ..................................................................... 40 Digital Signal Interconnect ....................................................... 40 Analog Signal Interconnect....................................................... 40 Appendix 2Closed Captioning ................................................. 41
Rev. A | Page 2 of 52
ADV7174/ADV7179
Appendix 3Copy Generation Management System (CGMS) ............................................................................................................42 Function of CGMS Bits ..............................................................42 Appendix 4Wide Screen Signaling (WSS) ...............................43 Function of WSS Bits ..................................................................43 Appendix 5Teletext .....................................................................44 Teletext Insertion.........................................................................44 Teletext Protocol..........................................................................44 Appendix 6Waveforms ...............................................................45 NTSC Waveforms (with Pedestal) ............................................45 NTSC Waveforms (without Pedestal) ......................................46 PAL Waveforms ...........................................................................47 Pb Pr Waveforms.........................................................................48 Appendix 7Optional Output Filter ...........................................49 Appendix 8Recommended Register Values.............................50 Outline Dimensions........................................................................52 Ordering Guide ...........................................................................52
REVISION HISTORY
2/04Changed from REV. 0 to REV A. Added 2.8 V Version .......................................................... Universal Format Updated.................................................................. Universal Device Currents Updated on 3.3 V Specification .......... Universal Added new Table 1 and Renumbered Subsequent Tables.............4 Added new Table 2 and Renumbered Subsequent Tables ...........5 Change to Figure 54 ........................................................................38 Change to Figure 55 ........................................................................39 Change to Figure 79 ........................................................................48 Changed Ordering Guide Temperature Specifications ..............52 Updated Outline Dimensions........................................................52 10/02Revision 0: Initial Version
Rev. A | Page 3 of 52
ADV7174/ADV7179 SPECIFICATIONS
2.8 V SPECIFICATIONS
VAA = 2.8 V, VREF = 1.235 V, RSET = 150 . All specifications TMIN to TMAX1, unless otherwise noted. Table 1.
Parameter STATIC PERFORMANCE2 Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity Differential Nonlinearity DIGITAL INPUTS2 Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN DIGITAL OUTPUTS2 Output High Voltage, VOH Output Low Voltage, VOL Three-State Leakage Current Three-State Output Capacitance ANALOG OUTPUTS2 Output Current 3 DAC-to-DAC Matching Output Compliance, VOC Output Impedance, ROUT Output Capacitance, COUT POWER REQUIREMENTS2, 4 VAA Normal Power Mode IDAC (Max)5 ICCT6 Low Power Mode IDAC (Max)5 ICCT6 Sleep Mode IDAC7 ICCT8 Power Supply Rejection Ratio Conditions1 Min Typ Max 10 RSET = 300 Guaranteed monotonic 1.6 VIN = 0.4 V or 2.4 V 10 ISOURCE = 400 A ISINK = 3.2 mA 2.4 0.4 10 10 RSET = 150 , RL = 37.5 33 0 30 IOUT = 0 mA 2.8 RSET = 150 , RL = 37.5 115 30 62 30 0.1 0.001 0.01 120 30 34.7 2.0 37 1.4 0.7 1 3.0 1 Unit Bits LSB LSB V V A pF V V A pF mA % V k pF V mA mA mA mA A A %/%
COMP = 0.1 F
0.5
1 2
Temperature range TMIN to TMAX: 20C to +85C. Guaranteed by characterization. 3 DACs can output 35 mA typically at 2.8 V (RSET = 150 and RL = 37.5 ). Full drive into 37.5 load. 4 Power measurements are taken with clock frequency = 27 MHz. Max TJ = 110C. 5 IDAC is the total current (min corresponds to 5 mA output per DAC, max corresponds to 37 mA output per DAC) to drive all three DACs. Turning off individual DACs reduces IDAC correspondingly. 6 ICCT (circuit current) is the continuous current required to drive the device. 7 Total DAC current in sleep mode. 8 Total continuous current during sleep mode.
Rev. A | Page 4 of 52
ADV7174/ADV7179
2.8 V TIMING SPECIFICATIONS
VAA = 2.8 V, VREF = 1.235 V, RSET = 150 . All specifications TMIN to TMAX1, unless otherwise noted. Table 2.
Parameter MPU PORT2, 3 SCLOCK Frequency SCLOCK High Pulse Width, t1 SCLOCK Low Pulse Width, t2 Hold Time (Start Condition), t3 Setup Time (Start Condition), t4 Data Setup Time, t5 SDATA, SCLOCK Rise Time, t6 SDATA, SCLOCK Fall Time, t7 Setup Time (Stop Condition), t8 ANALOG OUTPUTS3, 4 Analog Output Delay DAC Analog Output Skew CLOCK CONTROL AND PIXEL PORT4, 5 fCLOCK Clock High Time, t9 Clock Low Time, t10 Data Setup Time, t11 Data Hold Time, t12 Control Setup Time, t11 Control Hold Time, t12 Digital Output Access Time, t13 Digital Output Hold Time, t14 Pipeline Delay, tPD5 TELETEXT3, 4, 6 Digital Output Access Time, t16 Data Setup Time, t17 Data Hold Time, t18 RESET CONTROL3, 4 RESET Low Time Conditions1 Min 0 0.6 1.3 0.6 0.6 100 Typ Max 400 Unit kHz s s s s ns ns ns s ns ns MHz ns ns ns ns ns ns ns ns Clock Cycles ns ns ns ns
After this period the first clock is generated Relevant for repeated start condition
1 2
Temperature range TMIN to TMAX: 20C to +85C. TTL input values are 0 V to 2.8 V, with input rise/fall times 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Analog output load 10 pF. 3 Guaranteed by characterization. 4 Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition. 5 See Figure 60. 6 Teletext Port consists of the following: Teletext Output: TTXREQ Teletext Input: TTX
Rev. A | Page 5 of 52
ADV7174/ADV7179
3.3 V SPECIFICATIONS
VAA = 3.0 V3.6 V1, VREF = 1.235 V, RSET = 150 . All specifications TMIN to TMAX2, unless otherwise noted. Table 3.
Parameter STATIC PERFORMANCE3 Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity Differential Nonlinearity DIGITAL INPUTS3 Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN3, 4 Input Capacitance, CIN DIGITAL OUTPUTS3 Output High Voltage, VOH Output Low Voltage, VOL Three-State Leakage Current Three-State Output Capacitance ANALOG OUTPUTS3 Output Current4, 5 Output Current6 DAC-to-DAC Matching Output Compliance, VOC Output Impedance, ROUT Output Capacitance, COUT POWER REQUIREMENTS3, 7 VAA Normal Power Mode IDAC (Max)8 IDAC (Min)8 ICCT9 Low Power Mode IDAC (Max)8 IDAC (Min)8 ICCT9 Sleep Mode IDAC10 ICCT11 Power Supply Rejection Ratio Conditions1 Min Typ Max 10 RSET = 300 Guaranteed Monotonic 2 VIN = 0.4 V or 2.4 V 10 ISOURCE = 400 A ISINK = 3.2 mA 2.4 0.4 10 10 RSET = 150 , RL = 37.5 RSET = 1041 , RL = 262.5 33 34.7 5 2.0 30 IOUT = 0 mA 3.0 RSET = 150 , RL = 37.5 RSET = 1041 , RL = 262.5 3.3 115 20 35 62 20 35 0.1 0.001 0.01 30 3.6 120 37 0.8 1 0.6 1 Unit Bits LSB LSB V V A pF V V A pF mA mA % V k pF V mA mA mA mA mA mA A A %/%
1.4
COMP = 0.1 F
0.5
1 2
The max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V. Temperature range TMIN to TMAX: 40C to +85C. 3 Guaranteed by characterization. 4 Full drive into 37.5 load. 5 DACs can output 35 mA typically at 3.3 V (RSET = 150 and RL = 37.5 ), optimum performance obtained at 18 mA DAC current (RSET = 300 and RL = 75 ). 6 Minimum drive current (used with buffered/scaled output load). 7 Power measurements are taken with clock frequency = 27 MHz. Max TJ = 110C. 8 IDAC is the total current (min corresponds to 5 mA output per DAC, max corresponds to 37 mA output per DAC) to drive all three DACs. Turning off individual DACs reduces IDAC correspondingly. 9 ICCT (circuit current) is the continuous current required to drive the device. 10 Total DAC current in sleep mode. 11 Total continuous current during sleep mode.
Rev. A | Page 6 of 52
ADV7174/ADV7179
3.3 V TIMING SPECIFICATIONS
VAA = 3.0 V3.6 V1, VREF = 1.235 V, RSET = 150 . All specifications TMIN to TMAX2, unless otherwise noted. Table 4.
Parameter MPU PORT3, 4 SCLOCK Frequency SCLOCK High Pulse Width, t1 SCLOCK Low Pulse Width, t2 Hold Time (Start Condition), t3 Setup Time (Start Condition), t4 Data Setup Time, t5 SDATA, SCLOCK Rise Time, t6 SDATA, SCLOCK Fall Time, t7 Setup Time (Stop Condition), t8 ANALOG OUTPUTS3, 5 Analog Output Delay DAC Analog Output Skew CLOCK CONTROL AND PIXEL PORT4, 5 fCLOCK Clock High Time, t9 Clock Low Time, t10 Data Setup Time, t11 Data Hold Time, t12 Control Setup Time, t11 Control Hold Time, t12 Digital Output Access Time, t13 Digital Output Hold Time, t14 Pipeline Delay, tPD6 TELETEXT3, 4 Digital Output Access Time, t16 Data Setup Time, t17 Data Hold Time, t18 RESET CONTROL3, 4 RESET Low Time Conditions1 Min 0 0.6 1.3 0.6 0.6 100 Typ Max 400 Unit kHz s s s s ns ns ns s ns ns MHz ns ns ns ns ns ns ns ns Clock Cycles ns ns ns ns
After this period, the first clock is generated Relevant for repeated start condition
1 2 3
The maximum/minimum specifications are guaranteed over this range. The maximum/minimum values are typical over 3.0 V to 3.6 V range. Temperature range TMIN to TMAX: 40C to +85C. TTL input values are 0 V to 3 V, with input rise/fall times 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Analog output load 10 pF. 4 Guaranteed by characterization. 5 Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition. 6 See Figure 60.
Rev. A | Page 7 of 52
ADV7174/ADV7179
t5 t3
SDATA
t3
t6 t1
SCLOCK
02980-0A-002
t2
t7
t4
t8
CLOCK
t9
CONTROL I/PS S HSYNC, FIELD/VSYNC, BLANK
t10
t12
Cb
Cr
Cb
t11
CONTROL O/PS HSYNC, FIELD/VSYNC, BLANK
t13
02980-A-003
t14
TTXREQ
t16
CLOCK
t17 t18
TTX
02980-A-004
4 CLOCK CYCLES
4 CLOCK CYCLES
4 CLOCK CYCLES
3 CLOCK CYCLES
4 CLOCK CYCLES
Rev. A | Page 8 of 52
Rating 4V GND 0.5 V to VAA + 0.5 V 65C to +150C 150C 260C GND 0.5 V to VAA 30C/W
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability
Analog output short circuit to any power supply or common can be of an indefinite duration. With the exposed metal paddle on the underside of LFCSP soldered to GND on the PCB.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 9 of 52
P4
38
37
36
35
34
33
CLOCK 1 VAA 2 P5 3 P6
4
PIN 1 INDICATOR
P3
P2
P1
P0
TTX
VREF DAC A DAC B VAA GND VAA DAC C COMP SDATA SCLOCK
ADV7174/ADV7179 LFCSP
TOP VIEW (Not to Scale)
27 26 25 24 23 22 21
GND 9 VAA 10
11 12 13 14 15 16 17 18 19 20
GND
FIELD/VSYNC
HSYNC
BLANK
RESET
GND
ALSB
GND
GND
VAA
VREF RSET COMP DAC A DAC B DAC C SCLOCK SDATA ALSB RESET TTX TTXREQ VAA GND
I/O I O O O O I I/O I I I O P G
Rev. A | Page 10 of 52
02980-A-005
Alternatively, each DAC can be individually powered off if not required. Video output levels are illustrated in Appendix 6.
Rev. A | Page 11 of 52
ADV7174/ADV7179
Table 7. Luminance Internal Filter Specifications
Filter Type Low-Pass (NTSC) Low-Pass (PAL) Notch (NTSC) Notch (PATL) Extended (SSAF) CIF QCIF Filter Selection MR04 MR03 MR02 0 0 0 0 0 0 1 1 1 0 1 1 0 0 1 1 0 1 0 1 0 Pass-Band Ripple (dB) 0.091 0.15 0.015 0.095 0.051 0.018 Monotonic 3 dB Bandwidth (MHz) 4.157 4.74 6.54 6.24 6.217 3.0 1.5 Stop-Band Cutoff (MHz) 7.37 7.96 8.3 8.0 8.0 7.06 7.15 Stop-Band Attenuation (dB) 56 64 68 66 61 61 50
0.084 Monotonic
0.7 0.5
3.01 4.08
45 50
Rev. A | Page 12 of 52
MAGNITUDE (dB)
30
MAGNITUDE (dB)
02980-A-006
30
40 50 60 70
40 50 60 70
02980-A-009
6 8 FREQUENCY (MHz)
10
12
6 8 FREQUENCY (MHz)
10
12
10 20
10 20
MAGNITUDE (dB)
30
MAGNITUDE (dB)
02980-A-007
30
40 50 60 70
40 50 60 70
02980-A-010
6 8 FREQUENCY (MHz)
10
12
6 8 FREQUENCY (MHz)
10
12
10 20
10 20
MAGNITUDE (dB)
30
MAGNITUDE (dB)
02980-A-008
30
40 50 60 70
40 50 60 70
02980-A-011
6 8 FREQUENCY (MHz)
10
12
6 8 FREQUENCY (MHz)
10
12
Rev. A | Page 13 of 52
ADV7174/ADV7179
0 0 10 20 10 20
MAGNITUDE (dB)
30
MAGNITUDE (dB)
02980-A-012
30
40 50 60 70
40 50 60 70
02980-A-015
6 8 FREQUENCY (MHz)
10
12
6 8 FREQUENCY (MHz)
10
12
10 20
10 20
MAGNITUDE (dB)
30
MAGNITUDE (dB)
02980-A-013
30
40 50 60 70
40 50 60 70
02980-A-016
6 8 FREQUENCY (MHz)
10
12
6 8 FREQUENCY (MHz)
10
12
10 20
10 20
MAGNITUDE (dB)
30
MAGNITUDE (dB)
02980-A-014
30
40 50 60 70
40 50 60 70
02980-A-017
6 8 FREQUENCY (MHz)
10
12
6 8 FREQUENCY (MHz)
10
12
Rev. A | Page 14 of 52
ADV7174/ADV7179
0 10 20
MAGNITUDE (dB)
30
40 50 60 70
02980-A-018
6 8 FREQUENCY (MHz)
10
12
Rev. A | Page 15 of 52
ADV7174/ADV7179 FEATURES
COLOR BAR GENERATION
The ADV7174/ADV7179 can be configured to generate 100/ 7.5/75/7.5 color bars for NTSC or 100/0/75/0 for PAL color bars. These are enabled by setting MR17 of Mode Register 1 to Logic 1.
REAL-TIME CONTROL
Together with the SCRESET/RTC pin and Bits MR22 and MR21 of Mode Register 2, the ADV7174/ADV7179 can be used to lock to an external video source. The real-time control mode allows the ADV7174/ADV7179 to automatically alter the subcarrier frequency to compensate for line length variation. When the part is connected to a device that outputs a digital data stream in the RTC format (such as a ADV7183A video decoder; see Figure 19), the part automatically changes to the compensated subcarrier frequency on a line-by-line basis. This digital data stream is 67 bits wide and the subcarrier is contained in Bits 0 to 21. Each bit is two clock cycles long. 00H should be written into all four subcarrier frequency registers when using this mode.
SUBCARRIER RESET
Together with the SCRESET/RTC pin and Bits MR22 and MR21 of Mode Register 2, the ADV7174/ADV7179 can be used in subcarrier reset mode. The subcarrier resets to Field 0 at the start of the following field when a low-to-high transition occurs on this input pin.
Rev. A | Page 16 of 52
ADV7174/ADV7179
CLOCK COMPOSITE VIDEO (e.g., VCR OR CABLE) SCRESET/RTC VIDEO DECODER (e.g., ADV7183A) GREEN/LUMA/Y P7P0 RED/CHROMA/Pr BLUE/COMPOSITE/Pb HSYNC FIELD/VSYNC
AD7174/ADV7179
SEQUENCE RESERVED BIT2 RESET BIT3
H/LTRANSITION COUNT START LOW 128 13 RTC TIME SLOT: 01 14 NOT USED IN THE ADV7174/ADV7179 14 BITS RESERVED 0
5 BITS RESERVED
21
67 68
NOTES 1F SC PLL INCREMENT IS 22 BITS LONG, VALUE LOADED INTO ADV7174/ADV7179 FSC DDS REGISTER IS FSC PLL INCREMENT BITS 21:0 PLUS BITS 0:9 OF THE SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS OF THE ADV7174/ADV7179. 2SEQUENCE BIT PAL: 0 = LINE NORMAL, 1 = LINE INVERTED NTSC: 0 = NO CHANGE 3RESET BIT RESET ADV7174/ADV7179 DDS
nization pattern. A synchronization pattern is sent immediately before and after each line during active picture and retrace. Mode 0 is illustrated in Figure 20. The HSYNC, FIELD/VSYNC, and BLANK (if not used) pins should be tied high during this mode.
Rev. A | Page 17 of 52
02980-A-019
ADV7174/ADV7179
ANALOG VIDEO
EAV CODE INPUT PIXELS Y C F 0 0 X 8 1 8 1 Y r F 0 0 Y 0 0 0 0 0 F F A A A 0 F F B B B ANCILLARY DATA (HANC) 268 CLOCK 4 CLOCK 280 CLOCK END OF ACTIVE VIDEO LINE
SAV CODE C C 8 1 8 1 F 0 0 X C Y C Y C Y r Y b b 0 0 0 0 F 0 0 Y b r
4 CLOCK
4 CLOCK 1440 CLOCK 4 CLOCK 1440 CLOCK START OF ACTIVE VIDEO LINE
02980-A-020
DISPLAY
522 H
523
524
525
10
11
20
21
22
V F
260 H
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
ODD FIELD
EVEN FIELD
Rev. A | Page 18 of 52
02980-A-021
ADV7174/ADV7179
DISPLAY VERTICAL BLANK DISPLAY
622 H V
623
624
625
21
22
23
EVEN FIELD
ODD FIELD
DISPLAY
VERTICAL BLANK
DISPLAY
309 H
310
311
312
313
314
315
316
317
318
319
320
334
335
336
ODD FIELD
EVEN FIELD
ANALOG VIDEO
F
02980-A-023
Rev. A | Page 19 of 52
02980-A-022
ADV7174/ADV7179
Mode 1: Slave Option HSYNC, BLANK, FIELD
(Timing Register 0 TR0 = X X X X X 0 1 0) In this mode, the ADV7174/ADV7179 accepts horizontal SYNC and odd/even FIELD signals. A transition of the FIELD input when HSYNC is low indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, the ADV7174/ADV7179 automatically blanks all normally blank lines as per CCIR-624. Mode 1 is illustrated in Figure 24 (NTSC) and Figure 25 (PAL).
DISPLAY
DISPLAY
VERTICAL BLANK
522 HSYNC
523
524
525
10
11
20
21
22
BLANK FIELD
EVEN FIELD
ODD FIELD
DISPLAY
260 HSYNC
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
BLANK
02980-A-024
FIELD
ODD FIELD
EVEN FIELD
DISPLAY
623
624
625
21
22
23
EVEN FIELD
ODD FIELD
DISPLAY
310
311
312
313
314
315
316
317
318
319
320
334
335
336
ODD FIELD
EVEN FIELD
02980-A-025
ADV7174/ADV7179
Mode 1: Master Option HSYNC, BLANK, FIELD
(Timing Register 0 TR0 = X X X X X 0 1 1) In this mode, the ADV7174/ADV7179 can generate horizontal SYNC and odd/even FIELD signals. A transition of the FIELD input when HSYNC is low indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, the ADV7174/ADV7179 automatically blanks all normally blank lines as per CCIR-624. Pixel data is latched on the rising clock edge following the timing signal transitions. Mode 1 is illustrated in Figure 24 (NTSC) and Figure 25 (PAL). Figure 26 illustrates the HSYNC, BLANK, and FIELD for an odd or even field transition relative to the pixel data.
HSYNC
FIELD
PIXEL DATA
Cb
Cr
Y
02980-A-026
Rev. A | Page 21 of 52
ADV7174/ADV7179
Mode 2: Slave Option HSYNC, VSYNC, BLANK
(Timing Register 0 TR0 = X X X X X 1 0 0) In this mode, the ADV7174/ADV7179 accepts horizontal and vertical SYNC signals. A coincident low transition of both and VSYNC inputs indicates the start of an odd field. A VSYNC low
DISPLAY
transition when HSYNC is high indicates the start of an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7174/ADV7179 automatically blanks all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 27 (NTSC) and Figure 28 (PAL).
VERTICAL BLANK
DISPLAY
522 HSYNC
523
524
525
10
11
20
21
22
DISPLAY
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
EVEN FIELD
DISPLAY
VERTICAL BLANK
DISPLAY
622 HSYNC
623
624
625
21
22
23
DISPLAY
309 HSYNC
310
311
312
313
314
315
316
317
318
319
320
334
335
336
Rev. A | Page 22 of 52
02980-A-028
BLANK
02980-A-027
ADV7174/ADV7179
Mode 2: Master Option HSYNC, VSYNC, BLANK
(Timing Register 0 TR0 = X X X X X 1 0 1) In this mode, the ADV7174/ADV7179 can generate horizontal and vertical SYNC signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7174/ADV7179 automatically blanks all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 27 (NTSC) and Figure 28 (PAL). Figure 29 illustrates the HSYNC, BLANK, and VSYNC for an even-to-odd field transition relative to the pixel data. Figure 30 illustrates the HSYNC, BLANK, and VSYNC for an odd-to-even field transition relative to the pixel data.
HSYNC
VSYNC
BLANK
HSYNC
VSYNC PAL = 12 CLOCK/2 NTSC = 16 CLOCK/2 BLANK PAL = 864 CLOCK/2 NTSC = 858 CLOCK/2
Cb
Cr
Cb
02980-A-082
Rev. A | Page 23 of 52
02980-A-029
PIXEL DATA
Cb
Cr
ADV7174/ADV7179
Mode 3: Master/Slave Option HSYNC, BLANK, FIELD
(Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1) In this mode, the ADV7174/ADV7179 accepts or generates horizontal SYNC and odd/even FIELD signals. A transition of the FIELD input when HSYNC is high indicates a new frame,
DISPLAY VERTICAL BLANK
that is, vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, the ADV7174/ADV7179 automatically blanks all normally blank lines as per CCIR-624. Mode 3 is illustrated in Figure 31 (NTSC) and Figure 32 (PAL).
DISPLAY
523
524
525
10
11
20
21
22
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
VERTICAL BLANK
DISPLAY
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
ODD FIELD
EVEN FIELD
622 HSYNC
623
624
625
21
22
23
FIELD
DISPLAY
309 HSYNC
310
311
312
313
314
315
316
317
318
319
320
334
335
336
FIELD
ODD FIELD
EVEN FIELD
02980-A-031
BLANK
02980-A-030
ADV7174/ADV7179
POWER-ON RESET
After power-up, it is necessary to execute a reset operation. A reset occurs on the falling edge of a high-to-low transition on the RESET pin. This initializes the pixel port so that the pixel inputs, P7P0, are selected. After reset, the ADV7174/ADV7179 is automatically set up to operate in NTSC mode. Subcarrier frequency code 21F07C16H is loaded into the subcarrier frequency registers. All other registers, with the exception of Mode Register 0, are set to 00H. With the exception of Bit MR44, all bits in Mode Register 0 are set to Logic 0. Bit MR44 of Mode Register 4 is set to Logic 1. This enables the 7.5 IRE pedestal.
1 1 0 1 0 1 A1 ADDRESS CONTROL SET UP BY ALSB READ/WRITE CONTROL 0 1 X
WRITE READ
0 1
WRITE READ
To control the various devices on the bus, the following protocol must be followed: first, the master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on SDATA while SCLOCK remains high. This indicates that an address/data stream will follow. All peripherals respond to the start condition and shift the next eight bits (7-bit address + R/W bit). The bits transfer from MSB down to LSB. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as an Acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. The idle condition is where the device monitors the SDATA and SCLOCK lines waiting for the start condition and the correct transmitted address. The R/W bit determines the direction of the data. A Logic 0 on the LSB of the first byte means that the master will write information to the peripheral. A Logic 1 on the LSB of the first byte means that the master will read information from the peripheral. The ADV7174/ADV7179 acts as a standard slave device on the bus. The data on the SDATA pin is eight bits long, supporting the 7-bit addresses plus the R/W bit. The ADV7174/ADV7179 has 26 subaddresses to enable access to the internal registers. It therefore interprets the first byte as the device address and the second byte as the starting subaddress. The subaddresses auto increment allows data to be written to or read from the starting subaddress. A data transfer is always terminated by a stop condition. The user can also access any unique subaddress register on a one-by-one basis without having to update all the registers. There is one exception. The subcarrier frequency registers should be updated in sequence, starting with Subcarrier Frequency Register 0. The auto increment function should then be used to increment and access Subcarrier Frequency Registers 1, 2, and 3. The subcarrier frequency registers should not be accessed independently.
Rev. A | Page 25 of 52
02980-A-033
READ/WRITE CONTROL
02980-A-032
ADV7174/ADV7179
Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. During a given SCLOCK high period, the user should issue only one start condition, one stop condition, or a single stop condition followed by a single start condition. If an invalid subaddress is issued by the user, the ADV7174/ ADV7179 cannot issue an acknowledge and returns to the idle condition. If in auto-increment mode the user exceeds the highest subaddress, the following action is taken: 1. In read mode, the highest subaddress register contents continues to be output until the master device issues a noacknowledge. This indicates the end of a read. A noacknowledge condition is when the SDATA line is not pulled low on the ninth pulse. In write mode, the data for the invalid byte is not loaded into any subaddress register, a no-acknowledge is issued by the ADV7174/ADV7179, and the part returns to the idle condition.
WRITE SEQUENCE
Figure 35 illustrates an example of data transfer for a read sequence and the start and stop conditions. Figure 36 shows bus write and read sequences.
SDATA
02980-A-034
SCLOCK
17
17
17 DATA
9 ACK
P STOP
REGISTER ACCESSES
The MPU can write to or read from all of the ADV7174/ ADV7179 registers except the subaddress register, which is a write-only register. The subaddress register determines which register the next read or write operation accesses. All communications with the part through the bus start with an access to the subaddress register. A read/write operation is performed from to the target address, which then increments to the next address until a stop command on the bus is performed.
2.
SUB ADDR
A(S)
DATA
A(S) LSB = 1
DATA
A(S) P
Rev. A | Page 26 of 52
02980-A-035
READ SEQUENCE
SUB ADDR
A(S) S
SLAVE ADDR
A(S)
DATA
A(M)
DATA
A(M) P
Rev. A | Page 27 of 52
02980-A-036
ADV7174/ADV7179
MODE REGISTER 0 (MR0)
Bits: Address: MR07 MR00 SR4SR0 = 00H
Figure 38 shows the various operations under the control of Mode Register 0. This register can be read from as well as written to.
MR07 MR06 MR05 MR04 MR03 MR02 MR01 MR00
CHROMA FILTER SELECT MR07 MR06 MR05 0 0 0 1.3 MHz LOW-PASS FILTER 0 0 1 0.65 MHz LOW-PASS FILTER 0 1 0 1.0 MHz LOW-PASS FILTER 0 1 1 2.0 MHz LOW-PASS FILTER 1 0 0 RESERVED 1 0 1 CIF 1 1 0 QCIF 1 1 1 RESERVED
OUTPUT VIDEO STANDARD SELECTION MR01 MR00 0 0 NTSC 0 1 PAL (B, D, G, H, and I) 1 0 PAL (M) 1 1 RESERVED LUMA FILTER SELECT MR04 MR03 MR02 0 0 0 LOW-PASS FILTER (NTSC) 0 0 1 LOW-PASS FILTER (PAL) 0 1 0 NOTCH FILTER (NTSC) 0 0 1 NOTCH FILTER (PAL) 1 0 0 EXTENDED MODE 1 0 1 CIF 1 1 0 QCIF 1 1 1 RESERVED
MR02MR04 MR05MR07
Rev. A | Page 28 of 52
02980-A-037
ADV7174/ADV7179
MODE REGISTER 1 (MR1)
Bits: Address: MR17MR10 SR4SR0 = 01H
Figure 39 shows the various operations under the control of Mode Register 1. This register can be read from as well as written to.
MR17 MR16 MR15 MR14 MR13 MR12 MR11 MR10
CLOSED CAPTIONING FIELD SELECTION MR12 MR11 0 0 1 1 0 1 0 1 NO DATA OUT ODD FIELD ONLY EVEN FIELD ONLY DATA OUT (BOTH FIELDS) INTERLACE CONTROL MR10 0 INTERLACED 1 NONINTERLACED
02980-A-039
Rev. A | Page 29 of 52
ADV7174/ADV7179
MODE REGISTER 2 (MR2)
Bits: Address: MR27MR20 SR4SR0 = 02H
Mode Register 2 is an 8-bit-wide register. Figure 40 shows the various operations under the control of Mode Register 2. This register can be read from as well as written to.
MR27 MR26 MR25 MR24 CHROMINANCE CONTROL MR24 DISABLE ENABLE 0 1 ENABLE COLOR DISABLE COLOR MR23 MR22 MR21 MR20
GENLOCK CONTROL MR22 MR21 x 0 1 0 1 1 DISABLE GENLOCK ENABLE SUBCARRIER RESET PIN ENABLE RTC PIN SQUARE PIXEL CONTROL MR20 0 1 DISABLE ENABLE
0 1
MR23
Rev. A | Page 30 of 52
02980-A-039
ADV7174/ADV7179
MODE REGISTER 3 (MR3)
Bits: Address: MR37MR30 SR4SR0 = 03H
Mode Register 3 is an 8-bit-wide register. Figure 41 shows the various operations under the control of Mode Register 3.
MR37 MR36 MR35 MR34 MR33 MR32 MR31 MR30
DAC OUTPUT
02980-A-040
DAC B
DAC C
DAC Output Chroma Output Select Teletext Enable TTXREQ Bit Mode Control Input Default Color
CVBS: Composite Video Baseband Signal Y: Luminance Component Signal (For YPbPr or Y/C Mode) C: Chrominance Signal (For Y/C Mode) Pb: ColorComponent Signal (For YPbPr Mode) Pr: Color Component Signal (For YPbPr Mode) R: RED Component Video (For RGB Mode) G: GREEN Component Video (For RGB Mode) B: BLUE Component Video (For RGB Mode)
Each DAC can be powered on or off individually See MR1 Description and Figure 39.
Rev. A | Page 31 of 52
ADV7174/ADV7179
MODE REGISTER 4 (MR4)
Bits: Address: MR47MR40 SR4SR0 = 04H
Mode Register 4 is an 8-bit-wide register. Figure 42 shows the various operations under the control of Mode Register 4.
MR47 MR46 MR45 MR44 MR43 MR42 MR41 MR40
0 1
DISABLE ENABLE
0 1
DISABLE ENABLE
0 1
MR44 MR45
MR46
Reserved
MR47
Rev. A | Page 32 of 52
02980-A-041
RGB/YUV CONTROL
ADV7174/ADV7179
TIMING MODE REGISTER 0 (TR0)
Bits: Address: TR07TR00 SR4SR0 = 07H
Figure 43 shows the various operations under the control of Timing Register 0. This register can be read from as well as written to.
TR07 TR06 TR05 TR04 TR03 TR02 TR01 TR00
BLANK INPUT CONTROL TR03 0 1 ENABLE DISABLE TIMING MODE SELECTION TR02 TR01 0 0 1 1 0 1 0 1 MODE 0 MODE 1 MODE 2 MODE 3
LUMA DELAY TR05 TR04 0 0 1 1 0 1 0 1 0ns DELAY 74ns DELAY 148ns DELAY 222ns DELAY
Rev. A | Page 33 of 52
02980-A-042
ADV7174/ADV7179
TIMING MODE REGISTER 1 (TR1)
Bits: Address: TR17TR10 SR4SR0 = 08H
Timing Register 1 is an 8-bit-wide register. Figure 44 shows the various operations under the control of Timing Register 1. This register can be read from as well written to. This register can be used to adjust the width and position of the master mode timing signals.
TR17 TR16 TR15 TR14 TR13 TR12 TR11 TR10
HSYNC TO PIXEL DATA ADJUST TR17 TR16 0 0 1 1 0 1 0 1 0 TPCLK 1 TPCLK 2 TPCLK 3 TPCLK
HSYNC TO FIELD RISING EDGE DELAY (MODE 1 ONLY) TR15 TR14 x x 0 1 TC TB TB + 32s
VSYNC WIDTH (MODE 2 ONLY) TR15 TR14 0 0 1 1 TIMING MODE 1 (MASTER/PAL) LINE 1 HSYNC TA TB FIELD/VSYNC TC LINE 313 LINE 314 0 1 0 1 1 TPCLK 4 TPCLK 16 TPCLK 128 TPCLK
Rev. A | Page 34 of 52
02980-A-043
ADV7174/ADV7179
SUBCARRIER FREQUENCY REGISTERS 30
Bits: Address: FSC3FSC0 SR4SR00 = 09H0CH
These 8-bit-wide registers are used to set up the subcarrier frequency. The value of these registers is calculated by using the following equation:
No. of Subcarrier Frequency Values in One Line of Video Line 32 2 * No. of 27 MHz Clock Cycles in One Video Line
* Rounded to the nearest integer.
Note that on power-up, FSC Register 0 is set to 16h. A value of 1E as derived above is recommended. Program as FSC Register 0: 1EH FSC Register 2: 7CH FSC Register 3: F0H FSC Register 4: 21H Figure 45 shows how the frequency is set up by the four registers.
SUBCARRIER FREQUENCY REG 3 SUBCARRIER FREQUENCY REG 2 SUBCARRIER FREQUENCY REG 1 SUBCARRIER FREQUENCY REG 0 FSC31 FSC30 FSC29 FSC28 FSC27 FSC26 FSC25 FSC24
FSC16
FSC11 FSC10
FSC9
FSC8
02980-A-044
FSC7
FSC6
FSC5
FSC4
FSC3
FSC2
FSC1
FSC0
This 8-bit-wide register is used to set up the subcarrier phase. Each bit represents 1.41. For normal operation, this register is set to 00H.
These 8-bit-wide registers are used to set up the closed captioning extended data bytes on even fields. Figure 46 shows how the high and low bytes are set up in the registers.
002980-A-045
BYTE 1
CED9
CED8
BYTE 0
CED7
CED6
CED5
CED4
CED3
CED2
CED1
CED0
Rev. A | Page 35 of 52
ADV7174/ADV7179
CLOSED CAPTIONING ODD FIELD DATA REGISTERS 10
Bits: Subaddress: CCD15CCD0 SR4SR0 = 10H11H
These 8-bit-wide registers are used to set up the closed captioning data bytes on odd fields. Figure 47 shows how the high and low bytes are set up in the registers.
002980-A-046 02980-A-048 02980-A-047
BYTE 1
CCD9
CCD8
BYTE 0
CCD7
CCD6
CCD5
CCD4
CCD3
CCD2
CCD1
CCD0
These 8-bit-wide registers are used to enable the NTSC pedestal/ PAL Teletext on a line-by-line basis in the vertical blanking interval for both odd and even fields. Figure 48 and Figure 49 show the four control registers. A Logic 1 in any of the bits of these registers has the effect of turning the pedestal off on the equivalent line when used in NTSC. A Logic 1 in any of the bits of these registers has the effect of turning Teletext on the equivalent line when used in PAL.
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 FIELD 1/3 PCO7 PCO6 PCO5 PCO4 PCO3 PCO2 PCO1 PCO0
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 FIELD 1/3 PCO15 PCO14 PCO13 PCO12 PCO11 PCO10 PCO9 PCO8
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 FIELD 2/4 PCE7 PCE6 PCE5 PCE4 PCE3 PCE2 PCE1 PCE0
FIELD 2/4
PCE15
PCE14
PCE13
PCE12
PCE11
PCE10
PCE9
PCE8
LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9 FIELD 1/3 TXO7 TXO6 TXO5 TXO4 TXO3 TXO2
LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15 FIELD 1/3 TXO15 TXO14 TXO13 TXO12 TXO11 TXO10 TXO9 TXO8
LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9 FIELD 2/4 TXE7 TXE6 TXE5 TXE4 TXE3 TXE2
LINE 8 TXE1
LINE 7 TXE0
LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15 FIELD 2/4 TXE15 TXE14 TXE13 TXE12 TXE11 TXE10 TXE9 TXE8
Rev. A | Page 36 of 52
ADV7174/ADV7179
TELETEXT REQUEST CONTROL REGISTER (TC07)
Bits: Address: TC07TC00 SR4SR0 = 19H
Teletext control register is an 8-bit-wide register (see Figure 50). Table 17. Teletext Request Control Register
Bit Name TTXREQ Rising Edge Control Bit No. TC07TC04 Description These bits control the position of the rising edge of TTXREQ. It can be programmed from 0 CLOCK cycles to a maximum of 15 CLOCK cycles (see Figure 50). These bits control the position of the falling edge of TTXREQ. It can be programmed from zero CLOCK cycles to a max of 15 CLOCK cycles. This controls the active window for Teletext data. Increasing this value reduces the amount of Teletext bits below the default of 360. If Bits TC03TC00 are 00H when Bits TC07 TC04 are changed, the falling edge of TTXREQ tracks that of the rising edge, i.e., the time between the falling and rising edge remains constant (see Figure 49).
TC03TC00
CGMS_WSS Register 0 is an 8-bit-wide register. Figure 51 shows the operations under the control of this register.
TC07 TC06 TC05 TC04 TC03 TC02 TC01 TC00
TTXREQ RISING EDGE CONTROL TC07 TC06 0 0 " 1 1 0 0 " 1 1 TC05 TC04 0 0 " 1 1 0 1 " 0 1 0 PCLK 1 PCLK " PCLK 14 PCLK 15 PCLK
TTXREQ FALLING EDGE CONTROL TC03 TC02 0 0 " 1 1 0 0 " 1 1 TC01 TC00 0 0 " 1 1 0 1 " 0 1 0 PCLK 1 PCLK " PCLK 14 PCLK 15 PCLK
C/W06
C/W04
C/W03
C/W02
C/W01
C/W00
CGMS Odd Field Control CGMS Even Field Control WSS Control
02980-A-050
02980-A-049
ADV7174/ADV7179
CGMS_WSS REGISTER 1 (C/W1)
Bits: Address : C/W17C/W10 SR4SR0 = 17H
CGMS_WSS Register 1 is an 8-bit-wide register. Figure 52 shows the operations under the control of this register.
C/W17 C/W16 C/W15 C/W14 C/W13 C/W12 C/W11 C/W10
02980-A-051
CGMS_WSS Register 2 is an 8-bit-wide register. Figure 53 shows the operations under the control of this register.
C/W27 C/W26 C/W25 C/W24 C/W23 C/W22 C/W21 C/W20
02980-A-052
Rev. A | Page 38 of 52
POWER PLANES
The ADV7174/ADV7179 and any associated analog circuitry should have its own power plane, referred to as the analog power plane (VAA). This power plane should be connected to the regular PCB power plane (VCC) at a single point through a ferrite bead. This bead should be located within 3 inches of the ADV7174/ADV7179. The metallization gap separating the device power plane and board power plane should be as narrow as possible to minimize the obstruction to the flow of heat from the device into the general board. The PCB power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all ADV7174/ADV7179 power pins and voltage reference circuitry. Plane-to-plane noise coupling can be reduced by ensuring that portions of the regular PCB power and ground planes do not overlay portions of the analog power plane unless they can be arranged so that the plane-to-plane noise is common mode.
GROUND PLANES
The ground plane should encompass all ADV7174/ADV7179 ground pins, voltage reference circuitry, power supply bypass circuitry for the ADV7174/ADV7179, the analog output traces, and all the digital signal traces leading up to the ADV7174/ ADV7179. The ground plane is the boards common ground plane.
POWER SUPPLY DECOUPLING FOR EACH POWER SUPPLY GROUP 0.1F 3.3V (VAA) 0.1F 3.3 V (VAA) 10F 0.1F
23 30
COMP VREF
VAA
ADV7174/ADV7179
35, 3539 3.3 V (VAA) 4k RESET 100nF UNUSED INPUTS SHOULD BE GROUNDED
32 13 14
P7P0
DAC C 24 75
DAC B 28 75
3.3 V (VCC) 5k
3.3 V (VCC) 5k
TTXREQ 100k 3.3 V (VAA) TELETEXT PULL-UP AND PULL-DOWN RESISTORS SHOULD ONLY BE USED IF THESE PINS ARE NOT CONNECTED 27MHz CLOCK (SAME CLOCK AS USED BY MPEG2 DECODER) 10k
33 TTXREQ 1
MPU BUS
CLOCK ALSB
16
Rev. A | Page 39 of 52
02980-A-053
ADV7174/ADV7179
SUPPLY DECOUPLING
For optimum performance, bypass capacitors should be installed using the shortest leads possible, consistent with reliable operation, to reduce the lead inductance. Best performance is obtained with 0.1 F ceramic capacitor decoupling. Each group of VAA pins on the ADV7174/ADV7179 must have at least one 0.1 F decoupling capacitor to GND. These capacitors should be placed as close to the device as possible. It is important to note that while the ADV7174/ADV7179 contains circuitry to reject power supply noise, this rejection decreases with frequency. If a high frequency switching power supply is used, the designer should pay close attention to reducing power supply noise and consider using a 3-terminal voltage regulator for supplying power to the analog power plane.
D CLOCK CK
Q D CK Q 13.5MHz
HSYNC
Rev. A | Page 40 of 52
02980-A-054
10.5 0.25s
D0D6
50 IRE
D0D6
BYTE 0 40 IRE REFERENCE COLOR BURST (9 CYCLES) FREQUENCY = FSC = 3.579545MHz AMPLITUDE = 40 IRE 10.003s 27.382s 33.764s
BYTE 1
Rev. A | Page 41 of 52
02980-A-055
Word 1 Word 2
100 IRE REF 70 IRE C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 CRC SEQUENCE
40 IRE
Rev. A | Page 42 of 52
500mV W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 RUN-IN SEQUENCE START CODE ACTIVE VIDEO
Rev. A | Page 43 of 52
TELETEXT PROTOCOL
The relationship between the TTX bit clock (6.9375 MHz) and the system clock (27 MHz) for 50 Hz is
27 MHz 4 = 6.75 MHz 6.9375 106 6.75 106 = 1.027777
Thus, 37 TTX bits correspond to 144 clocks (27 MHz) and each bit has a width of almost four clock cycles. The ADV7174/ ADV7179 uses an internal sequencer and variable phase interpolation filter to minimize the phase jitter and thus generate a band-limited signal that can be output on the CVBS and Y outputs. At the TTX input, the bit duration scheme repeats after every 37 TTX bits or 144 clock cycles. The protocol requires that TTX Bits 10, 19, 28, and 37 are carried by three clock cycles and all other bits by four clock cycles. After 37 TTX bits, the next bits with three clock cycles are 47, 56, 65, and 74. This scheme holds for all following cycles of 37 TTX bits until all 360 TTX bits are completed. All Teletext lines are implemented in the same way. Individual control of Teletext lines is controlled by Teletext setup registers.
RUN-IN CLOCK
tSYNTTXOUT
CVBS/Y
tPD
HSYNC 10.2s TTXDATA TTXDEL TTXREQ PROGRAMMABLE PULSE EDGES TTXST
tPD
02980-A-058
Rev. A | Page 44 of 52
02980-A-059
100 IRE
REF WHITE
1048.4mV
714.2mV
02980-A-060
100 IRE
REF WHITE
1048.4mV
714.2mV 7.5 IRE 0 IRE 40 IRE BLACK LEVEL BLANK LEVEL SYNC LEVEL 387.6mV 334.2mV 48.3mV
PEAK CHROMA
BLANK/BLACK LEVEL
0mV
100 IRE
REF WHITE
1052.2mV
720.8mV 7.5 IRE 0 IRE 40 IRE BLACK LEVEL BLANK LEVEL SYNC LEVEL 387.5mV 331.4mV 45.9mV
Rev. A | Page 45 of 52
02980-A-063
02980-A-062
335.2mV
PEAK CHROMA
02980-A-061
ADV7174/ADV7179
NTSC WAVEFORMS (WITHOUT PEDESTAL)
130.8 IRE PEAK COMPOSITE 1289.8mV
100 IRE
REF WHITE
1052.2mV
100 IRE
REF WHITE
1052.2mV
714.2mV
0 IRE 40 IRE
338mV 52.1mV
PEAK CHROMA
BLANK/BLACK LEVEL
299.3mV
PEAK CHROMA
0mV
100 IRE
REF WHITE
1052.2mV
715.7mV
0 IRE 40 IRE
336.5mV 51mV
Rev. A | Page 46 of 52
ADV7174/ADV7179
PAL WAVEFORMS
989.7mV 672mV (p-p) BLANK/BLACK LEVEL PEAK CHROMA
317.7mV
PEAK CHROMA
02980-A-068
0mV
1047mV
REF WHITE
696.4mV
02980-A-069
350.7mV 50.8mV
PEAK CHROMA
BLANK/BLACK LEVEL
317.7mV
PEAK CHROMA
02980-A-070
0mV
1050.2mV
REF WHITE
698.4mV
351.8mV 51mV
Rev. A | Page 47 of 52
02980-A-071
ADV7174/ADV7179
Pb Pr WAVEFORMS
MAGENTA YELLOW GREEN BLACK WHITE CYAN BLUE RED
YELLOW
GREEN
0mV
0mV
BLACK
+505mV
WHITE
MAGENTA
CYAN
BLUE
RED
0mV 82mV
0mV
171mV
334mV
02980-A-072 02980-A-075
423mV 505mV
05mV
RED
YELLOW
+467mV
MAGENTA
GREEN
0mV
0mV
BLACK
0mV
WHITE
CYAN
0mV 76mV
158mV
309mV
02980-A-073
BLUE
RED
391mV 467mV
467mV
RED
MAGENTA
YELLOW
GREEN
WHITE
CYAN
BLUE
+350mV
BLACK
RED
0mV
0mV
0mV 57mV
0mV
118mV
232mV
02980-A-074
293mV 350mV
350mV
Rev. A | Page 48 of 52
02980-A-077
02980-A-076
0 10 20
MAGNITUDE (dB)
30 40 50 60 70 80 100k
02980-A-079
75
270pF
330pF
Z0 = 75 75
1M
100M
Rev. A | Page 49 of 52
switched off. In the examples shown, the timing mode is set to Mode 0 in slave format. TR02TR00 of the Timing Register 0 control the timing modes. For a detailed explanation of each bit in the command registers, refer to the Register Programming section. TR07 should be toggled after setting up a new timing mode. Timing Register 1 provides additional control over the position and duration of the timing signals. In the examples, this register is programmed in default mode.
Rev. A | Page 50 of 52
ADV7174/ADV7179
Table 26. PAL-60 (FSC = 4.43361875 MHz)
Address 00H 01H 02H 03H 04H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H Description Mode Register 0 Mode Register 1 Mode Register 2 Mode Register 3 Mode Register 4 Timing Register 0 Timing Register 1 Subcarrier Frequency Register 0 Subcarrier Frequency Register 1 Subcarrier Frequency Register 2 Subcarrier Frequency Register 3 Subcarrier Phase Register Closed Captioning Ext Register 0 Closed Captioning Ext Register 1 Closed Captioning Register 0 Closed Captioning Register 1 Pedestal Control Register 0 Pedestal Control Register 1 Pedestal Control Register 2 Pedestal Control Register 3 CGMS_WSS Register 0 CGMS_WSS Register 1 CGMS_WSS Register 2 Teletext Request Control Register Data 04H 10H 00H 00H 00H 00H 00H CBH 8AH 09H 2AH 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H
On power-up, this register is set to 16h. 1Eh should be written here for correct FSC.
Rev. A | Page 51 of 52
PIN 1 INDICATOR
TOP VIEW
5.75 BSC SQ
BOTTOM VIEW
21 20 10 11
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08
SEATING PLANE
Figure 81. 40-Lead Lead Frame Chip Scale Package [LFCSP] (CP-40) Dimensions shown in millimeters
Note that the exposed metal paddle on the bottom side of the LFCSP package must be soldered to PCB ground for proper heat dissipation and also for noise and mechanical strength benefits.
ORDERING GUIDE
Model ADV7179KCP ADV7179KCP-REEL ADV7179BCP ADV7179BCP-REEL ADV7174KCP ADV7174KCP-REEL ADV7174BCP ADV7174BCP-REEL EVAL-ADV7179EBM EVAL-ADV7174EBM Temperature Range 0C to 70C 0C to 70C 40C to +85C 40C to +85C 0C to 70C 0C to 70C 40C to +85C 40C to +85C Package Description Lead Frame Chip Scale Package Lead Frame Chip Scale Package Lead Frame Chip Scale Package Lead Frame Chip Scale Package Lead Frame Chip Scale Package Lead Frame Chip Scale Package Lead Frame Chip Scale Package Lead Frame Chip Scale Package Evaluation Board Evaluation Board Package Option CP-40 CP-40 CP-40 CP-40 CP-40 CP-40 CP-40 CP-40
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C0298002/04(A)
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