Analog and Mixed signal Design

Advanced VLSI design Lab IIT Kharagpur

Activity: Ultra Wideband Differential Operational Amplifier. Team Members:

Amal Kumar Kundu (amal.kundu@gmail.com), Dr. T.K. Bhattacharyya. (tkb@ece.iitkgp.ernet.in) Sponsoring Organization: AVLSI Consortium, IIT Kharagpur.

Compensation Ckt

ViP ViN

+ Diff I/P - +
CMFB

+ AB Class O/P - +
Compensation Ckt

VoP

VoN

_
Error Amp

CMS Vcmr
Silicon Result: Closed loop Gain = 12 Frequency = 20 MHz

The two stage Operational amplifier provides high DC gain, differential Output ultra wide band width and rail to rail output swing. The output stage is a class AB amplifier with a unique pole zero cancellation and transconductance doubling features. This output stage provides a unity gain bandwidth of 1.43 times than that of normal common source output stage for the same peak current and load specification.

Power consumption: 23 mA Input Ref. Noise: 2.95 nV/sqrt(Hz) VINCM = VOCM = 900 mV

DC Gain = 60 dB UGB = 3.12 GHz PM = 55 degree

AVLSI Lab, IIT Kharagpur.

Activity: A 1.6GS/s 20mW 4bit Flash ADC with Wallace Tree Encoder in 0.18u Digital CMOS process. Team Member : Ramen Dutta (dutta.ramen@gmail.com) Dr T.K.Bhattacharyya (tkb@ece.iitkgp.ernet.in)

Motivation & Application:

This is a high speed low power low resolution ADC for Ultra Wide Band (UWB) and high speed link application. Conversion speed critical in these applications and thus higher sampling frequency is a must for the ADC where as the resolution of 4 bit is acceptable. One other constraint comes in terms of power as we are going towards high level of integration. Target for this design was to design a low power ADC meeting the speed requirement of these applications.

Brief Summary:
Simulation shows that this ADC is operational upto maximum sampling frequency of 1.6GS/s and Consumes power about 20mW at that frequency. For a input frequency of 100MHz, SNDR achieved is 23.6dB at the post layout simulation. This overall result gives a Figure Of Merit (FoM) of 1.2pJ/conversion. The ADC incorporated a low power comparator which is the key to reduce the power consumption. The Wallace tree encoder used other than the conventional encoder to minimized bubble errors. High Speed latches are incorporated to get a pipelined operation which increases throughput. Post layout simulation on Extreme corner shows that the non-linearity errors, DNL and INL are within 0.5LSB and 0.7LSB respectively. ADC core are is 180um x 260 um True Single Phase Circuit(TSPC) flipflop is used for pipelining digital data to get rid of CLK skew and minimize area.

ADC architecture

Wallace Lab, IIT Kharagpur. Tree Encoder AVLSI

Activity: TIA-Equalizer for High Speed Optical Link Team Members: Saurav Bandyopadhyay, Prof. Pradip Mandal Sponsored by: National Semiconductor, Santa Clara, CA

Brief Summary:
Our objective is to make a cheap high speed optical link. This involves the use of slow or bandwidth limiting Photo-diodes. To overcome this problem, we use an equalizer which enhances the bandwidth of the system thereby making it even 6Gbps possible over a slow system.
Data Input VCSEL Photo-Diode Clock & Data Recovery

Features: Integrated TIA-Equalizer Implementation on 0.18um Digital CMOS process Having variable bit rate equalizer( 1Gbps6Gbps)

Fiber

Laser Driver

TIA

Equalizer

TIA
First Stage: Inductive Peaking

Negative Capacitor

Negative Capacitor

Peaking Adjustment Circuit

Second Stage: High Bandwidth Stage

Post Amp

Input and Output EyeDiagrams for 4Gbps

Input and Output Eye-Diagrams for 6Gbps

AVLSI Lab, IIT Kharagpur.

Activity: An OTA-C cell having optimum phase response For Continuous Time Filters Team Members : Kshitij Yadav, Dr. Pradip Mandal, Prof. K.D. Pedrotti

We propose an OTA-C topology, suitable for high speed applications. In this topology the tuning circuit is separated from the main amplifier, which enables reduction in the number of stack transistors and hence, makes the circuit suitable for sub-micron technology. While smaller devices provide better speed, their larger channel length modulation makes the phase response more sensitive to the operating point and hence, to the Gm tuning point. A sizing guideline is adopted that helps to get an optimal frequency response over a large tuning range. The circuit was designed in a .18u CMOS technology. The phase error variation is within .5 degrees as the unity-gain frequency is tuned from 250MHz to 1GHz.

List of Publications:
[1] Kshitij Yadav and K.D. Pedrotti "Investigation of the High Frequency Operation of Gm-C Integrators for Continuous Time Filters" in Proceedings IEEEs International Conference on Communication Circuits and Systems (ICCCAS), China, June 2006, vol. 4, pp. 2332-2336. [2] Kshitij Yadav and Pradip Mandal "A VHF OTA-C Topology Having Low Phase Error With Gm Tuning" in Proceedings IEEEs International conference on communication, circuits and systems (ICCCAS), China, June 2006, vol. 4, pp. 2327-2331. [3] Kshitij Yadav and Pradip Mandal "Design and analysis of a VHF OTA-C cell for optimum phase response" in Proceedings IEEEs Asia pacific conference on circuits and systems (APCCAS 06), Singapore, December 2006.
AVLSI Lab, IIT Kharagpur.