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Objective Part A:
To learn to create transistor level schematics using Composer, to create structural (gate and transistor level) and functional descriptions of elementary and complex logic functions in a hierarchical system, and to use Verilog-XL simulations to verify functional behavior.
Background Part A:
There are many hierarchies and levels of abstraction in VLSI design into which one could start his/her initial efforts in using the Cadence CAD toolset they range from high-level system design to transistor-level circuit layout. We choose to begin your journey in using Cadence with logic synthesis and simulation. Logic design is an important early step in VLSI circuit design. Verilog-XL is a high-level logic simulation tool available within Cadence that allows the designer to verify the behavior of the circuit in orders of magnitude less time than using circuit level simulators such as SPICE and SPECTRE. This is especially evident when the project being simulated is a complex logic design comprised of many interconnected gates. Furthermore VerilogXL gives the designer a higher level of abstraction to work with than circuit level simulators provide. If you completed the Cadence Tutorial you have created functional, transistor and gate level descriptions for the CMOS inverter using the Cadence schematic entry tool Composer. In this first Cadence lab we will focus on advancing your experience with developing structural and functional descriptions of logic functions suited for hierarchical design, We will also provide you with opportunities to experience the flexibility and power of Verilog-XL as a logic system simulator. Let's start with the functional view of your inverter module inv (out, in), or use the functional description in the Cadence Tutorial section Creating a Behavioral Model for an Inverter. In this functional description replace the line with not (strong1, strong0) #1 (out, in); The modier (strong1, strong0), informs Verilog-XL that the outputs of the inverter will have strengths strong for 1 and 0. The #1 informs Verilog-XL to delay the output by one time unit. The gate strength options, in order of decreasing strength, are as follows: supply, strong, pull, large, weak, medium, small For complementary CMOS gates the output strengths for logic 1 and 0 will always be strong. Strength specications will be useful when simulating circuits where race conditions need to be resolved. The Verilog-XL primitives for elementary logic gates AND, OR, NAND, NOR, XOR, XNOR are and, or, nand, nor, xor, xnor. An illustrative Verilog-XL example is provided at the ESE570 website. not (out, in);
Objective Part B:
Using the inverter and gates created in Part A as cells, develop gate and transistor level schematics schematics using Composer and functional descriptions for two-phase static and dynamic flip-flop circuits.
Background Part B:
A dynamic D ip-op is shown in Fig. 1 where clk and clkP are two-phase nonoverlapping clocks and clkp and clkPp are their complements, respectively. Variable d is the input and q is the output. The two phases of the input clock clk and clkP can be generated from the circuit in Fig. 2. An important thing to notice is that the inverter in Fig. 2 serves as a delay element, so its Verilog model must also have a delay.
Figure 1 Dynamic D Flip-flop The Verilog primitive for the CMOS transmission gate is cmos and the input and output arguments are (output, input, clock, clockbar), where clock = clk and clockbar = clkP. The first inverters input will be will be the value of d when clk = 1. However, when clk = 0, there is no logic level at the input to the first inverter because the CMOS transmission gate is off and the d input is disconnected from the circuit. In a real transistor implementation there will be parasitic capacitance that maintains charge and keeps the logic level at the value it was just prior to the CMOS transmission gate turning off, albeit it will eventually leak (or decay) to zero if not refreshed or updated.
In Verilog high impedance or high-Z and physical capacitors are not defined which makes it difficult to model transmission gates and dynamic logic with out some help. Verilog provides the help by modeling this behavior using the declaration trireg (strengtha) #(x, y, z) nodename, where nodename in this case is the node for the input of the first inverter, x, y, z refer to rise delay, fall delay and charge decay time, respectively. This statement effectively attaches a capacitor-like storage element between the node and ground.
Figure 2 Two-phase Non-Overlapping Clock Generator If the dynamic D flip-flop in Fig. 1 does not receive any clock pulse for a long period of time, in fact just enough time for all the charge on the parasitic capacitance to decay to zero, the output will give an erroneous logical state. A static D flip-flop, such as that shown in Fig. 3, does not suffer from this issue.
qm
qs
Figure 3 Static D Flip-Flop The static D flip-flop in Fig. 3 is sometimes referred to as master-slave static D flip-flop where the first stage is the master stage with output qm and second is the slave stage with output qs .