PART -A INTRODUCTION TO ELECTRONIC CIRCUITS EXPERIMENT 1 (a) CLIPPING AND CLAMPING CIRCUITS AIM: To study the working of positive

e clipper, double ended clipper and positive clamper using diodes. COMPONENTS REQUIRED: Diode (IN914 / IN4007), Resistors-1 K & 100k , DC regulated power supply (for Vref), Signal generator (for Vi) and CRO. 1. POSITIVE CLIPPER: CIRCUIT DIAGRAM Fig.1 a Positive clipper Circuit b. Transfer Characteristics

THEORY: Clippers clip off a portion of the input signal without distorting the remaining part of the waveform. In the positive clipper shown above the input waveform above Vref is clipped off. If Vref = 0V, the entire positive half of the input waveform is clipped off. Plot of input Vi (along X-axis) versus output Vo (along Y-axis) called transfer characteristics of the circuit can also be used to study the working of the clippers. For stiff clipper: 100RB < RS< 0.01RL, Where RB is bulk resistance of the diode. For diode IN914, value of RB is 30 .Series resistor RS must be 100times greater than bulk resistance RB and 100 times smaller than load resistance RL. If RB=30 , select RS=1k and RL=100k . PROCEDURE: 1. Before making the connections check all components using multi-meter. 2. Make the connections as shown in circuit diagram. 3. Using a signal generator (Vi) apply a sine wave of 1KHz frequency and a peak-topeak amplitude of 10V to the circuit. (Square wave can also be applied.) 4. Keep the CRO in dual mode, connect the input (Vi) signal to channel 1 and output waveform (Vo) to channel 2. Observe the clipped output waveform which is as shown in fig. 2. Also record the amplitude and time data from the waveforms. 5. Now keep the CRO in X-Y mode and observe the transfer characteristic waveform.

Note: 1. Vary Vref and observe the variation in clipping level. For this use variable DC power supply for Vref. 2. Change the direction of diode and Vref to realize a negative clipper. 3. For double-ended clipping circuit, make the circuit connections as shown in fig.3 and the output waveform observed is as shown in figure 5. 4. Adjust the ground level of the CRO on both channels properly and view the ouput in DC mode (not in AC mode) for both clippers and clampers. INPUT AND OUTPUT WAVEFORMS

Fig.2. Input and output waveform for positive Clipper RESULT: Output voltage V0 =__________ during positive half cycle =__________ during negative half cycle 2. DOUBLE ENDED CLIPPER: CIRCUIT DIAGRAM

Fig.3 Double ended clipper Circuit b. Transfer Characteristics Apply Vi = 10 Vpp at 1kHz V1= 2V V2= -2V INPUT AND OUTPUT WAVE FORMS

Fig.4. Input and output waveform for double-ended clipping circuit RESULT: Output voltage V0 =__________ during positive half cycle =__________ during negative half cycle Note: The above clipper circuits are realized using the diodes in parallel with the load (at the output), hence they are called shunt clippers. The positive (and negative) clippers can also be realized in the series configuration wherein the diode is in series with the load. These circuits are called series clippers. 3. POSITIVE CLAMPER COMPONENTS REQUIRED: Diode (IN 914/BY-127), Resistor of 100 K , Capacitor 0.1 F, DC regulated power supply, Signal generator, CRO

Fig. 5: Positive Clamper THEORY: The clamping network is one that will clamp a signal to a different DC level. The network must have a capacitor, a diode and a resistive element, but it can also employ an independent DC supply (Vref) to introduce an additional shift. The magnitude of R and C must be chosen such that time constant = RLC is large enough to ensure the voltage across capacitor does not discharge significantly during the interval of the diode is non-conducting.

DESIGN: For proper clamping, >100T where T is the time period of input waveform If frequency is 1 kHz with peak-peak input voltage of 10V, T=1ms =RL.C=100T = 100ms Let C=1F RL=
-3

10010 =100kO -6 110 Select C =1uF and RL=100 kO PROCEDURE: 1 2 Before making the connections check all components using multimeter. Make the connections as shown in circuit diagram (fig. 5).

3 Using a signal generator apply a square wave input (Vi) of peak-to-peak amplitude of 10V (and frequency greater than 50Hz) to the circuit. (Sine wave can also be applied) 4 Observe the clamped output waveform on CRO which is as shown in Fig. 6.

Note: 1 For clamping circuit with reference voltage Vref, the output waveform is observed as shown in Fig. 7. For without reference voltage, Keep Vref = 0V. 2 CRO in DUAL mode and DC mode. Also the grounds of both the channels can be made to have the same level so that the shift in DC level of the output can be observed. 3 For negative clampers reverse the directions of both diode and reference voltage.

Fig.6: Input and output waveform for positive clamper without reference voltage.

Fig. 7 Input and output waveform for positive clamper circuit with reference voltage = 2V

RESULT: With Vref =0, output voltage V0=_________ With Vref =2, output voltage V0=_________

EXPERIMENT 2 (a) CE AMPLIFIER AIM: To determine the frequency response, input impedance, output impedance and bandwidth of a CE amplifier. COMPONENTS REQUIRED: Transistor SL-100, Resistors -33 K , 6.8 K , 470 , 2.2k , 10k Capacitors -47 F, 10 F, DC regulated power supply, Signal generator, CRO PROCEDURE: 1 Before making the connections check all components using multimeter. 2 3 Make the connections as shown in circuit diagram. Using a signal generator apply a sinusoidal input waveform of peak-to-peak amplitude 5mV (Vin) to the circuit and observe the output signal on the CRO. 4 Vary the frequency of input from 50Hz to 1MHz range and note down corresponding output voltage VO in the tabular column. Note: When the input frequency is being changed the input amplitude (i.e., around 20 mV) should remain constant. Adjust the amplitude of Vin (in mV) such that the output Vo does not get clipped (i.e., saturated) when the frequency is in the mid range say 1kHz. 5. After the frequency has been changed from 50 Hz to 1MHz and the readings are tabulated in a tabular column, calculate gain of the amplifier (in dB) using the formula, Gain in dB = 20 log 10 (Vo/Vin) Plot the graph of gain versus frequency on a semi log sheet and hence determine the bandwidth as shown in Fig. 3. Bandwidth = B = f2-f1 To find input impedance, set the input DRBI to a minimum value and DRBO to a maximum value (say, 10k) as shown in figure 2. Now apply an input signal using signal generator, say a sine wave whose peak-to-peak amplitude is 5mV with a frequency of 10KHz. Observe the output on CRO. Note this value of output with DRBI = 0 as V0max. Now increase the input DRBI value till the output voltage V0 = (1/2) V0max.The corresponding DRBI value gives input impedance. To find output impedance, set DRBO which is connected across the output to a maximum value as shown in figure 2, with the corresponding DRBI at the minimum position. Apply the input signal using signal generator, say a sine wave whose peak-topeak amplitude is 50mV with a frequency of 10 KHz. Observe the output on CRO. Note this value of output with DRBI = 0 as V0max. Now decrease the DRBO value till the output voltage V0 = (1/2) V0max. The corresponding DRBO value gives output impedance. Note: DRBI is connected between the signal generator and the input coupling capacitor. DRBO is connected across the output (across the CRO terminals). The ground symbol in the circuit diagram implies a common point. In some of the power supplies, there will be three terminals -+ (plus), -(minus) and GND (ground). Never connect this GND terminal to the circuit.

TABULAR COLUMN

CIRCUIT DIAGRAM:
f in Hz 50 Hz --1 MHz V0 P-P volts Vi = 5 mV (P-P) AV = V 0 Vi Power Gain = 20 log10 Av in dB

Values R1 = 33kO R2 = 6.8kO RC = 2.2kO RE = 470O RL= 10kO CC1 = CC2 =10F CE=47F Fig. 1: Transistor as a CE amplifier circuit diagram

Fig. 2: CE Amplifier with DRBs connected at both input and output

WAVEFORMS:

FREQUENCY RESPONSE:

Fig. 3 Frequency response plotted on semi log graph (X-axis is log scale)

THEORY: The frequency response of an amplifier is the graph of its gain versus the frequency. Fig. 3 shows the frequency response of an ac amplifier. In the middle range of frequencies, the voltage gain is maximum. The amplifier is normally operated in this range of frequencies. At low frequencies, the voltage gain decreases because the coupling (CC in Fig.1) and bypass (CE) capacitors no longer act like short circuits; instead some of the ac signal voltage is attenuated. The result is a decrease of voltage gain as we approach zero hertz. At high frequencies, voltage gain decreases because the internal (parasitic) capacitances across the transistor junctions provide bypass paths for ac signal. So as frequency increases, the capacitive reactance becomes low enough to prevent normal transistor action. The result is a loss of voltage gain. Cutoff frequencies (f1 & f2 in Fig. 3) are the frequencies at which the voltage gain equals 0.707 of its maximum value. It is also referred to as the half power frequencies because the load power is half of its maximum value at these frequencies. DESIGN: Given: VCC =10V , IC =2mA & B= 50, S =10 Assume VRE=VCC/10, VCE= VCC/2. Apply KVL to the output circuit of transistor. VCC=ICRC+ VCE+ VRE VRC= VCC-VRE -VCE =10-1-5 = 4v RC= VRC / IC = 2000 O. Select RC = 2.2kO. To find RE, let VRE = IE RE = (1/ 10) VCC = 1V, and IE =IC; Hence, RE = VCC / IE = VCC/ Ic= (1/2mA) = 500O. Choose RE = 470 O. Voltage across resistor R2 is VR2 = VCC R2 / R1 + R2 --------------------------------------------1 Stability factor S = 1+B/1+B (RE / RE + RB ) ------------------------2 Substitute all the values in the above equation and calculate RB. RB = 5.6k O. But RB = R1R2/R1+R2. ---------------------------------------------------3

From the circuit VR2 = VBE + VRE =0.7 V+1.0V = 1.7v From Eq 1 1.7V = 10* R2/R1+R2. --------------------------------------------------4 From Eq 3 RB = 5.6kO = R1R2/R1+R2. -------------------------------------------5 Using Equation 4&5 calculate R1 and R2 R1= 33kO R2 =6.8kO To find the bypass capacitor CE: Let XCE = RE/10 at f = 75Hz 1 R Hence X = Substituting all the values, CE =45 F. CE 2 fCE 10 Input impedance (Zi ) = RB || re` -3 -3 Wherere`=25mv/IE=25x10 /2x10 =22.7 O Out impedance (Z0) of the CE amplifier is the Thevenins impedance Zo = RC ||RL RESULT: 1. BANDWIDTH = ------Hz 2. INPUT IMPEDANCE =--O 3. OUTPUT IMPEDANCE =-O Note: Maximum gain occurs in mid frequency region. This is also called mid band gain. Gain-bandwidth product = Mid-band gain x Bandwidth
E

Choose CE =47 F and the coupling capacitors C C1 = CC2 = 10 F.

EXPERIMENT 3(a) CHARACTERISTICS OF AN ENHANCEMENT MODE MOSFET AIM: To determine the drain characteristics and Transconductance characteristics of an enhancement mode MOSFET. COMPONENTS REQUIRED: MOSFET (1RF 740), Resistor (1kO), Voltmeters (0 30V range and 0-10V range), Ammeter (0-25mA range) and Regulated power supply (2 nos. variable power supply) CIRCUIT DIAGRAM:

Enhancement MOSFET CHARACTERISTICS

Fig.2a: Drain Characteristics and 2b: Transconductance characteristics PROCEDURE: 1. Make the connections as shown in the corresponding circuit diagram. Special care to be taken in connecting the voltmeters and ammeters according to the polarity shown in circuit diagram.

2. Repeat the procedure for finding drain and Transconductance characteristics of Enhancement MOSFET. 1 2 Tabulate the readings in separate tabular columns as shown below. Plot the drain characteristics (ID versus VDS for different values of gate voltages VGS). Take ID along the Y-axis and VDS along the X-axis in the plot. characteristics find the drain resistance, RD = VDS / Id Similarly plot the transconductance charahcteristics with ID along the Y-axis and VGS long the X-axis in the graph for one value of VDS, say VDS= V. From this plot find the mutual conductance or transconductance = gm= I/VGS

3 4

8. Lastly find the amplification factor, rd . gm Procedure for finding the Tran conductance Characteristics: 1. Switch on the power supplies, with both V2 and V1 at zero voltage. 2. Initially set V1 =VGS = 0V. Now set V2 = VDS = 5V (constant). Vary the power supply V1 i.e., VGS and note down the corresponding current ID (in mA) (Simultaneously note down the VGS value from the voltmeter connected at the gate terminal). 3. Repeat the above procedure for a different value of VDS, say 10V. Note: In the above procedure VDS (i.e., the power supply V2) is kept constant and the power supply V1 (=VGS) is varied. Drain Characteristics: 1 Initially set V1 = VGS =4V (constant), slowly vary V2 and note down the corresponding current ID. Simultaneously note down in the tabular column the voltmeter reading VGS. 2 Repeat the above procedure for different values of VGS and note down the current ID for corresponding V1 = VDS. 3 Plot the graph of ID versus VDS for different values of gate voltages.

Note: In the above procedure VDS (i.e., the power supply V2) is varied and the power supply V1 (=VGS) is kept constant.

READINGS TABULATED IN TABULAR COLUMN Drain Characteristics VGS=+2V V DS ID (V) ma 02 ... . 10 VGS=+4V V DS ID (V) ma 02. ... 10 VGS=+6V
V DS

(V) 02. ... 10

ID ma

Transconductance Characteristics
VDS =5V VDS = 10 V

VGS Volts 0 . . . . . 10

ID ma

VGS Volts 0 . . . . . 10

ID ma

EXPERIMENT 4(a) SCHMITT TRIGGER AIM: To design and implement a Schmitt trigger circuit using op-amp for the given UTP and LTP values. COMPONENTS REQUIRED: IC A 741, Resistor of 10KO, 100KO, DC regulated power supply, Signal generator, CRO DESIGN: From theory of Schmitt trigger circuit using op-amp, we have the trip points, RV
UTP =
R 1 R2
R V given ref the 2
1 sat

RV

2 ref
R1

is the positive saturation of the opamp 90% of Vcc where Vsat

R2

Hence

LTP & UTP values to find the R1, R2& Vref values, the following design is
RV
1 sat

used. 2R2.Vref & =

LTP UTP + LTP= ------(1) R R1 R2 2RV 1 UTP-LTP= R2 1 R1 sat Design 1: Let Vsat

------(2) R1 R2 R2 =10V, UTP = 4V & LTP =2V, then equation (2) yields R2= 9R1
12

Let R1 = 10K , then R2= 90K=100k (UTP LTP)(R1 R2 ) From equation (1) Vref = = 3.33V 2R2 PROCEDURE: 1. Before doing the connections, check all the components using multimeter. 2. Make the connection as shown in circuit diagram.

3. Using a signal generator apply the sinusoidal input waveform of peak-to-peak amplitude of 10V, frequency 1 kHz. 4. Keep the CRO in dual mode; apply input (Vin) signal to the channel 1 and observe

the output (Vo) on channel 2 which is as shown in the waveform below. Note the amplitude levels from the waveforms. 5. Now keep CRO in X-Y mode and observe the hysteresis curve.

CIRCUIT DIAGRAM

Circuit Diagram of Schmitt Trigger Circuit WAVEFORMS

CRO in DUAL mode HYSTERISIS CURVE

CRO in X-Y mode showing the Hysteresis curve

THEORY: Schmitt Trigger converts an irregular shaped waveform to a square wave or pulse. Here, the input voltage triggers the output voltage every time it exceeds certain voltage levels called the upper threshold voltage VUTP and lower threshold voltage VLTP. The input voltage is applied to the inverting input. Because the feedback voltage is aiding the input voltage, the feedback is positive. A comparator using positive feedback is usually called a Schmitt Trigger. Schmitt Trigger is used as a squaring circuit, in digital circuitry, amplitude comparator, etc.

EXPERIMENT 5(a) OP-AMP AS A RELAXATION OSCILLATOR AIM: To design and implement a rectangular waveform generator (op-amp relaxation oscillator) for a given frequency. COMPONENTS REQUIRED: Op-amp A 741, Resistor of 1KO, 10KO, 20kO Potentiometer, Capacitor of 0.1 F, Regulated DC power supply, CRO. DESIGN: 1 The period of the output rectangular wave is given as T =2RC ln -------(1) R

1 Where, is the feedback fraction R1 R2 If R1 = R2, then from equation (1) we have T = 2RC ln(3) Another example, if R2=1.16 R1, then T = 2RC ----------(2) 11 Design for a frequency of 1
3

kHz (implies T= = 10- =1ms ) 3 f 10Use R2=1.16 R1, or equation (2) to be applied. Let R1 = 10kO, then R2 = 11.6kO (use 20kO potentiometer as shown in circuit figure) Choose next a value of C and then calculate value of R from equation (2). 3 T 10 -7 Let C=0.1F (i.e., 10 ), then R= = =5K . Select R=4.7KO 7 2C 2 10 R 1
V

The voltage across the capacitor has a peak voltage of Vc = sat R1 R2 PROCEDURE: 1. Before making the connections check all the components using multimeter. 2. Make the connections as shown in figure and switch on the power supply. 3. Observe the voltage waveform across the capacitor on CRO. 4. Also observe the output waveform on CRO. Measure its amplitude and frequency.

CIRCUIT DIAGRAM AND ACTUAL CONNECTIONS Values C=0.1F R1 =10kO, R2 = 11.6 kO,R = 4.7k/5.1kO

WAVEFORMS

RESULT: The frequency of the oscillations = ___ Hz. THEORY: Op-Amp Relaxation Oscillator is a simple Square wave generator which is also called as a Free running oscillator or Astable multivibrator or Relaxation oscillator. In this figure the op-amp operates in the saturation region. Here, a fraction (R1/ (R1+R2)) of output is fed back to the noninverting input terminal. Thus reference voltage is (R1/ (R1+R2)) Vo. And may take values as + (R1/ (R1+R2)) Vsat or -(R1/ (R1+R2)) Vsat. The output is also fed back to the inverting input terminal after integrating by means of a low-pass RC combination. Thus, whenever the voltage at inverting input terminal just exceeds reference voltage, switching takes place resulting in a square wave output.

EXPERIMENT 6(a) 5. ASTABLE MULTIVIBRATOR USING 555 TIMERS AIM: To design and implement an astable multivibrator using 555 Timer for a given frequency and duty cycle. COMPONENTS REQUIRED: 555 Timer IC, Resistors of 3.3KO, 6.8KO, Capacitors of 0.1 F, 0.01 F, Regulated power supply, CRO DESIGN: Given frequency (f) = 1 KHz and duty cycle = 60% (=0.6). The time period T =1/f = 1ms = tH + tL Where tH is the time the output is high and tL is the time the output is low. From the theory of astable multivibrator using 555 Timer (refer Malvino), we have tH = 0.693 RB C ------(1) tL = 0.693 (RA + RB)C ------(2) T = tH + tL = 0.693 (RA +2 RB) C Dutycycle=tH/T=0.6.HencetH=0.6T=0.6msandtL =T tH = 0.4ms. Let C=0.1F and substituting in the above equations, RB = 5.8KO (from equation 1) and RA = 2.9KO (from equation 2 & RB values). The Vcc determines the upper and lower threshold voltages (observed from the capacitor voltage waveform) as VUT=2/3. VCC and VL = 1/3 VCC. Note: The duty cycle determined by RA & RB can vary only between 50 & 100%. If RA is much smaller than RB, the duty cycle approaches 50%.

Circuit Diagram and actual connections

PROCEDURE: 1 Before making the connections, check the components using multimeter. 2 3 Make the connections as shown in figure and switch on the power supply. th Observe the capacitor voltage waveform at 6 pin of 555 timer on CRO. rd

4 Observe the output waveform at 3 pin of 555 timer on CRO (shown below). 5. Note down the amplitude levels, time period and hence calculate duty cycle. RESULT: tH =-----------tL = ----------T = -----------The frequency of the oscillations = 1/T= ___ Hz. %Duty cycle (DC) = tH/T*100 = --------WAVEFORMS

---------T -------THEORY: Multivibrator is a form of oscillator, which has a non-sinusoidal output. The output waveform is rectangular. The multivibrators are classified as: Astable or free running multivibrator: It alternates automatically between two states (low and high for a rectangular output) and remains in each state for a time dependent upon the circuit constants. It is just an oscillator as it requires no external pulse for its operation. Monostable or one shot multivibrator: It has one stable state and one quasi stable. The application of an input pulse triggers the circuit time constants. After a period of time determined by the time constant, the circuit returns to its initial stable state. The process is repeated upon the application of each trigger pulse. Bistable Multivibrators: It has both stable states. It requires the application of an external triggering pulse to change the output from one state to other. After the output has changed its state, it remains in that state until the application of next trigger pulse. Flip flop is an example.

PART -A INTRODUCTION TO 5SPICE SIMULATION EXPERIMENT 1(b) 1. POSITIVE CLIPPER AIM: To build and simulate the positive clipper, double-ended clipper and positive clamper circuits using a simulation package

WAVEFORMS

Type of analysis: TIME DOMAIN (TRANSIENT) Run to time: 5msec step size:0.01msec

2. DOUBLE ENDED CLIPPER

Type of analysis: TIME DOMAIN (TRANSIENT) Run to time: 5msec step size: 0.01msec

3. POSITIVE CLAMPER

Type of analysis: TIME DOMAIN (TRANSIENT) Run to time: 5msec step size:0.01msec

EXPERIMENT 2(b) COMMON EMITTER AMPLIFIER AIM: To build the CE amplifier circuit using a simulation package and determine the voltage gain for two different values of supply voltage and for two different values of emitter resistance.

Type of analysis: Ac Sweep Sweep type: logrithemic Start frequency: 10 Hz End frequency: 100Meg points per decade: 40 Result: parametric Analysis (must be used in conjunction with Ac Sweep) to verify the change in output with variation in source Vcc or emitter resistance RE. Step 1: To change the value of emitter resistance RE a) Select the emitter resister and change the value to { Rval }

b) Double click on the parameter, write name 1 = Rval and initial value = 470 ohms c) Click on analysis icon on the screen Select set up

Select parametric analysis Select sweep variables as shown Global parameter Name: Rval Start value = 470 End value = 660 Increment = 200 Sweep type: linear Click ok f) Check the variation in gain on the displaySelect set up Voltage gain with VCC = 10V and emitter resistor RE = 470 ohms is _________ Voltage gain with VCC = 10V and emitter resistor RE = 660 ohms is _________ Step 2: To change VCC from 10 V 12 V in steps along with ac sweep Select parametric analysisStart value = 10 parametric analysis sweep variables as shown a) Click on analysis icon on the screen Name: V1 of2 V Select

use

Sweep variable type: Voltage source End value = 12 Increment = 2 Sweep type: linear Click ok c) Check the variation in gain on the display

Voltage gain with VCC = 10V and emitter resistor RE = 470 ohms is _________ Voltage gain with VCC = 12V and emitter resistor RE = 470 ohms is _________

EXPERIMENT 3(b) CMOS INVERTER AIM: To implement a CMOS inverter using a simulation package and verify its truth table.

Type of analysis: TIME DOMAIN (TRANSIENT) Run to time: 100usec step size: 0.1usec Skip the initial transients

EXPERIMENT 4(b) SCHMITT TRIGGER AIM: To implement a Schmitt trigger using Op-Amp using a simulation package for two sets of UTP and LTP values.

Type of analysis: TIME DOMAIN (TRANSIENT) Run to time: 40msec step size: 0.1msec

On the display window select settings, click on X-axis and select axis variable. Type input voltage on X-axis. Next click on Trace icon, select Add trace and write output voltage on Y-axis. Observe Hystersis curve on the display and measure Hystersis voltage VH. Repeat for two values of UTP and LTP

EXPERIMENT 5(b) RELAXATION OSCILLATOR AIM: To implement a rectangular waveform generator (Op-Amp relaxation oscillator) using a simulation package and observe the change in frequency when all resistor values are doubled.

TYPE OF ANALYSIS : TIME DOMAIN RUN TO TIME : 4ms MAXIMUM STEP SIZE: 0.01ms

RESULT: 1. The time/frequency of output waveform is ---------------2. Double all the resister values and measure the time/frequency of output Waveform ------------------.

EXPERIMENT 6(b) REGULATED POWER SUPPLY AIM: To implement a +5V regulated power supply using full-wave rectifier and 7805 IC regulator in simulation package. Find the output ripple for different values of load current.

R1 220 D4 D2 D 1N 4002 D 1N 4002 V V1 D1 R2 C1 D 1N 750 1K V FREQ =60Hz 47uf VAMPL = 10V VOFF =0V D5 D3 D 1N 4002 D 1N 4002 0

TYPE OF ANALYSIS : TIME DOMAIN RUN TO TIME : 100ms MAXIMUM STEP SIZE: 0.1ms

PART -B INTRODUCTION TO DIGITAL CIRCUITS EXPERIMENT 1(a) MULTIPLEXER (8:1)

CIRCUIT DIAGRAM:

EXPERIMENT 2(a) FULL ADDER

PIN DIAGRAMS:

A 0 0 0 0 1 1 1 1

INPUTS B CIN 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1

OUTPUTS SUM CARRY 0 0 1 0 1 0 0 1 1 0 0 1 0 1 1 1

TRUTH TABLE:

CIRCUIT DIAGRAM:

EXPERIMENT 3(a) JK MASTER SLAVE FLIP FLOP

PIN DIAGRAMS:

PART -B

INTRODUCTION TO VERILOG VERILOG is a complex, sophisticated Hardware Description Language (HDL) which has a number of constructs similar to the C programming language. The designer can provide the initial description of the circuit in several different ways; one efficient way is to write this description in the form of VERILOG source code. This compiler translates this code into a logic circuit. OBJECTIVE: 1 To allow the structural representation of logic circuits by representing simple circuit elements such as logic gates or even transistors and a larger circuit can be defined by writing code that connects such elements tighter. 2 To describe a circuit through behavioral representation by using logic expressions and programming constructs that defines the behavior of the circuit but not its actual structure in terms of gates. GENERAL STRUCTURE OF VERILOG: module module_name(x1, x2, x3, y); input x1, x2, x3; output y; assign y = (x1 & x2 & x3); endmodule

A circuit or sub-circuit described with VERILOG is called a module. The module has a name, module_name, which can be any valid identifier, followed by a list of ports, in which it refers to an input or output connection in a circuit. The ports can be of type input, output, inout and be either scalar or vector. A module can contain any number of variables (reg or integer) declarations and a variety of other types of statements which are included in general form. The assign is the keyword which instantiates the gate to describe the circuit structure with the continuous assignment which in turn describes the circuit function. Here, y can be any expression involving the operators. Multiple assignments can be specified in one assignment statement, using commas to separate the assignment.

EXPERIMENT 1(b) MULTIPLEXER (8:1) AIM: To write the VERILOG code for 8:1 Multiplexer. Simulate and verify its working. COMPONENTS REQUIRED: Xilinx (Verilog) Simulation software and computer. BLOCK DIAGRAM OF 8:1 MULTIPLEXER:

TRUTH TABLE:
S(2) 0 0 0 0 1 1 1 1 INPUTS S(1) 0 0 1 1 0 0 1 1 S(0) 0 1 0 1 0 1 0 1 OUTPUT Y I(0) I(1) I(2) I(3) I(4) I(5) I(6) I(7)

VERILOG CODE:

RESULT: The VERILOG code for 8:1 Multiplexer is written, coded, simulated and verified its working by the truth table.

EXPERIMENT 2(b) FULL ADDER AIM: To write the VERILOG code for Full adder. Simulate and verify its working. COMPONENTS REQUIRED: Xilinx (Verilog) Simulation software and computer. : TRUTH TABLE:
A 0 0 0 0 1 1 1 1 INPUTS B CIN 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 OUTPUTS SUM CARRY 0 0 1 0 1 0 0 1 1 0 0 1 0 1 1 1

BLOCK DIAGRAM OF FULL ADDER

EXPRESSION: SUM = A XOR B XOR CIN; CARRY = AB + B CIN + A CIN; VERILOG CODE: module FA(A, B, CIN); input A, B, CIN; output SUM, CARRY; assign SUM = ( A ^ B ^ CIN), CARRY = (A &B) | (B & CIN) | (A & CIN); Endmodule

RESULT: The VERILOG code for Full adder is written, coded, simulated and verified its working by the truth table.

EXPERIMENT 3(b) D FLIP FLOP AIM: To write the VERILOG code for D FF with positive edge triggering. Simulate and verify its working. COMPONENTS REQUIRED: Xilinx (Verilog) Simulation software and computer. BLOCK DIAGRAM OF D FLIP-FLOP:

TRUTH TABLE:
INPUT D 0 1 OUTPUTS Q QB 0 1 1 0

VERILOG CODE: module DFF(D, CLK, Q, QB); input D, CLK; output Q, QB; reg Q; always @(posedge CLK) Q = D; assign QB = (~ Q);

endmodule RESULT: The VERILOG code for D Flip-Flop with positive edge triggering is written, coded, simulated and verified its working by the truth table.

EXPERIMENT 4(b) MOD 8 UP COUNTER AIM: To write the VERILOG code for MOD 8 Up counter. Simulate and verify its working. COMPONENTS REQUIRED: Xilinx (Verilog) Simulation software and computer. BLOCK DIAGRAM OF MOD-8 UP COUNTER: TRUTH TABLE:
RST 1 0 0 0 0 0 0 0 CLK X 1 1 1 1 1 1 1 EN 0 1 1 1 1 1 1 1 Q 0000 0001 0010 0011 0100 0101 0110 0111

VERILOG CODE: module MOD8(RST, CLK,EN, Q); input RST, CLK, EN; output [3:0] Q; reg [3:0] Q; always @(posedge CLK) begin if(RST) Q = 4b0000; else if(EN) Q = Q+1; if(Q == 4b1000) Q = 4b0000; end endmodule RESULT: The VERILOG code for MOD-8 Up counter is written, coded, simulated and verified its working by the truth table.

EXPERIMENT 5(b) SWITCHED TAIL OR JOHNSONS COUNTER AIM: To write the VERILOG code for Switched-tail counter. Simulate and verify its working. COMPONENTS REQUIRED: Xilinx (Verilog) Simulation software and computer. BLOCK DIAGRAM OF SWITCHED-TAIL COUNTER:
RST 1 0 0 0 0 0 0 0 0 0 CLK X 1 1 1 1 1 1 1 1 1 EN 0 1 1 1 1 1 1 1 1 1 Q 0001 0000 1000 1100 1110 1111 0111 0011 0001 0000

TRUTH TABLE:

VERILOG CODE: module JOHN(RST, CLK, EN, Q); input RST, CLK, EN; output [3:0] Q; reg [3:0] Q; always @(posedge CLK) begin if(RST) Q = 4b0001; else if(EN) Q = {~ Q [0], Q [3], Q [2], Q [1]}; end endmodule RESULT: The VERILOG code for Switched-Tail counter is written, coded, simulated and verified its working by the truth table.