CONTROL UNIT -89C52

In our project 89C52 Microcontroller is used as a control unit.

INTRODUCTION ABOUT MICRO CONTROLLER:

A microcontroller consists of a powerful CPU tightly coupled with memory (RAM, ROM or EPROM), various I/O features such as serial port(s), parallel port(s), Timer/Counter(s), Interrupt controller, Data Acquisition interfaces-Analog to Digital Converter (ADC), Digital to Analog Converter (DAC), everything integrated onto a single silicon chip.

It does not mean that any micro controller should have above said features on-chip. Depending on the need and area of application for which it is designed, the on-chip features present in it may or may not include all the individual sections said above. Any micro computer system requires memory to store a sequence of instructions making up a program, parallel port or serial port for communicating with an external system, timer/counter for control purposes like generating time delays, baud rate for the serial port, apart from the controlling unit called the Central Processing Unit.

MEMORY ASSOCIATED WITH AT-89C52: PROGRAM MEMORY: A program memory is a block of memory, which can be used to store a sequence of program codes (by using special EPROM / PROM programmers). It can only be read from and not written into, under normal operating conditions.

There can be up to 64 k bytes of program memory in AT-89C52. in ROM and EPROM versions of the MCS-351 family of devices, the lower 4K are provided on-chip whereas in ROM fewer versions, all program memory is external.

In ROM and EPROM versions of this device, if the special control signals EA (External Access enable) is strapped off Vcc, and then program fetches to addresses 0000 to 0FFF are directed to the internal ROM. The program fetch will be from external memory, where EA* is grounded.

After reset, the CPU begins execution from address location 0000 of the program memory.

Figure shows a map of the AT-89C52-program memory

FFFF
60K Bytes Internal

FFFF OR
64 K Bytes External

1000 0FFF
4 K Bytes Internal

0000

0000

DATA MEMORY:

Data memory is the Read/Write memory. Hence, it can be both read from and written into. AT-89C52 has got 128 bytes of internal data memory and 64K of external data memory.

FF

SFRS DIRECT ADDRESS 80 SING ONLY 7F DIRECT AND INDIRECT 00 ADDRESSI NG

FFFF AND 0000

64 K Bytes External

INTERNAL DATA MEMORY:

Internal data memory addresses are one byte wide, which includes 128 bytes of onchip RAM plus a number of special Function Registers. The 128 bytes of RAM can be accessed either by direct addressing (MOV data address) or by indirect addressing (MOV @Ri).

The lowest 32bytes (00-1F) of on-chip RAM are grouped into 4 banks of 8 registers each. Program instructions call out these registers as R0 through R7 > Bits 3 and 4 (PSW.3 and PSW.4) in register program status word (PSW) select which register bank is n use. This allows more efficient use of code space, since register instructions are shorter than instructions that use direct addressing.

Reset initializes the stack pointer register to 7 and its incremented once to start from locating 08, which is register R0 of second register bank. Hence, in order to use more than one register bank, the stack pointer should be initialized to a different location of RAM if it is not used for data storage.

The next 16 bytes (20-2F) from a block of bit addressable memory space, which can also byte addressed.

Bytes 30 through 7F are available to the user as data RAM. However, is the stack pointer has been initialized to this area, enough number of bytes should be left a side to prevent stack overflow.

I/O STRUCTURE OF AT-89C52:

AT-89C52 has four 8-bit parallel ports (hence 8*4=32 I/O lines are available). All four parallel ports are bi-directional. Each line consists of a latch, an output driver and an input buffer.

The four ports are named as port 0 (po), port 1 (p1), port 2 (p2) and port 3(p3). They are bit addressable and has to be represented in the form PX.Y is i.e. bit Y of port X while using bit addressing mode. PX.0 is the LSB (least significant Bit) of port x and px.7 is the MSB (Most Significant Bit) of that port.

Out of the four ports, port 0 and port 2 are used in accesses to external memory. All the port 3 pins are multifunctional. Port 3 is an 8-bit bidirectional with internal pull-ups.

Port pin

Alternate Functions

P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6

RXD (Serial input port) TXD (Serial output port) INTO (External Interrupt 0) INT1 (External Interrupt 1) T0 (Timer 0 External input) T1 (Timer 1 External Input) WR (External Data memory write strobe)

P3.7

RD (External Data memory Read Strobe)

PORT 0: Port 0 is an 8-bit open drain bi-directional I/O port. It is also the multiplexed low order address and data bus during access to external memory.

It also receives the instruction bytes during EPROM programming and outputs instruction bytes during program verification. (External pull-ups are required during verification). Port 0 can sink (and operation and source) eight LS TTL input.

PORT 1: Port 1 is an 8-bit bi-directional with internal pull-ups. It receives the low order address byte during EPROM program verification. The port-1 output buffers can sink/source four LS TTL inputs.

PORT 2: Port 2 is an 8-bit bi-directional with external pull-ups. It emits the high order address byte during accesses to external memory. It also receives, these high-order address bits during EPROM programming Verification. Port 2 can sink/source four LS TTL inputs.

RST: While the oscillator is running a high on this pin for two machine cycles resets the device. A small external pull down resistor (8.2k) from RST to Vss permits power on reset when a capacitor (10 micro frequencies) also connected from this pin to Vcc.

ALE/PROG: Address latch enable is the output for latching low byte of the address, during access 10 external memory. ALE is activated at a constant rate of 1/6 the oscillator frequency except during an external data memory access at which time one ALE pulse is skipped. ALE can sink/source eight LS TTL inputs. This pin is also the program pulse input (PROG) during EPROM programming.

PSEN: Program Store Enable is the read strobe to external program memory. PSEN is activated twice each machine cycle, during fetches form external program memory. PSEN is not activated during fetches from internal program memory. PSEN can sink/source 8 LS TTL inputs.

EA/Vpp: When external access enable (EA) is held high, the AT-89C52 execute out of internal program memory (Unless the program counter exceeds OFF (H)). When EA is held low, the AT-89C52 H executes only out of external program memory. This pin also

receives the 21 Volts programming. Supply Voltage (Vpp) during EPROM programming. This pin should not be floated during normal.

XTAL1: It is inputs to the inverting amplifier that forms the oscillator. XTAL1 should be grounded when an external oscillator is used.

XTAL 2: It is Outputs to the inverting amplifier that forms the oscillator, and input to the internal clock generator, receives the external oscillator signal when an external oscillator is used.

Vss Vcc Operation.

Circuit ground potential Supply Voltage during Programming Verification and normal

TIMERS/COUNTERS: AT-89C52 has two 16-bit timer/counter 0, and timer/counter 1. They can be configured in any of the four operating modes, which are selected by bit-pars (m1, 0) in register TMOD (Timer/counter Mode control). Modes 0, 1 and 2 are the same for the timer/counters. Mode 3 is different.

FEATURES OF AT-89C52: Now a days an 8-bit AT-89C52/8031/8751 and 16 bit 8097 micro controllers available in the form of kits. Its special features are summarized as: 4k Bytes of Flash 128 Bytes of RAM

32 I/O lines A five vector two level interrupt architecture.

 A full duplex serial port On chip Oscillator and clock circuitry.

ADDRESSING MODES: The AT-89C52 instructions operate on data stored in internal CPU registers, external memory or on the I/O ports. There are a number of methods (modes) in which these registers, memory (internal or external) and I/O Ports (Internal / External) can be addressed, called addressing modes. This section gives a brief summary of the various types of addressing modes available in AT-89C52. These Modes are: Immediate Direct Indirect

Register

 Register Specific Indexed

IMMEDIATE ADDRESSING: In this mode, the data to be operated upon is in the location immediately following the opcodes. For example, the instruction, MOV A, # 41 -Loads the accumulator with the hex value 41. // Signifies IMMEDIATE ADDRESSING.

DIRECT ADDRESSING: In direct addressing, the operand is specified by an 8-bit address field in the instruction. For example, the instruction,

INC 20

Increments the contents of the On-Chip data address 20 by one.

INDIRECT ADDRESSING: In indirect addressing, the instruction specifies a register, which contains the address of the operand. Both internal and external RAM can be indirectly addressed. The address register for 8-bit address can be R0 or R1 of the selected register bank or the stack pointer. The address register for 16-bit address can only be the 16-bit data pointer register, DPTR. For example, the instruction, MOVX @DPTR, A -Writes the contents of the accumulator to the address held by the DPTR register. RESISTOR ADDRESSING: The register banks, containing resistors R0 through R7, can be accessed by certain instructions, which carry a 3-bit register specification within the opcode of the instruction. Instructions that access the registers this way are code efficient, since this mode eliminates an address byte.

When the instruction is executed, one of the eight resistors in the selected bank at the execution time by two bank select bits is selected at the execution time by the two bank select bits in the PSW. For example, the instruction, MOV A, R0 -Copies the contents of the resistor R0 (of the selected bank) to the accumulator.

INDEXED ADDRESSING: Only program memory can be accessed with indexed intended for reading look-up tables in program memory. A 16-bit base resistor (Either DPTR or the Program counter) points to the base of the table and accumulator is set up with the table entry number. The address of the table entry in program memory is formed by adding the accumulator data to the base pointer. The instruction, MOVC A,@A+DPTR This function reads the contents of program memory, whose address is obtained by adding the content of DPTR and accumulator copies it to the accumulator.

PIN DIAGRAM OF AT89C52:

PDIP
P1.0 P1.1 P1.2
RAM ADDR RESISTOR

1 2 3 RAM 4 5 6 7 8 9 10 11 12 13 14 15 PSW 16 17 18
PORT 1 LATCH PORT 0 LATCH

40
PORT 0 DRIVERS

Vcc
PORT 2 DRIVERS

39

P 0.0(AD 0)

38 37 PORT 2

P 0.1 (AD 1)

P1.3 P1.4 P1.5 P1.6

P 0.2 (AD 2) FLASH LATCH P 0.3 (AD 3) 36 35 34

STACK POINTER 33

P 0.4 (AD 4) P 0.5 (AD 5) P 0.6 (AD 6) P 0.7 (AD 7) EA / VPP ALE/PROG PSEN P2.7 (A 15) P2.6 (A 14)
PC INCREME N-TER BUFFER PROGRAM ADDRESS REGISTER

B REGISTER

P1.7 ACC RST (R X D) P3.0 TMP (T X D) P3.1 2 (INT 0) P3.2 (INT 1) P3.3 (T 0) P3.4 (T1) P3.5 (WR) P3.6 (RD) P3.7 XTAL 2

32 TMP 1 31 30 29 28

27 INTERRUPT SERIAL PORT (A 13) P2.5 AND TIMER BLOCKS 26 25 24 23 22 P2.4 (A 12) P2.3 (A 11) P2.2 (A 10)
DPTR PROGRAM COUNTER

TIMING AND CONTROL

INSTRUCT XTAL 1 -ION REGISTER

P2.1 (A 9) P2.0 (A 8)
PORT 3 LATCH P2.0 P2.7

GND

19 20

PLCC

21

P 0. 0 P 0 . 7 Vcc

OSC

PORT 1 DRIVERS

PORT 3 DRIVERS

GND

ALU

PSEN ALE/ PROG EA/Vpp RST

P1.0 P1.7

P3.0 P3.7

ACCUMULATOR:

Accumulator is the Accumulator register mnemonics for Accumulator. Specific instruction however, refer to the Accumulator simply A.

B REGISTER:

The B register is used during multiply and divide operations. For other instructions can be treated as another scratch pad register.

PROGRAM STATUS WORD:

The PSW resistor contains program status information. The program status word (PSW) contains several status bits that reflect the current state of the CPU. The PSW resides in SFR space. It contains the carry bit, the auxiliary carry 9for BCD operations), the two register bank select bits, the overflow flag a parity bit and two user definable status flags. The carry bit other than serving the functions of a carry bit in arithmetic operations, also serves as the Accumulator for a number of Boolean operations. The bits and RSI are used to select one of the register bans. A number instruction refers of their RAM location R0 through R7. The selection of which the four banks is being referred to is made on the bass of the bits RS0 and RS1 execution time.

The lower 32B are grouped into 4 banks of 8 resistors. Program instructions call out there resistors as R0 through R7 bits in the PSW select which register is n use. The parity bit reflects the number is in the accumulator. P=1 if the accumulator contains an old number of 1 s and p=0 if the accumulator contains an even number of 1 s. Thus the number of 1 s in the accumulator plus P is always even. Two bits in the PSW are uncommitted and may be used as general-purpose status flags.

PROGRAM STATUS WORD OF AT89C52 DEVICES:

AC

FO

RS1

RS0

OV

Carry flag receives carry out from bit-1 of ALU operation

Parity of accumulator by hard ware to 1 bit if it contains an old number of 1 s otherwise set to 0

Auxiliary carry flag receives carry out from bit-1 of addition operands

User Definable Flag

Overflow Flag set by Arithmetic Operation

General Purpose Status Flag

Resistor Bank Select bit- 0

Register Bank Select bit-1

THE LOWER 128 BYTES OF INTERNAL RAM

7F (H) 2F (H) 20 (H) Bank Select Bit In PSW 11 Bank-3 18 (H) Bank-2 10 (H) 10 01 00 Bank-1 08 (H) Bank-0 00 (H) 1F (H) 17 (H) 0F (H) 07 (H) 4 Banks of 8 resistors R0 - R7 Bit addressable Space Bit address 0-7F (H)

STACK POINTER:

The stack pointer resistor is 8-bit wide. It is incremented before data is stored during PUSH and CALL execution while the stack may where in on-chip RAM. The stack pointer is initialized to 07(H) after a reset. This causes the stack to begin at location 08(H).

DATA POINTER:

The data pointer (DPTR) consists of a high byte (DPH) and a low byte (DPL). Its intended function is to hold a 16-bit address. It may be manipulated as a 16-bit resistor or 08 two independent bit registers. Ports 0 to 3 p0, p1, p2 and p3 are the SFR latches for ports 0, 1, 2, and 3 respectively.

SERIAL DATA BUFFER:

The serial data buffer is actually two separate resistors transmit buffer and a receive buffer resistor. When data is moved to SBUF, it goes to the transmit buffer where it is held for serial transmission. (Moving a byte to SBUF is what initiates the transmission) When data is moved from SBUF, it comes from the receive buffer.

TIME RESISTORS:

Resistors pairs (TH0, TL), (TH1, TL1) and (TH2, TL2) are the 16-bits counting resistors for the interrupt system, the timer counters and the serial port.