Testability Analysis

Chapter 6 Dr. Sushanta K. Mandal

Testability Analysis
Testability
A relative measure of the effort or cost of testing a logic circuit

Testability Analysis
The process of assessing the testability of a logic circuit

Sushanta K. Mandal

PGVE-203 Testing of VLSI Circuits Spring 2012

Testability Analysis
Controllability
Difficulty of setting internal signal lines to 0 or 1 by setting primary input values.

Observability
Difficulty of observing internal signal lines by observing primary outputs.
Difficulty of propagating the logic value of the signal line to primary outputs.
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Why Testability Analysis

To analyze the difficulty of testing internal circuit parts. redesign or add special test hardware To provide guidance for algorithms for computing test patterns.

avoid using hard-to-control lines

Estimation of fault coverage.

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Origin
Control theory Rutman 1972
First definition of controllability.

Goldstein 1979 -- SCOAP

First definition of observability.
First elegant formulation. First efficient algorithm to compute controllability and observability.
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Types of Measures in SCOAP

SCOAP
Sandia Controllability and Observability Analysis Program

Combinational measures:
CC0 Difficulty of setting circuit line to logic 0 CC1 Difficulty of setting circuit line to logic 1 CO Difficulty of observing a circuit line

Sequential measures analogous:

SC0 sequential 0-controllability SC1 sequential 1-controllability SO sequential observabilty
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Range of SCOAP Measures

Controllability
Value ranges from 1 (easiest) to infinity (hardest).

Observability
Value ranges from 0 (easiest) to infinity (hardest).

Combinational and sequential measures:

The CC0 and CC1 values of a primary input are set to 1
The SC0 and SC1 values of a primary input are set to 0 The CO and SO values of a primary output are set to 0

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PGVE-203 Testing of VLSI Circuits Spring 2012

SCOAP Measures
For each logic gate in the path add 1 to the controllability. If a logic gate output is produced by setting only one input to a controlling value, then:
Output controllability = min (input controllabilities) + 1

If a logic gate output can only be produced by setting all inputs to a non-controlling value:
Output controllability = (input controllabilities) + 1

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PGVE-203 Testing of VLSI Circuits Spring 2012

SCOAP Measures
If an output can be controlled by multiple input sets (e.g., a two-input XOR gate where 01 and 10 input sets will both cause a 1 output)
output controllability = min (controllabilities of each input set) + 1

Fanout Stem observability: or min (some or all fanout branch observabilities)

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Controllability Basic Gates

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Controllability Basic Gates

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Observability Basic Gates

To observe a gate input: Observe output and make other input values non-controlling.

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Observability Basic Gates

Fanout stem: Observe through branch with best observability.

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Error Due to stems and Reconverging Fanouts

SCOAP measures wrongly assume that controlling or observing x, y, z are independent events
CC0 (x), CC0 (y), CC0 (z) correlate CC1 (x), CC1 (y), CC1 (z) correlate CO (x), CO (y), CO (z) correlate

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Correlation Error Example

Exact computation of measures is NP-Complete and impractical. Italicized measures show correct values SCOAP measures are not italicized CC0,CC1 (CO).
1,1(6)

1,1(5, )
8
1,1(5) (6) (6) (5)

x 2,3(4, )
8

2,3(4)

6,2(0)

4,2(0)

1,1(4,6)

(4,6)

y z
8

2,3(4)

2,3(4, )

1,1(6)
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1,1(5, )
8
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Sequential Example

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Controllability Through Level 0

Circled numbers give level number. (CC0, CC1)

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Controllability Through Level 2

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Final Combinational Controllability

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Combinational Observability for Level 1

Number in square box is level from primary outputs (POs). (CC0, CC1) CO

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Combinational Observability for Level 2

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Final Combinational Observabilities

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Sequential Measures (Comparison)

Combinational
Increment CC0, CC1, CO whenever you pass through a gate, either forward or backward.

Sequential
Increment SC0, SC1, SO only when you pass through a flip-flop, either forward or backward.

Both
Must iterate on feedback loops until controllabilities stabilize.
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D Flip-Flop Equations
Assume a synchronous RESET line. CC1 (Q) = CC1 (D) + CC1 (C) + CC0 (C) + CC0 (RESET) SC1 (Q) = SC1 (D) + SC1 (C) + SC0 (C) + SC0 (RESET) + 1 CC0 (Q) = min [CC1 (RESET) + CC1 (C) + CC0 (C), CC0 (D) + CC1 (C) + CC0 (C)] SC0 (Q) is analogous CO (D) = CO (Q) + CC1 (C) + CC0 (C) + CC0 (RESET) SO (D) is analogous

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D Flip-Flop Clock and Reset

CO (RESET) = CO (Q) + CC1 (Q) + CC1 (RESET) + CC1 (C) + CC0 (C) SO (RESET) is analogous Three ways to observe the clock line:
1. Set Q to 1 and clock in a 0 from D 2. Set the flip-flop and then reset it 3. Reset the flip-flop and clock in a 1 from D

CO (C) = min [ CO (Q) + CC1 (Q) + CC0 (D) + CC1 (C) + CC0 (C), CO (Q) + CC1 (Q) + CC1 (RESET) + CC1 (C) + CC0 (C), CO (Q) + CC0 (Q) + CC0 (RESET) + CC1 (D) + CC1 (C) + CC0 (C)] SO (C) is analogous
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Algorithm: Testability Computation

For all PIs, CC0 = CC1 = 1 and SC0 = SC1 = 0 For all other nodes, CC0 = CC1 = SC0 = SC1 = Go from PIs to POS, using CC and SC equations to get controllabilities -- Iterate on loops until SC stabilizes -convergence guaranteed. For all POs, set CO = SO = 0

Work from POs to PIs, Use CO, SO, and controllabilities to get observabilities
Fanout stem (CO, SO) = min branch (CO, SO) If a CC or SC (CO or SO) is , that node is uncontrollable (unobservable)
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Sequential Example Initialization

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After 1 Iteration

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After 2 Iteration

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After 3 Iteration

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Stable Sequential Measures

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Final Sequential Observabilities

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