Chapter 2

8051 Architecture
Overview of the 8051

In 1981 Intel Corporation introduced 8051. 8051 is an 8-bit, single-chip microcontroller optimized for control applications It had 128 bytes RAM, 4096 bytes (4KB) ROM, 2 timers, 1 serial port, 4 I/O ports(each 8-bit wide) all on a single chip. A System On Chip Packaged in a 40 pin dual in-line package (DIP) layout

8051 Architecture
General Physical Features The 8051 architecture provides the following functions (CPU, RAM, ROM, I/O, interrupt logic, timer, etc.) in a single package.

8051 is an 8-bit processor. The CPU can work on only 8 bits of data at a time It has 8-bit ALU, Accumulator and 8-bit Registers 8-bit data bus It can access 8 bits of data in one operation. 16-bit address bus It can access 216 memory locations 64 KB (65536 locations) each of RAM and ROM 4KB of On chip ROM (Program Memory) 128 bytes of On chip RAM (data Memory) 4 register banks of 8 bytes each (R0-R7) 4 x 8 = 32 16 bytes of bit-addressable area 16 80 bytes of general purpose memory 80 -----------128 128 bytes of Special Function Registers(only 21 are used) Four 8-bit I/O ports 32 bidirectional I/O lines used as four 8-bit ports or individually addressable I/O lines. Two 16-bit timers/Counters (Timer0 & Timer1) One Full duplex serial receiver-transmitter interface Five interrupt sources (2 external & 3 internal) One oscillator (generates clock signal) Memory of 8051 can be increased externally: Increase memory space for codes (programs) by 64K bytes Increase memory space for data by 64K bytes. The CPU of 8051 has the following registers and components: 8-bit ALU 16-bit Program counter (PC) 16-bit Data pointer (DPTR) Accumulator (A) register B register Flags and 8-bit Program status word (PSW) 8-bit stack pointer (SP) Special function register (SFRs) The block diagram of 8051 is shown in figure (1) and 1A. (Any one figure (1) and (1A) can be used). The 8051 microcontroller is available in a 40-pin DIL (Dual-In-Line) package; The Pin assignments are shown in Figure.2

The dual functions of pins are shown in figure 3

Figure 1

Figure

2 : The 8051 Pin Assignments

Figure 1A

Figure 3 : Dual Functions of Pins

Pin Descriptions of 8051

Pins 1-8: Port-1 (P1.O-P1.7) Port 1 is a Quasi bi directional port. Each of these pins can be configured as I/P or O/P pins. This port does not offer any alternate functions Pin-9: RST (Reset) Micro controller use Reset mechanism to establish initial conditions during initial power-on or thereafter . When RESET pin is made high for two machine cycles (a pulse), microcontroller will terminate all its activities and reset. All registers are initialized to default values. Program counter is loaded with 0000H.

Pin10-17: Port-3(P3.O-P3.7) Port 3 is a Quasi bi directional port with internal pull up. Each of these pins can be configured as I/P or O/P pins. Some alternate functions like interrupt input, timer/counter input and serial communication signals are shared with this port pins. Control signals necessary for external data memory interface, namely RDbar and WRbar, are also available from this port. Pins 10 & 11: RXD & TXD 8051 has Full duplex serial data communication circuits . The data is transmitted out of 8051 through TXD line. The data is received by 8051 through the RXD line. Pin 12 & 13:INT0 & INT1 Interrupt-0 and Interrupt-1 are two interrupt pins that are triggered by external circuits. Pins 14 & 15: T0 & T1 The 8051 has two 16-bit timers/counters. T0 is the Timer 0 external input. T1 is the Timer 1 external input. Pins 16 &17: (WR and RD) When (pin 17) RD = 0, microcontroller reads the data from external RAM. When (pin 16) WR = 0, microcontroller writes the data into external RAM. Pins 18 & 19: XTAL-2 & XTAL-1 XTAL 1(pin 19) and XTAL 2 (pin 18) provide connecting resonant circuit (crystal) to form oscillator. In case of an external clock it must applied to XTAL- 2 and XTAL-1 must be connected to GND. Pin 20: Vss It is a ground pin. Pins 21-28: Port-2(P2.O-P2.7) If external memory is not used, these pins can be configured as I/P or O/P pins. If external memory is used then the higher address i.e. A8-A15 will appear on this port. Pin 29: PSEN(Program Store Enable)

This pin provides an output read strobe to external program memory(ROM). The output is active low during the fetch stage of an instruction.(and code byte from the ROM is placed on the data bus). The signal is not activated during a fetch from internal memory. Pin 30: ALE (Address Latch Enable) The ALE signal is an output pulse used to latch the low byte of an address during access to external memory. When ALE = 1, port 0 is providing lower order address (A0-A7) When ALE = 0, port 0 is used as data lines. Pin 31: EAbar (External Access) This pin is used whenever external memory is used.

When EAbar is connected to VCC i.e. EAbar = 1, code is stored in internal ROM. The device will execute programs from internal memory in the address range 0000h to 0FFFh. If address is larger than 0FFFh code is fetched from external memory. When EAbar is connected to GND i.e. EAbar = 0, code is stored in external ROM. The program is fetched from address location 0000h to FFFFh of external memory. Pins 32-39: Port-0(P0.7-P0.0) This is a dual purpose port. The port may be used with external memory to provide a multiplexed address and data bus. If external memory is not used, these pins can be configured as I/P or O/P pins. If external memory is used then the lower address i.e. A0-A7 will appear on this port. Pin 40: VCC DC power supply +5V is connected to this pin.

2.3 Functional Blocks of 8051

Functions of architectural blocks of 8051 shown in figure (1) are described in next sections

The Oscillator
The heart of 8051 is the circuitry that generates the clock pulses by which all internal operations are synchronized. Pins XTAL1 and XTAL2 are provided for connecting resonator circuit (Crystal) to form an oscillator. The crystal frequency is the basic internal frequency of the microcontroller. 8051 is designed to operate between 1MHz to 16MHz and generally operates with a crystal frequency 11.04962 MHz. Machine Cycle The smallest interval of time to accomplish any simple instruction, or part of a complex instruction, is the machine cycle. A machine cycle consists of a fixed number of clock cycles (pulses). The 8051 family needs 12 clock cycles for a machine cycle. In 8051 the machine cycle is itself made up of six states. Two oscillator pulses define each state. A state is the basic time interval for discrete operations of the microcontroller such as fetching an opcode byte, decoding an opcode, executing an opcode, or writing a data byte. The CPU takes one or more machine cycles to complete an instruction. More complex instructions require more number of machine cycles to complete the instruction. The numbers of machine cycles of the 8051 instructions are ranging from 1 to 4.

To calculate the time any particular instruction will lake to be executed, Find the number of machine cycles(C) for the instruction, (from the data sheet/programmers manual). The time to execute that instruction is then found by multiplying C by 12 (clock pulses/machine cycle) and dividing the product by the crystal frequency: C 12d Tinst = Crystal Frequency Example 4-1 Find the elapse time of the machine cycle for: (a) XTAL = 11.0592 MHz (b) XTAL = 16 MHz (c) XTAL = 20 MHz Solution: (a) 11.0592 MHz / 12 = 921.6 kHz Machine cycle = 1 / 921.6 kHz = 1.085 s (b) 16 MHz / 12 = 1.333 MHz Machine cycle = 1 / 1.333 MHz = 0.75 s (c) 20 MHz / 12 = 1.667 MHz Machine cycle = 1 / 1.667 MHz = 0.60 s

Central Processing Unit (CPU):

The 8051 CPU consists of 8-bit arithmetic and logic unit with associated registers. The 8051s ALU can perform arithmetic and logic functions on 8-bit variables. The arithmetic unit performs addition, subtraction, multiplication and division. The logic unit can perform logical operations such as AND, OR and X-OR as well as rotate, clear and complement. A Boolean processor performs bit wise operations. Set or clear bit ,Compliment bit etc

CPU Registers

Register are used to store information temporarily. The information to be stored could be 1. A byte of data to be processed, or 2. An address pointing to the data to be fetched The majority of 8051 register are 8-bit registers The 8 bits of a register are shown from MSB D7 to the LSB D0

The most widely used registers PC (program counter) , A (Accumulator), B, DPTR (data pointer), Stack Pointer (SP) and and bank register R0, R1, R2, R3, R4, R5, R6, R7

Program Counter (PC)

Data Pointer (DPTR)

Program Counter (PC) is a 16-bit register. Holds the address of the memory location to fetch the program instruction. PC is the only register that does not have an internal address. Program ROM may be on the chip at addresses 0000H to 0FFFH (4Kbytes), external to the chip for addresses that exceed 0FFFH Program ROM may be totally external for all addresses from 1000H to FFFFH PC is automatically incremented (+1) after every instruction byte is fetched DPTR is a 16-bit register DPTR is made up of two 8-bit registers: DPH and DPL DPTR holds the memory addresses for internal and external code access external data access (eg. MOVC A,@A+DPTR MOVX A,@DPTR MOVX @DPTR,A ) DPTR is under the control of program instructions and can be specified by its 16-bit name, or by each individual byte name, DPH and DPL DPTR does not have a single internal address; DPH and DPL are each assigned an address (83H and 82H) In 8051 a 8 bit accumulator is used for many operations, including addition, integer multiplication and division, and Boolean bit manipulations A register is a general-purpose register used for storing intermediate results obtained during operation. Prior to executing an instruction upon any number or operand it is necessary to store it in the accumulator first. All results obtained from arithmetical operations performed by the ALU are stored in the accumulator.. Data to be moved from one register to another must go through the accumulator. Access to accumulator is faster than access to memory. Has direct path to ALU and can immediately store the result of operation. A register is also used for all data transfer between the 8051 and any external memory

Accumulator (A Register)

B Register

B register is a 8- bit register used with the A register for multiplication and division operations. One of the operand is stored in B. Higher order byte of Product after Multiplication, and Remainder after Division are stored in B. (eg. MUL AB DIV AB) No other special function other than as a location where data may be stored

Program Status Word (PSW)

PSW contains the math flags, user program flag F0, and the register select bits (RS1, RS0) that identify which of the four general-purpose register banks is currently in use by the program
PSW

Flags Flags are1-bit registers provided to store the status that reflects the current state of the CPU. Flags are Set or Reset as result of certain program instructions. Other instructions can test the condition of the flags and make decisions based on the flag states Flags are grouped inside the program status word (PSW) for convenient addressing Math flags respond automatically to the outcomes of math operations. 8051 has four Math flags namely Cary(CY) , Auxiliary Cary( AC), Overflow( OV), Parity(P) Flags RS0, RS1 - Register bank selects bits. These two bits are used to select one of four register banks of RAM. By setting and clearing these bits, registers R0-R7 are stored in one of four banks of RAM. Table (1) shows the details different flags and RS0,RS1 bits. Example 2 Show the status of the CY, AC and P flag after the addition of 38H and 2FH in the following instructions. MOV A, #38H ADD A, #2FH ;after the addition A=67H, CY=0 Solution: 38 00111000 + 2F 00101111 -------------------67 0 01100111 CY = 0 since there is no carry beyond the D7 bit AC = 1 since there is a carry from the D3 to the D4 bi P = 1 since the accumulator has an odd number of 1s (it has five 1s) Example 2 Show the status of the CY, AC and P flag after the addition of 9CH and 64H in the following instructions. MOV A, #9CH ADD A, #64H ; after the addition A=00H, CY=1 Solution: 9C 10011100 + 64 01100100 ----------------100 1 00000000 CY = 1 since there is a carry beyond the D7 bit AC = 1 since there is a carry from the D3 to the D4 bi P = 0 since the accumulator has an even number of 1s (it has zero 1s)

Example Show the status of the CY, AC and P flag after the addition of 88H and 93H in the following instructions. MOV A, #88H ADD A, #93H ;after the addition A=1BH, CY=1 Solution: 88 10001000 + 93 10010011 --------------------11B 00011011 CY = 1 since there is a carry beyond the D7 bit AC = 0 since there is no carry from the D3 to the D4 bi P = 0 since the accumulator has an even number of 1s (it has four 1s) Table 1 Bit Symbol Function 7 CY Carry Flag is used in arithmetic, JUMP, ROTATE, and BOOLEAN instructions. Indicates carry out of D7 of result (accumulator) after execution of the instruction. CY=1 If Carry exists out of D7 of accumulator. CY=0 If there is No carry out of D7 of accumulator. 6 AC Auxiliary Carry Flag is used for BCD operations only. AC=1 If there is a Carry out of D3 of the result. AC=0 If there is No Carry out of D3 of the result. 5 4 3 F0 RS1 RS0

User flag: A general-purpose flag that may be used by the programmer to record some event in the program Register bank select bit 1 Register bank select bit 0 RS1 RS0

OV

0 0 Select Register bank 0 0 1 Select Register bank 1 1 0 Select Register bank 2 1 1 Select Register bank 3 Overflow occurs when the result of an arithmetical operation is larger than 255 and cannot be stored in one register. Overflow flag is set (ie , OV=1) if there is a 1. Carry out of D6 and no carry out of D7 of result. 2. Carry out from D7 (CY = 1) but no carry from D6 to D7. Else OV = 0 Reserved for future use Parity Flag (P):The 8051 maintains even parity with the accumulator A, i.e., the number of ones in the accumulator together with the parity bit (in the program status word, PSW) is always even. Parity flag; shows parity of register A: P = 1 if Odd Parity. (Odd number of 1s in A) P = 0 if Even Parity (Even number of 1s in A)

1 0

-P

Internal Memory
o

A functioning computer must have o memory for program code bytes, commonly in ROM, and RAM memory for variable data that can be altered as the program runs. Additional memory can be added externally using suitable circuits. The 8051 has Harvard architecture o uses the same address but in different memories for code and data. o The Internal circuitry access the correct memory based on the nature of the operation in progress 8051 has internal RAM (128 bytes) and ROM (4Kbytes). Internal RAM: The 128 bytes internal RAM is organized into 3 distinct areas. The internal RAM of 8051 is organized into three distinct areas: 1. Working Registers 2. Bit addressable registers 3. General purpose registers

1.

32 bytes from address 00h to 1Fh that make up 32 working registers organized as 4 memory banks of 8 registers each.

The 4 register banks are numbered 0 to 3 and are made up of 8 registers named R0 to R7. Each register can be addressed by name or by its RAM addresses. Bits RS0 and RS1 in the PSW determine which bank of registers is currently in use at any time when program is running. Register banks not selected can be used as general purpose RAM. Bank0 is selected by default on reset.

Ex: Thus R0 of bank3 is R0 (if bank3 is selected ) or address 18h (where bank3 is selected) .

PSW.3 = PSW.4 =
2.

RS0=0 RS1=0

RS0=1 RS1=0

RS0=0

RS0=1

RS1=1

RS1=1

A bit addressable area of 16 bytes occupies RAM byte addresses 20h to 2Fh, forming total of 128 bits. An addressable bit may be specified by its bit address of 00h to 7Fh or 8 bits may form any byte address from 20h to 2Fh.(shown in fig ) For example bit address 4fh is also bit 7 of byte address 29h. Addressable bits are useful when the program need only remember a binary event.

3. A general purpose RAM area above the bit area from 30h to 7Fh, addressable as byte. May be used for any general-purpose storage including the stack.

Any unused bytes of the bit-addressable area or unused register banks may also be used for general-purpose data storage. Stack and Stack Pointer (SP) Stack refers to an area of internal RAM that is used in conjunction with certain opcodes to store and retrieve(take back) data quickly SP is a 8-bit register SP holds the internal RAM address where the last byte of data was stored by a stack operation An internal RAM address where last byte was stored by stack operation is called the top of the stack When data is to be placed on the stack, the SP increments before storing data on the stack so that the stack grows up as data is stored. As data is retrieved from the stack, the byte is read from the stack, and then the SP decrements to point to the next available byte of stored data SP = 07H after reset.(default address stored in SP = 07h) so that the stack may start from 08H onward. (ie, Default stack is Bank 1) The storing of a CPU register contents in to the stack is called a PUSH. Loading the contents of the stack back to the CPU register is called a POP Special Function Registers (SFR) 8051 has 21 SFRs which occupy the addresses from 80H to FFH (128bytes) Not all of the addresses from 80H to FFH are used for SFRs Attempt to use the empty addresses may get unpredictable result

Value of SFR at Reset

Internal ROM
Internal ROM occupies the code address space from 0000H to 0FFFH (Size = 4K byte) Program addresses higher than 0FFFH will automatically fetch code bytes from external program memory

Code bytes can also be fetched exclusively from an external memory by connecting the external access pin (EA) to ground

I/O Ports (P0 - P3)

The 8051 has 32 Input/Output pins configured as four 8-bit parallel ports i.e. port-0, port-1, port-2 and port-3.

All ports are bidirectional (they can take input and to provide output) Each pin can be configured as I/O or O/P under software control. All ports have multiple functions (except P1) All ports are bit addressable On RESET all the ports are configured as output When a bit latch is to be used as an input, a 1 must be written to the corresponding latch by the program to configure it as input (eg. MOV P1, #0FFH)

Port 0 Occupies a total of 8 pins (Pins 32-39) It can be configured as Input only Output only Input and output at the same time (i.e. some pins for input and the others for output) Can be used to handle both address and data Need pull-up resistors Dual Role of Port 0 When connecting an 8051 to an external memory, port 0 provides both address and data (AD0 AD7) When ALE = 0, it provides data D0 D7 When ALE = 1, it provides data A0 A7 ALE is used for demultiplexing address and data with the help of a 74LS373 latch

Port Port

1 Occupies a total of 8 pins (Pins 1-8) Can be used as input or output Does not need any pull-up resistors Upon reset, port 1 is configured as an output port No alternative functions 2 Occupies a total of 8 pins (Pins 21-28) Similar function as Port 1. Can be used as input or output Does not need any pull-up resistors

 Upon reset, port 2 is configured as an output port Dual Role of Port 2 When connecting an 8051 to an external memory, port 2 provides address (A8 A15) It is used along with P0 to provide the 16-bit address When P2 is used for the upper 8 bits of the 16-bit address, it cannot be used for I/O Port 3 Occupies a total of 8 pins (Pins 10-17) Similar function as Port 1 and Port 2 Can be used as input or output Does not need any pull-up resistors Upon reset, port 3 is configured as an output port Pins can be individually programmable for other uses Most commonly be used to provide some important signals (e.g. interrupts) Port 3 Alternate Functions P3 Bit P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Function RxD TxD INT0 INT1 T0 T1 WR RD Pin 10 11 12 13 14 15 16 17

Timers and Counters

8051 has Two 16-bit programmable UP timers/counters. Timer 0 and Timer 1. T0 and T1 Can be configured to operate either as timers or as event counters. The timer content is available in four 8-bit special function registers, TL0,TH0,TL1 and TH1 respectively. In the "timer" function mode, o the counter is incremented in every machine cycle. o Thus, one can think of it as counting machine cycles. o Hence the clock rate is 1/12 th of the oscillator frequency. "counter" function mode, o the register is incremented in response to a 1 to 0 transition at its corresponding external input pin (T0 or T1). The operation of the timers/counters is controlled by two special function registers, TMOD and TCON respectively.

Serial Interface

The serial port of 8051 is full duplex, i.e., it can transmit and receive simultaneously. The register SBUF is used to hold the data. The special function register SBUF is physically two registers. One is, write-only and is used to hold data to be transmitted out of the 8051 via TXD. The other is, read-only and holds the received data from external sources via RXD.

Both mutually exclusive registers have the same address 099H. Register SCON controls serial data communication. 8051 provides 5 vectored interrupts. They areI) INT0 2) INT1 3) TF0 4) TF1 5) RI/TI Out of these, INT0 and INT1 are external interrupts whereas Timer and Serial port interrupts are generated internally. The external interrupts could be negative edge triggered or low level triggered. All these interrupt, when activated, set the corresponding interrupt flags. Except for serial interrupt, the interrupt flags are cleared when the processor branches to the Interrupt Service Routine (ISR). The external interrupt flags are cleared on branching to Interrupt Service Routine (ISR), provided the interrupt is negative edge triggered. For low level triggered external interrupt as well as for serial interrupt, the corresponding flags have to be cleared by software by the programmer.

Interrupts: