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ANALOG AND MIXED MODE VLSI VI SEM ENC DATA CONVERTER FUNDAMENTALS Introduction Why data Conversion?

• Most real-world signals are analog in nature. • Real-world signals-Continuous time, Continuous amplitude • However Digital signal processing allows us to efficiently manipulate information. • Digital abstraction-discrete time, discrete amplitude • To take advantage of DSP we must be able to move from analog to digital and back as needed What is data Converter? • A device that converts a signal from analog to digital domain and vice versa. What type of systems require data converters? • Any system that requires real inputs from outside world that need to be processed digitally or any system that wants to convert digital data to analog signal that can be interpreted in the outside world need a converter.

How does a data converter fit in to signal chain? • Data converters typically accept analog signals from sensors once these signals have been conditioned, and pass off digital data to a processor. • They can also accept digital data from these devices and pass them off for signal conditioning and analog system output.

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Applications- wide range. • Performance requirements such as resolution and bandwidth are set by intended applications. • Portable devices-push the limits of technology by requiring faster speed and lower power. • Communications: Wireless transceivers, Modems • Computing and control: Imagers,displays, Multimedia • Measurement & Instrumentation: Test equipment, Industrial and scientific Instrumentation, Sensors & actuators. • Consumer Electronics: Video/Audio, Control (Automotive, Appliances, etc). • Embedded data Conversion

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Types of Data Converters Two types: 1. Analog to digital Converter(ADC) 2. Digital to analog Converter(DAC) Analog to digital converter consists of two basic functions. • Sampling: convert a continuous time input signal to a discrete time representation. • Quantization: convert a continuous amplitude input signal to a discrete amplitude representation. • Input signal must be bandlimited to no more than ½ FS to prevent aliasing.

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Uniform Sampling and Quantization

Uniform Sampling and Quantization -Sample signal Uniformly in time -Quantize signal Uniformly in amplitude Issues: How fast to sample? How much noise added to quantization? How can we reconstruct signal back to analog form? Discrete time signals -Discrete time signals are simply a sequence of numbers with a set of corresponding discrete time indexes. -Intermediate signal values are not defined. -Mathematically convenient but non-physical:use the term sampled data signals.

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-Representing signals in discrete–time domain determines an increase in ambiguity in frequency domain; undesired frequency translation /interaction(aliasing)

Sampling theory

Fig. shown below illustrates the sampled signal in time and frequency domain.

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Types of Sampling Nyquist rate Sampling: Sampling at twice the signal frequency Down sampling Up sampling 7 .

Over Sampling 8 .

Down Sampling fs<2fb Data Converter Building blocks Sample and Hold Circuits Operational Amplifiers. • Precision Parameters are 9 .OTA’s Comparators Filters Current sources Reference Circuits Logic Circuits • • • • • • • Data Converters key parameters • Performance parameters are Sampling freq Resolution.

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-The summation of differential nonlinearities from the bottom up to a particular step .• Sampling frequency is the speed at which samples are measured and converted’ -inversely related to sample time. determines the value of the INL at that step. -determines to what granularity a data converter can identify an analog signal. INL and DNL INL(Integral Nonlinearity error) -deviation of the values on the actual transfer function from the ideal transfer function once the gain and offset errors are nullified. -12 bit Conveter running at 100KSPS has 1.2Mbps throughput. • Resolution is the number of digital bits that the converter will use. -12 bit converter will have 212 different voltage levels it can identify. -measured in samples per second. 12 . • Throughput is the amount of digital data a converter uses in a given amount of time.

e. 13 . -inherent in the design and manufacuring of the converter. -INL error-how far away from the ideal transfer function value the measured converter is. DNL (Differential Nonlinearity error) -difference between the actual step width (for an ADC) or step height(for DAC) and the ideal value of 1 LSB. -The full scale point is defined as level ½ LSB beyond last code transition. DNL specifies the deviation of any adjacent code in the transfer function of DAC or ADC from an ideal code width of 1 LSB. -good INL gaurantees good DNL. -In ADC there is also a possibility that there can be missing codes.(if DNL> -1LSB)i.INL(Integral Nonlinearity error) -INL is defined as the integral of DNL. -Can not be corrected are calibrated. -Point used as zero occurs ½ of LSB before the first code transition. one or more of the possible 2 n binary codes are never output. -deviation is measured from centre of each particular code to the true straight line between these two points.

- 14 .The transition of code N is compared to that of code N+1. . DNL error of -1LSB implies that the output did not increase for increasing input code. .DNL is measured in the increasing code direction of the transfer curve. -positive DNL implies that the code is longer than the ideal code width.-DNL is determined by subtracting the locations of successive code transition points after compensating for gain and offset errors.negative DNL implies that the code is Shorter than the ideal code width . .For DAC.

15 . a small constant analog voltage is always present before the conversion begins to function linearly. . . meaning that there is no analog voltage which will generate a particular code. versus the ideal levels that produce these codes In an ideal situation. data converter would begin to notice deviations from true zero voltage. because of offset error.If the output codes increase at a different rate than the analog input does.Ideally.Manufactures include”No missing Codes”spec.Gain error has a non ideal slope. Gain and Offset error .DNL error of greater than -1LSB implies that at least one code is missing. as the analog input increases at a certain rate. the output codes would also increase at the same rate. . . Gain error can be defined as the difference between the level that produces the greatest code and the smallest code. However. then it results in gain error.For DAC. DNL error of greater than -1LSB implies that the device is non-monotonic.. in the graphs above.For an ADC.

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ENOB(Effective Number of bits) -The number of bits achieved in a real system. -difference between the signal amplitude and the first and largest harmonic spur. -Another way of specifying SNR. discounting bits that are affected by noise.(dB) -expression of distortion effect of signal harmonics on the original signal.Dynamic Characteristics 1. . .Measure of strength of a signal to background noise. -headroom available in FFT plot. 2. SFDR(Spurious dynamic range) -Distance in dB between the fundamental input and the worst spur. a low SNR means the device has lots of hiss and static high rating. 17 .Contributes to the overall dynamic performance of the device at higher frequencies and affects the linearity at those frequencies. . SNR (Signal-to-Noise Ratio) .In audio world. -higher values are desirable. 4.Key measure of Data converter. Total Hormonic Distortion . 3. -measure of signal quality.The ratio of sum of the powers of all hormonic frequencies above the fundamental frequency to the power of the funadamental frequency. .RMS value representing the ratio of the amplitude of the desired signal to noise power below one half of the frequency.

Data Converters Building blocks • • • • • • • Sample and Hold Circuits Operational Amplifiers.OTA’s Comparators Filters Current sources Reference Circuits Logic Circuits 18 .

Data Converters blocks-DAC Digital n-bit word 19 .

• The Least and Most Significant Bits(LSB & MSB) are just what their name implies. the MSB has a weight of 2 (n-1) = 2 n / 2 where ‘n’ is the total number of bits in the word. • LSB has a weight of 1. Digital coding techniques 20 .• For an n-bit word.

in a thermometer-code the number of 1’s represent the decimal value.Thermometer code • Thermometer-code differs from a binary code in that a thermometer-code has 2N . • Typically.1 digital inputs to represent 2N different digital values.) 21 . Features • Low DNL errors • Guarnteed monotonocity • Reduced glitch area • Increased complexity(binary code needs only N digital inputs to represent 2N different digital values.

• The transfer function of DAC is a series of discrete points as shown in fig. • 1 LSB corresponds to the height of a step between successive analog outputs. • Each of the possible digital input word has its own unique analog output voltage. 22 . • Resolution: The number of bits in the digital input word. • A DAC can be thought of as a digitally controlled potentiometer whose output is a fraction of the full scale analog voltage determined by the digital input data. An N-bit digital word is mapped in to an equivalent analog voltage by scaling a reference.

. because the resolution is finite) and is defined as the difference between Vref and VLSB or the analog output for the largest digital word (111…1) and the analog output for the smallest digital word(000. VLSB is the voltage change when one LSB changes. VFS(does not equal to Vref.0). 23 . Data Converters DAC spec-Nonlinearity The maximum analog voltage that can be generated is known as full-scale voltage.Analog output of unipolar DAC is • Vref need special care for design.

536 76. • Vout approaches that of Vref as N increases. • Precision required to map the analog voltage at high resolution is very difficult to achieve. Solution : DAC must resolve 1mV/5V = 0.Find the resolution of DAC if the output voltage is desired to change in 1mV.29uV 0.8 16 bit DAC with Vref=5v Resolution Comb 1LSB % accuracy Vfs 3 8 0. Vref: 5V Vout = F Vref F-fraction determined by n-bit word F=D/2N Vout(max) = 7/8 Vref.9999V • Increasing the resolution by 1 bit increases the accuracy by a factor of 2.02% Accuracy required = 1/2N =0.985V 16 65.0002 =.391 4.00153 4.0002 N=Log (5V/1mV)= 12. 24 .Consider 3 bit DAC.5 4.29 = 13 bits Comparison of 3. Ex. Max. Vref is 5V.375V 8 256 19.625V 12.625V MSB causes the output to change by ½ Vref. analog voltage generated-full scale voltage VFS I LSB = Vref/2N For 3-bit DAC 1 LSB= 5/8 V = 0.5mV 0.

DAC-Nonlinearity Differential Nonlinearity: • Ideal increments as per the ideal curve= 0.The difference between actual and idealdifferential nonlinearity is • DNLn = Actual increment height of transition n – Ideal increment height • N-number corresponding to digital input transition. Vref=5V 1LSB=1/8 of Vout/Vref DNL 1=DNL 2=DNL 7=0 DNL 3=1.5 LSB-1 LSB =-0.75 LSB 25 .75 LSB-1 LSB =0.5 LSB-1 LSB =0.3125V DNL 4=0.25 LSB-1 LSB =-0.625V=1LSB • Nonideal components cause the analog increments to differ from ideal values.75 LSB DNL 6=1. Differential Nonlinearity:Example n=3.5 LSB=0.5 LSB DNL 5=0.

26 .if it is to be n-bit accurate. DNL for the converter is ±0. DAC-should exhibit monotonicity if it is to function witout error.Differential Nonlinearity:Example Plot DNL in LSB versus input digital code. If the DNL for DAC is less than -1LSBs. then DAC is said to be nonmonotonic. DAC will have ±1/2 LSB of DNL .75LSBs of DNL has resolution of 4-bit DAC. Differential Nonlinearity:Example 5-bit DAC with . Generally.75LSB since the overall error of DAC is defined by its worst-case DNL. The DNL specification measures how well a DAC can generate uniform analog LSB multiples at its output.

Integral Nonlinearity: • Another important Static characteristic of DAC. INL-other errors(gain and offset are zero) 27 . • INL defines the linearity of overall transfer curve as INL n = Output value for input code n – output value of the reference line at that point. • Difference between the data converter output values and a reference straight line drawn through the first and last output values.

Another method: Best-fit-minimize INL 28 . For ex.13 bit DAC having greater than ±1/2 LSB of DNL or INL actually has the resolution of 12bit DAC.Integral Nonlinearity: Converter with N-bit resolution will have less than ±1/2 LSB of DNL or INL. 0.75 LSB.5LSB = Vref/2 N+1 Integral Nonlinearity:Ex 3-bit DAC.5 LSB and -0. Vref=5V Integral Nonlinearity: INL2 = INL4 = INL6= INL7=0 INL1 = INL3 = 0.5LSB INL5 = -0.75LSB INL for the DAC is considered to be its wirst case INL of +0.

-seen as shift in the transfer curve. 29 . an offset exists.Offset ERROR: Analog output should be 0V for D=0 However.

Latency: Total time from the moment that the input digital word changes to the analog output value has settled to within a specified tolerance.Gain ERROR: Gain error exists if the slope of the best-fit line through the transfer curve is different from the slope of the best-fit line for the ideal case. 30 . Gain error=Ideal slope-Actual slope.

33db. Dynamic Range: Largest output signal over the smallest output signal.Signal to Noise Ratio-SNR: -ratio of Signal power to the noise at the analog output. Dynamic Range: Largest output signal over the smallest output signal. Analog to Digital Converter 31 . Related to resolution N-bit DAC can produce a maximum of 2N -1 multiples of LSBs and a minimum value of 1LSB.1)/1 DB 16 bit DR is 96. Related to resolution DR = 20log(2N .

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in this example) • Resolution may also be defined as the size of the LSB or one count. analog signal may continue to varytrack-and-hold or T/H.• Resolution of an A/D Converter is the number of output bits it has(3-bits. • Analog signal is instantly captured and held until the next sampling period. Sample-and-hold(S/H) are critical in ADC. • However. 33 . • Characterize S/H circuit-performing data conversion. a finite amount of time is required for sampling. • During sampling period.

• S/H circuits operate dynamic(sample mode) in both static(hold mode) and Sample Mode • .Acquisition time: Time required for the S/H to track the analog signal to within a specified tolerance. once the sampling command has been issued. • S/H circuits use amplifiers as buffers. • Worst case acquisition time would correspond to the time required for the output to transition from 0 to Vin(max). 34 .

• Error tolerance at the output of S/H –dependent on amplifiers’s offset. then a large overshoot occur which requires a longer settling time. • If the amplifier is not compensated correctly. and the phase margin is too small. gain error and linearity.Sample Mode • . 35 .Acquisition time: • Output of T/H is limited by the amplifier’s slew rate.

Leakage current: compensated by making drain area small.Pedestal error: occurs as result of charge injection and clock feedthrough. • Clock couples onto the capacitor via overlap capacitance between the gate and the source or drain.however –increase time required to charge the capacitor to the value of the input signal. Aperture Error Transient effect that introduces error occurs between the sample and hold modes. 36 . Minimize droop: increase the value of the capacitor. Droop error: related to leakage of current from the capacitor due to parasitic impedances and to the leakage through reverse biased diode formed by drain of the switch. Tradeoff. • Part of the charge built up in the channel of the switch is distributed onto the capacitor.Hold Mode 1.slightly changing its voltage.

Finite amount of time. Aperture Error Related to the frequency of the signal and the worst case aperture error occurs at the zero crossing. is required to disconnect the capacitor from the analog input source.referred to as aperture time. • Example: Given Vin= A sin 2*pi*f*t A=2V f=100KHz Aperture uncertainity is 0. where dV/dt is the greatest. This assumes that the S/H circuit is capable of sampling both positive and negative voltages. Aperture Uncertainty or aperture jitter:creating sampling error.5ns. Find the sampling error 37 . The amount of error that can be tolerated is directly related to the resolution of the conversion.

38 . the input is an analog signal with an infinite number of values.628mV For ADC.Solution: dV/dt = 2*pi*f* A cos 2*pi*f*t • Maximum slew rate occurs when cosine term is = 1. which has to be quantized into an N-bit digital word. • Sampling error = dV(max)= 0. • dV/dt (max) = 2*pi*f*A. ADC. however has to “quantize” the infinite-valued analog signal into many segments so that Number of quantization levels=2N Transfer curve: stair case Maximum output of ADC will be 111(2N -1) corresponds to Vin/Vref≥7/8. Error caused by quantization.

1 LSB = Vref/2N = 0.625V for Vref=5V Quantization Error: Difference between the actual analog input and the value of the output(staircase) given in voltage. Vref/2N = D. Quantization Error: Qe =Vin – V staircase V staicase =D. 39 . • If Qe is centered about zero so that error would be ±1/2 LSB. Quantization Error: • Sawtooth waveform is centered about ½ LSB. Qe-generated by subtracting the value of the staircase from the dashed line. VLSB VLSB is value of 1 LSB in volts. • Here entire curve is shifted to left by ½ LSB. • Ideally magnitude of Qe will be between 0 and 1 LSB. Qe-expressed in terms of LSBs.

DNL=Actual step width-Ideal step width. DNL is the difference the actual code width of a nonideal converter and the ideal case. . Last transition occurs when Vin/Vref ≥13/16.(between 0 and 1/8) Therefore the range of Vin/Vref for the digital output corresponding to 000 is half as wide as the ideal step. 40 .(between 6/8 and 7/8) DNL: Similar to that of DAC.Quantization Error: First code transition occurs when Vin/Vref ≥1/16.

41 .5LSB DNL6 = -0. Qe worsens.5LSB DNL5 = -0. DNL can be defined in either units. DNL: Ideal step width=1/8 Videalstepwidth=1/8 Vref= 0. Vref=5V.5LSB Overall DNL for the curve is ±0.5 LSB-1LSB = -0. DNL0=DNL4 =DNL5=0 DNL2 = 1.5LSB As DNL increases in either direction.Since the step widths can be converted to either volts for LSBs.5 LSB-1LSB = 0.5LSB DNL3= 0.625V=1LSB Example: 3-bit ADC. find Qe in units of LSBs.

ADC with -1LSB DNL is not guarnteed to have a missing code 42 .DNL: ADC with -1LSB DNL is guarnteed to have a missing code.missing code. DNL5 = -1LSB.

INL0=INL1 =INL4 =INL5 =INL7 =0 INL3 = 3/8 -5/16 = 1/16=0. INL=magnitude of Qe outside ±LSB band of Qe.5LSB INL6 =-0.5LSB INL determined by inspecting value of Qe. 43 .5LSB Overall INL for the curve is ±0.

Qe becomes ideal after initial offset is overcome. Offset error is a constant value. Falias = Factual . Aliasing.Fsample 44 . Gain or Scale factor error-difference Gain or Scale factor errordifference in the slope of a straight line drawn through the transfer characteristic and the slope of an ideal ADC.Offset and Gain Errors: Identical to DAC. Offset errors occur when there is a difference begtween the value of first code transition and the ideal value of ½ LSB. Dynamic aspects of converter.

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02N+1. • Sensitive analog nodes must be protected and shielded from any potential noise sources. • Successful design will always minimize the effect of the digital switching on the analog circuits. Mixed Signal layout Strategy System level. • Techniques for mixed-signal designs vary in complexity and priority.RMS = VLSB/121/2 SNR=20N log (2) + 20 log (121/2) . • Most of the ADC’s use switches controlled by digital signals. SNRD=88db Resolution=? SNR= 6. SNR=20 log (Vin(max)/Vnoise Vin(max) = Vref/2*21/2 = 2N VLSB/2*21/2 Qe.76 N= 88-1.76/6.02 = 14.20 log (2*21/2) = 6.32 bits Mixed Signal layout Issues • Analog IC’s are more sensitive to noise than digital iC’s.76 Signal to Noise Ratio(SNR) Example: 16-bit ADC. • Grounding and power supply routing must also be considered.Signal to Noise Ratio(SNR) -ratio of largest RMS input signal into the converter over the RMS value of the noise.Device level-Interconnect level • Interconnect considerations • Shielding 47 .02N+1.

• Simple resistor string of 2N identical resistors and switches. 48 . • Analog output voltage is voltage division of resistors at the selected output tap.• • • • Guard rings Fully differential/Matching design Power supply and Grounding Issues Floorplanning Types of DAC • • • • • • Resistor String R-2R ladder Network Current Steering Charge scaling DAC Cyclic DAC Pipeline DAC Resistor String DAC • Most basic DAC.

resulting in slower conversion speeds. a large parasitic capacitance appears at the output node. provided that no output current is required and the values of resistors are within the specified error tolerance . Alternative to Resistor String DAC • Input to the switch array is binary word since the decoding is inherent in binary tree arrangement of the switch. 49 . • Another drawback in resistor string is • Balance between area and power dissipation.Resistor String DAC • Arch: typically results in good accuracy. • Ouput is monotonic Drawbacks • Converter output is always connected to 2N -1 switches that are off and one switch is ON. • For larger resolution.

Imax= 5mW/5V =1mA R= 1/8 * 5V/1mA = 625 ohms. PD= 5mW. relative accuracy of resistors becomes important factor.• IC version of DAC –larger area because of large prime components for higher resolution • For low resolution use active resistors such as nwell resistors. • R can be made small to rteduce area. Resistor String Problem • 3bit resistor string DAC using binary switches. VrefV. Compute the analog output for each input digital data. 50 . • As resolution increases . power dissipation would then be critical issue as current flows through the resistor string at all times.

so that sum of all the mismatch terms were zero or ∑ i=1 2 N ∆ Ri = 0 Value of voltage at the top ri is Vi. ideal= (i) Vref/ 2N for i=1. • Let resistor Ri has mismatch error. so that Ri= R + ∆Ri ideal + mismatch • Suppose mismatches were symmetrical about the string.Data Converters DAC-Nonlinearity Mismatch errors relate to Resistor String DAC • Accuracy of resistor string is related to matching between the resistors.2N -1 51 . which determine DNL and INL.2 ….

divided by the sum of all resistors in the string i i ∑ Vi = k =1 Rk ⋅ Vref Rk = ∑ k =1 R + ∆ Rk ∑ k =1 2 N 2 N ⋅R ⋅ Vref Vi = Vref ⋅ i 2 N + Vref i 2 N ⋅R ∑ k =1 ∆ Rk Vi = Vi.02R INL = Vref i 2 N ∑ ∆ Rk k =1 /R 52 .02R≤∆Rk≤+. Vref i N INL = 2 ∑ k =1 ∆ Rk / R INL of Resistor String DAC If resistors mismatch by 2%.ideal Worst case INL when i=2N and ∆Rk mismatch. then -. ideal + Vref 2 N ∆Rk ∑ R k =1 i INL of Resistor String DAC INL= Vi-Vi.• Actual value of ith voltage will be the sum of all resistors up to and including resistor i.

025V = 5/2N+1 DNL of worst case Resistor string DAC DNL= actual step height-ideal step height Vi − Vi − 1 = (i )Vref 2 N + Vref 2 N ∑ ∆Rk R k =1 i Vactual = DNL=Vactual –Videal = Vref/2N* ∆Ri/R Vref 2 N 〈1 + ∆ Ri 〉 R 53 .01Vref Ex:Find n if limited by INL If resistors mismatch by 1%.01R≤∆Rk≤+.01R/R =.INL max = Vref/2N * 2N-1 *. then -.005Vref =.01R INL = Vref 2 N −1 2 N ∑ ∆ Rk k =1 /R INL max = Vref/2N * 2N-1 *.025V INL max = ½ LSB 1/2LSB = .02R/R =.

voltage drop leading to error Total resistance of any horizontal branch R’ R’ = R + ∆R/2 Resistance of any vertical.Ex: let ∆R = 2% DNL max= . • • Vout= -itot*Rf itot = ∑ Dk k =0 N −1 Vref 2 N ⋅ 1 2R Dk kth bit of input word Switch resistance is negligible. branch is 2R + ∆R 54 .02R/R * Vref/2N = .02LSB DNL max ≤1/2 LSB R-2R Ladder Network • Fewer resistors • Starting at the right end of network. resistance looking to right of any node to groun is 2R.

Problem 3-bit DAC R=1k. Rf = 2k. 55 .R-2R Ladder Network R’-2R’ relationship to be maintained. Vref=5V Switch resistances negligible. Dummy switch size of a 2R switch will have to be placed in series with the terminating resistor as well.

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Current Steering Uses current throughout conversion. Set of current sources 57 . Requires precision current source.

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