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ABSTRACT

REVERSIBLE logic is an emerging research area. Interest in this field is motivated by its applications in several technologies involving low voltages and low power. Binary reversible circuits have been studied for their potential application in low-power CMOS design, quantum computation. Reversible computing was found on the basis of thermodynamics of information processing; it was shown that conventional irreversible circuits unavoidably generate heat because of loss of information during the computation. Reversible computing is based on two concepts: logical reversibility and physical reversibility. A computational operation is said to be logically reversible if the input of the system can be retrieved from the output obtained from it. Irreversible erasure of a bit in a system leads to generation of energy in the form of heat. An operation is said to be physically reversible if it converts no energy to heat and produces no entropy. Landauer has shown that for every bit of information lost in logic computations that are not reversible, kT ln2 joules of heat energy is generated, where k is Boltzmanns constant and T the absolute temperature at which computation is performed. The amount of energy dissipation in a system increases in direct proportion to the number of bits that are erased during computation. Bennett showed that kT ln2 energy dissipation would not occur, if a computation were carried out in a reversible way. Efficient charge recovery logic (ECRL) is proposed as a candidate for low-energy adiabatic logic circuit. Proposed logic shows four to six times power reduction with a practical loading and operation frequency range. The ECRL inverter chain shows 1020 times power gain over a conventional inverter chain. The main objective of the project is to realize 2:4 decoder using Basic reversible gates using Feynman & Peres, Feynman & Fredkin, Feynman & Toffoli and Fredkin gates only. Compare the parameters like Transistor cost, Quantum cost, gate cost, line cost and garbage outputs amongst the proposed designs in REV KIT. Synthesis of the designs is performed in REVKIT. Python language is used for coding. Calculate the power dissipated by reversible decoder. A 3:8 decoder is designed using reversible gates using three 2:4 decoders and synthesized. Compare the power dissipated by the reversible decoder with that of the conventional one. Also realize 4:2 Encoder is using Basic reversible gates. Compare the parameters like Transistor cost, Quantum cost, gate cost, line cost and garbage outputs amongst the proposed designs in REV KIT. Synthesis of the designs is performed in REVKIT. Python language is used for coding. Calculate the power dissipated by reversible encoder. A 8:3 encoder is designed using reversible gates using three 4:2 encoders and synthesized. Compare the power dissipated by the reversible encoder with that of the conventional one. Tools used : REVKIT, CADENCE