ISSCC 89 /THURSDAY, F

Y 16,1989 / EAST G

ROOM / 11:45 A.M.

SESSION 10: T H A M 10.6:

N 0 NVO LATl LE ME M 0 R I ES

A 1Mb FLASH EEPROM

Raul-Adrian Cernea, Gheorghe Samachisa, Chien-Sheng Su, Hui-Fang Tsai, Yu-Sheng Kao, Cheng-Yuan Michael Wang, Yueh-Shing Chen, Alan Renninger, Ting Wong /James Brennan, Jr., Jeff Haines SEEQ Technology Inc. /National Semiconductor San Jose, CA /West Jordan, U T

A lhlbit FLASII EEPROhl with a 5.6 x 4.4pm cell is fabricated with a double-polysilicon single-metal N-well CMOS process (Fig. 1). A double-diffused drain structure is used to reduce hot-electron degradation of N-channel peripheral devices. A summary of the process is presented in Table 1. The memory is organized into 1024 rows and 128 columns for each output. Erase and programming operations are internally controlled by a timer that is stabilized aagainst temperature and voltage supply variations. Addresses and data are latched during program and erase operations. Internal pumps generate the high voltage for the erase operation. Six redundant rows and two redundant columns are provided to enhance yield. Flash EEPROM cells similar t o the array cells are used as the programmable elements in the redundancy circuits. During the read operation, the sense current of the array cell, with drain kept at a constant voltage and gate at VCC, is compared t o a mirrored reference current (Fig. 2). An inverter, using a depletion transistor as the pull-up device for VCC insensitivity, senses the bit line voltage while feeding it back to the gate of a native pass transistor that regulates the bit line voltage and separates the bit line capacitance from the sensing node. An identical circuit is used t o regulate the drain voltage of the UV-erased flash EEPROM reference cell. The same circuit configuration is used t o clamp the sensing node at a voltage higher than that of the bit line while keeping the native transistor saturated for faster bit line precharge. With a poly-II-only word line, the access time is typically 120 ns (Fig. 3). For latching the addresses, a master-slave latch is set at the falling edge of the control signal (either WE or CE), while data is latched at the rising edge of the control signal. The internal timer controls the duration of the erase/programming operations with no need for external signals. Timing of these operations is optimized by the internal circuitry in order t o minimize the voltage stress experienced by the memory cell. The oscillator has two symmetrical halves with two capacitances alternatively charged t o a voltage Vref by a current Vref/R, R being the resistance of a poly-I1 resistor (Fig. 4).The period is 2RC, independent of Vref and thus of VCC, and has a low temperature coefficient. Measured period has +2%variation over VCC range and ?100/0variation over temperature range. The lOMHz oscillator drives 29 shift registers organized in three loops of shift register generators, t o provide all the waveforms needed for programming (ms range) and flash (seconds range) operations. Also the timer provides a fail-safe feature which prevents

unintentional erasing of the memory. The erase operation brings the whole chip or a column t o the FF state. Internal pumps, powered from Vpp, supply the drain current of the cells to be erased. In order t o supply DC current, depletion devices are used as the drivers of a cross-coupled system of diode-connect hlOS transistors (Fig. 5 ) . During the erase operation the drain voltage rises with time as the floating gate becomes less negatively charged through FowlerNordheim tunnelling. The gate of the cell remains grounded during this period. Programming operation is similar t o EPROhl and is also controlled by the timer. During power-up, a special circuit protects the memory against false write or erase. For testing and process monitoring, charge gain stress test, DC erase, and program disturb stress modes are implemented. In addition, the clock frequency can be read from an I/O pin. A micrograph of the chip is shown in Figure 6.

Acknowledgement The authors thank D. Anderson and B. Dockter for layout, D. Laughlin and B. Khoury for testing and characterization, M. Villott for support and P. Salsbury for guidance.

I . Sum Lithography Double Polysilicon N- Well CMOS Cell Size Cell Gate Oxide Interpoly Dielech'c Periphery Gate Oxide N+ Junction Depth P+ Junction Depth N-Well Junction Depth N-Channel Min Left P-Channel Min Left

14.6pm2 200 A 375 N 340 A .4pm

.5um
3.75pm 1.2pm 1.4~m

TABLE 1 - Process parameters

138

1989 lEEE International Sotid-Stow Circuita Conference

~ 1989 IEEE ~ 6 ~ 1

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ISSCC 89 /THURSDAY, FEBRUARY 16,1989 1 EAST GRAND BALLROOM I THAM 10.6

FIGL RE 3

- Access

time

VDD

VDD

VDD

REF

FIGURE; 1- Oscillator
FIGURE 1 - (a) Flash EEPROM cell cross section (b) Flash E.FPKO\I arral

PRECHARGING PATH SENSING NODE

OUTPUT BUFFER

REFERENCE CELL (UVERASED)

1."."'",-E,L

FIGURE 2

- Sense

amplifier

FIGURE 5

Write/flash pump

FIGURE 6 - See page 316

DIGEST OF TECHNICAL PAPERS

739

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T H A M 10.6: A lMb FLASH EEPROM (Continued from page 139)

FIGURE 6 - Chip micrograph

316

1989 IEEE lnternational Solid-State Circuits Conference

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