HEF4093B

Quad 2-input NAND Schmitt trigger

Rev. 04 12 June 2008 Product data sheet

1. General description
The HEF4093B is a quad two-input NAND gate. Each input has a Schmitt trigger circuit. The gate switches at different points for positive-going and negative-going signals. The difference between the positive voltage (VT+) and the negative voltage (VT) is dened as hysteresis voltage (VH). It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. The HEF4093B is suitable for use over both the industrial (40 C to +85 C) and automotive (40 C to +125 C) temperature ranges.

2. Features
I I I I I I I Schmitt trigger input discrimination Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Operates across the automotive temperature range from 40 C to +125 C Complies with JEDEC standard JESD 13-B ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V

3. Applications
I Wave and pulse shapers I Astable multivibrators I Monostable multivibrators

4. Ordering information
Table 1. Ordering information All types operate from 40 C to +125 C. Type number HEF4093BP HEF4093BT Package Name DIP14 SO14 Description plastic dual in-line package; 14 leads (300 mil) plastic small outline package; 14 leads; body width 3.9 mm Version SOT27-1 SOT108-1

NXP Semiconductors

HEF4093B
Quad 2-input NAND Schmitt trigger

5. Functional diagram

1A

1 3 1Y

1B

2A

5 4 2Y

2B

3A

8 10 3Y

3B

4A

12 11 4Y nA nY
001aag104

4B

13

nB

001aag105

Fig 1.

Functional diagram

Fig 2.

Logic diagram (one gate)

6. Pinning information
6.1 Pinning

1A 1B 1Y 2Y 2A 2B VSS

1 2 3 4 5 6 7
001aag106

14 VDD 13 4B 12 4A

HEF4093B 11 4Y
10 3Y 9 8 3B 3A

Fig 3.

Pin conguration

6.2 Pin description

Table 2. Symbol 1A to 4A 1B to 4B Pin description Pin 1, 5, 8, 12 2, 6, 9, 13 Description input input

HEF4093B_4

NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 04 12 June 2008

2 of 14

NXP Semiconductors

HEF4093B
Quad 2-input NAND Schmitt trigger

Table 2. Symbol 1Y to 4Y VDD VSS

Pin description continued Pin 3, 4, 10, 11 14 7 Description output supply voltage ground (0 V)

7. Functional description
Table 3. Input nA L L H H
[1]

Function table[1] Output nB L H L H nY H H H L

H = HIGH voltage level; L = LOW voltage level.

8. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground). Symbol VDD IIK VI IOK II/O IDD Tstg Tamb Ptot Parameter supply voltage input clamping current input voltage output clamping current input/output current supply current storage temperature ambient temperature total power dissipation Tamb = 40 C to +125 C DIP14 SO14 P
[1] [2]
[1] [2]

Conditions VI < 0.5 V or VI > VDD + 0.5 V VO < 0.5 V or VO > VDD + 0.5 V

Min 0.5 0.5 65 40 -

Max +18 10 VDD + 0.5 10 10 50 +150 +125 750 500 100

Unit V mA V mA mA mA C C mW mW mW

power dissipation

per output

For DIP14 packages: above Tamb = 70 C, Ptot derates linearly with 12 mW/K. For SO14 packages: above Tamb = 70 C, Ptot derates linearly with 8 mW/K.

HEF4093B_4

NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 04 12 June 2008

3 of 14

NXP Semiconductors

HEF4093B
Quad 2-input NAND Schmitt trigger

9. Recommended operating conditions

Table 5. Symbol VDD VI Tamb t/V Recommended operating conditions Parameter supply voltage input voltage ambient temperature input transition rise and fall rate in free air VDD = 5 V VDD = 10 V VDD = 15 V Conditions Min 3 0 40 Max 15 VDD +125 3.75 0.5 0.08 Unit V V C ns/V ns/V ns/V

10. Static characteristics

Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD; unless otherwise specied. Symbol Parameter VIH HIGH-level input voltage Conditions |IO| < 1 A VDD 5V 10 V 15 V VIL LOW-level input voltage |IO| < 1 A 5V 10 V 15 V VOH HIGH-level output voltage |IO| < 1 A 5V 10 V 15 V VOL LOW-level output voltage |IO| < 1 A 5V 10 V 15 V IOH HIGH-level output current VO = 2.5 V VO = 4.6 V VO = 9.5 V VO = 13.5 V IOL LOW-level output current VO = 0.4 V VO = 0.5 V VO = 1.5 V II IDD input leakage current supply current 5V 5V 10 V 15 V 5V 10 V 15 V 15 V all valid input 5V combinations; 10 V IO = 0 A 15 V Tamb = 40 C Tamb = +25 C Tamb = +85 C Tamb = +125 C Unit Min 3.5 7.0 11.0 4.95 9.95 14.95 1.7 0.64 1.6 4.2 0.64 1.6 4.2 Max 1.5 3.0 4.0 0.05 0.05 0.05 0.1 0.25 0.5 1.0 Min 3.5 7.0 11.0 4.95 9.95 14.95 1.4 0.5 1.3 3.4 0.5 1.3 3.4 Max 1.5 3.0 4.0 0.05 0.05 0.05 0.1 0.25 0.5 1.0 7.5 Min 3.5 7.0 11.0 4.95 9.95 14.95 1.1 0.36 0.9 2.4 0.36 0.9 2.4 Max 1.5 3.0 4.0 0.05 0.05 0.05 1.0 7.5 15.0 30.0 Min 3.5 7.0 11.0 4.95 9.95 14.95 1.1 0.36 0.9 2.4 0.36 0.9 2.4 Max 1.5 3.0 4.0 0.05 0.05 0.05 1.0 7.5 15.0 30.0 V V V V V V V V V V V V mA mA mA mA mA mA mA A A A A pF

CI

input capacitance

HEF4093B_4

NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 04 12 June 2008

4 of 14

NXP Semiconductors

HEF4093B
Quad 2-input NAND Schmitt trigger

11. Dynamic characteristics

Table 7. Dynamic characteristics Tamb = 25 C; CL = 50 pF; tr = tf 20 ns; wave forms see Figure 4; test circuit see Figure 5; unless otherwise specied. Symbol Parameter tPHL HIGH to LOW propagation delay Conditions nA or nB to nY VDD 5V 10 V 15 V tPLH LOW to HIGH propagation delay nA or nB to nY 5V 10 V 15 V tTHL HIGH to LOW output transition time nY to LOW 5V 10 V 15 V tTLH LOW to HIGH output transition time nA or nB to HIGH 5V 10 V 15 V
[1]

Extrapolation formula[1] 63 + 0.55 CL 29 + 0.23 CL 22 + 0.16 CL 58 + 0.55 CL 29 + 0.23 CL 22 + 0.16 CL 10 + 1.0 CL 9 + 0.42 CL 6 + 0.28 CL 10 + 1.00 CL 9 + 0.42 CL 6 + 0.28 CL

Min -

Typ 90 40 30 85 40 30 60 30 20 60 30 20

Max 185 80 60 170 80 60 120 60 40 120 60 40

Unit ns ns ns ns ns ns ns ns ns ns ns ns

Typical value of the propagation delay and output transition time can be calculated with the extrapolation formula (CL in pF).

Table 8. Dynamic power dissipation VSS = 0 V; tr = tf 20 ns; Tamb = 25 C. Symbol Parameter PD dynamic power dissipation VDD 5V 10 V 15 V Typical formula PD = 1300 fi + (fo CL) VDD2 (W)
2

where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; (fo CL) = sum of the outputs; VDD = supply voltage in V.

PD = 6400 fi + (fo CL) VDD2 (W) PD = 18700 fi + (fo CL) VDD (W)

HEF4093B_4

NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 04 12 June 2008

5 of 14

NXP Semiconductors

HEF4093B
Quad 2-input NAND Schmitt trigger

12. Waveforms
tr
VI nA, nB input 0V

tf

90 %
VM

10 %
t PHL t PLH

VOH nY output VOL

90 % VM 10 % t THL t TLH 001aag197

Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. tr, tf = input rise and fall times.

Fig 4. Table 9. VDD

Propagation delay and output transition time Measurement points Input VM 0.5VDD Output VM 0.5VDD

Supply voltage 5 V to 15 V

VDD VI G
RT

VO DUT
CL

001aag182

Test data given in Table 10. Denitions for test circuit: DUT = Device Under Test. CL = load capacitance including jig and probe capacitance. RT = termination resistance should be equal to the output impedance Zo of the pulse generator.

Fig 5. Table 10. VDD

Test circuit Test data Input VI VSS or VDD tr, tf 20 ns Load CL 50 pF

Supply voltage 5 V to 15 V

HEF4093B_4

NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 04 12 June 2008

6 of 14

NXP Semiconductors

HEF4093B
Quad 2-input NAND Schmitt trigger

13. Transfer characteristics

Table 11. Transfer characteristics VSS = 0 V; Tamb = 25 C; see Figure 6 and Figure 7. Symbol Parameter VT+ positive-going threshold voltage Conditions VDD 5V 10 V 15 V VT negative-going threshold voltage 5V 10 V 15 V VH hysteresis voltage 5V 10 V 15 V Min 1.9 3.6 4.7 1.5 3 4 0.4 0.6 0.7 Typ 2.9 5.2 7.3 2.2 4.2 6.0 0.7 1.0 1.3 Max 3.5 7 11 3.1 6.4 10.3 Unit V V V V V V V V V

VO VI VT+ VT VH

VH VT VT+

VI
001aag107

VO
001aag108

Fig 6.

Transfer characteristic

Fig 7.

Waveforms showing denition of VT+ and VT (between limits at 30 % and 70 %) and VH

HEF4093B_4

NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 04 12 June 2008

7 of 14

NXP Semiconductors

HEF4093B
Quad 2-input NAND Schmitt trigger

200

001aag109

1000

001aag110

IDD (A)

IDD (A)

100

500

0 0 2.5 VI (V) 5

0 0 5 VI (V) 10

a. VDD = 5 V; Tamb = 25 C
2000

b. VDD = 10 V; Tamb = 25 C
001aag111

IDD (A)

1000

0 0 10 VI (V) 20

c. Fig 8.

VDD = 15 V; Tamb = 25 C Typical drain current as a function of input

HEF4093B_4

NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 04 12 June 2008

8 of 14

NXP Semiconductors

HEF4093B
Quad 2-input NAND Schmitt trigger

10 VI (V)

001aag112

VT+ VT 5

0 2.5

7.5

10

12.5

15 VDD (V)

17.5

Tamb = 25 C.

Fig 9.

Typical switching levels as a function of supply voltage

14. Application information

Some examples of applications for the HEF4093B are:

Wave and pulse shapers Astable multivibrators Monostable multivibrators

Cp

VDD 14 1 3 VDD 2 7
001aag113
R

VDD 14 1 3 VDD 2
C

7
001aag114

Fig 10. Astable multivibrator

Fig 11. Schmitt trigger driven via a high-impedance input

If a Schmitt trigger is driven via a high-impedance (R > 1 k), then it is necessary to C V DD V SS incorporate a capacitor C with a value of ------ > ------------------------- ; otherwise oscillation can occur CP VH on the edges of a pulse. Cp is the external parasitic capacitance between inputs and output; the value depends on the circuit board layout. Remark: The two inputs may be connected together, but this will result in a larger through-current at the moment of switching.
HEF4093B_4 NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 04 12 June 2008

9 of 14

NXP Semiconductors

HEF4093B
Quad 2-input NAND Schmitt trigger

15. Package outline

DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1

D seating plane

ME

A2

A1

c Z e b1 b 14 8 MH w M (e 1)

pin 1 index E

5 scale

10 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.13 0.068 0.044 b1 0.53 0.38 0.021 0.015 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 2.2 0.087

Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT27-1 REFERENCES IEC 050G04 JEDEC MO-001 JEITA SC-501-14 EUROPEAN PROJECTION

ISSUE DATE 99-12-27 03-02-13

Fig 12. Package outline SOT27-1 (DIP14)

HEF4093B_4 NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 04 12 June 2008

10 of 14

NXP Semiconductors

HEF4093B
Quad 2-input NAND Schmitt trigger

SO14: plastic small outline package; 14 leads; body width 3.9 mm

SOT108-1

A X

c y HE v M A

Z 14 8

Q A2 pin 1 index Lp 1 e bp 7 w M L detail X A1 (A 3) A

2.5 scale

5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 8.75 8.55 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 0.028 0.024 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3

0.010 0.057 inches 0.069 0.004 0.049

0.019 0.0100 0.35 0.014 0.0075 0.34

0.244 0.039 0.041 0.228 0.016

0.028 0.004 0.012

8 o 0

Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT108-1 REFERENCES IEC 076E06 JEDEC MS-012 JEITA EUROPEAN PROJECTION

ISSUE DATE 99-12-27 03-02-19

Fig 13. Package outline SOT108-1 (SO14)

HEF4093B_4 NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 04 12 June 2008

11 of 14

NXP Semiconductors

HEF4093B
Quad 2-input NAND Schmitt trigger

16. Abbreviations
Table 12. Acronym DUT ESD HBM MM Abbreviations Description Device Under Test ElectroStatic Discharge Human Body Model Machine Model

17. Revision history

Table 13. Revision history Release date 20080612 Data sheet status Product data sheet Change notice Supersedes HEF4093B_CNV_3 Document ID HEF4093B_4 Modications:

The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Temperature range maximum increased from 85 C to 125 C throughout the data sheet. Section 4 Ordering information and Section 15 Package outline package SOT73 removed. Section 8 Limiting values and Section 10 Static characteristics added, taken from the HE4000B Family Specications data sheet. Section 10 Static characteristics IOH, IOL, II and IDD values updated. Section 11 Dynamic characteristics typical temperature coefcient for propagation delays and output transitions removed. Section 16 Abbreviations added. Product specication Product specication HEF4093B_CNV_2 -

HEF4093B_CNV_3 HEF4093B_CNV_2

19950101 19950101

HEF4093B_4

NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 04 12 June 2008

12 of 14

NXP Semiconductors

HEF4093B
Quad 2-input NAND Schmitt trigger

18. Legal information

18.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]

Product status[3] Development Qualication Production

Denition This document contains data from the objective specication for product development. This document contains data from the preliminary specication. This document contains the product specication.

Please consult the most recently issued document before initiating or completing a design. The term short data sheet is explained in section Denitions. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

18.2 Denitions
Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales ofce. In case of any inconsistency or conict with the short data sheet, the full data sheet shall prevail.

malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specied use without further testing or modication. Limiting values Stress above one or more limiting values (as dened in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/prole/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

18.3 Disclaimers
General Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or

18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

19. Contact information

For more information, please visit: http://www.nxp.com For sales ofce addresses, please send an email to: salesaddresses@nxp.com

HEF4093B_4

NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 04 12 June 2008

13 of 14

NXP Semiconductors

HEF4093B
Quad 2-input NAND Schmitt trigger

20. Contents
1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Transfer characteristics. . . . . . . . . . . . . . . . . . . 7 Application information. . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13 Denitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Contact information. . . . . . . . . . . . . . . . . . . . . 13 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information.

NXP B.V. 2008.

All rights reserved.

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 12 June 2008 Document identifier: HEF4093B_4