Test Time Reduction Techniques for Dynamic Random Access

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relationships between the fault models and physical

defects of DRAMs are discussed.
Thereafter, the
fault detection abilities of different memory test
algorithms are analyzed. In order to reduce test time,
three steps are adoptedfault accumulation, test
algorithm reduction, and seeking for alternate test
algorithms. According to experimental results, 17.1%
of the total DRAM test time can be reduced
effectively without reducing fault coverage and
fabrication yield.

30% (Dynamic Random

Access Memory; DRAM)
40~50%
DRAM
DRAM

1)
2) (pattern)3)

128M DRAM FT
(Final Test) 19.5% [4]
DRAM
DRAM (Fault Model)
DRAM

DRAM
256M DRAM CP
17.1%

Abstract
With the rapid progress of DRAM manufacturing
technology, the capacity of DRAMs keeps growing
significantly. This in turn increases the test time and
therefore the test cost. In order to alleviate this
problem, test time reduction for DRAMs should be
dealt with. This paper provides a deep discussion from
several aspects of this important topic. The

Keywords: DRAM, Test algorithm, Fault model,

Fault coverage

1.
DRAM
(particle) DRAM
DRAM
(Layout)
DRAM
DRAM

DRAM
[1]
DRAM

DRAM 228
189 17.1%

(Yield)
DRAM DRAM

2.
DRAM
(Bit Fail) (Bit-Line Fail)
(Word-Line Fail) (Others)
19
6 1-Bit2-Bit
2-BitCB2-BitDTC-Bit M-Bit
4 P-BL1-BL2-BL C-BL
4 P-WL1-WL2-WL C-WL
5 BankBlockY-DEC
SA Cross DRAM
1 1
1: DRAM

1-Bit
100% (P-WL)
53% (1-BL) 38%

3. DRAM
(Trench) 256M DDR1 SDRAM
32 15
DRAM

(Laser Repair)
DRAM

3.1 DRAM
3 DRAM
DRAM
Hard fail Soft fail
4
DRAM

DRAM
pass fail
10

Hard fail Soft fail

2: DRAM

3.2 Hard Fail

1: DRAM
DRAM
DRAM
2 DRAM

DRAM
Hard fail [2] Hard fail
DRAM 1
M5-FCN 2
{(w0);(r0, w1);(r1, w0)} March 5N
[3]
DRAM
1
Hard fail

 Hard fail 1
DRAM
1

stress DRAM
BI-DC stress BI-AC
stress
2: DRAM

Open/Short Test
DC Test
RA1

1Basic Function Test

fail

pass
2Wafer Level Burn-in
3DC Generator
4128ms Retention time
5256ms Retention time

6
7DRAM
8Signal Margin
9Bit-line Contact
10Bit-line

RA2

fail

pass

RA3

fail

pass
11
12Word-line
13
14
15

RA4

fail

pass
PASS Chip

FAIL Chip

RA: Redundancy Analysis

3: DRAM

3.3 Soft Fail

2~15 Soft Fail
Soft Fail DRAM

(weak) 4
DRAM
DRAM

2 Wafer Level
Burn-in BI-DC BI-AC
(pass)
DRAM (package) DRAM
(Final Test; FT) FT 3
Burn-in (125) (85) (-10)
Burn-in ( 2 )
( VPP: 4 (V)) stress
FT

stress
2 Burn-in

4: DRAM
3 DC Generator
BUMP {(w0);(r0)}
DC generator

DRAM
4 5
(Retention Time) 128 ms 256 ms
4 M16-128
{(w0); (r0, w1, r1); (r1, w0, r0); (r0);
(w1);(r1, w0, r0); (r0, w1, r1); (r1)}
16N-March 5 4
M12-HPMM12-HSPM12-HPPM12-HSC
12N-March {(w0); (r0, w1);
(r1, w0); (r0); (w1); (r1, w0); (r0, w1); (r1)}
4 WriteRead
background [4]
6
2 VPL1VPL0 VPL1
{(w1); (r1)} 1
(VPL) 0.5 (V)
VPL0 {(w0); (r0)}
0 VPL 1 (V)

6 weak

7 DRAM
2 TRCD TRPTRCD
{(w0); (r0)} TRP
{(w0); (r0, w1); (r1, w0)}
TRP TRCD Timing
13 ns DRAM CPU
DRAM
8 Signal Margin
4 SM1_HM SM1_HP
SM0_LM SM0_LP SM1_HM
{(w1); (r1)} 1 1
VBLEQ (Bit-line Equalize Voltage)
0.95 (V) (Sense Amplifier)
1 SM0_LM
{(w0); (r0)} 0 0
VBLEQ 0.65 V VPL 0.9 V
0 4
Write Read
background Signal Margin 1 0

9 10 CB
(Bit-line Contact) BL (Bit-line)
Write Read
WL Active SA (Enable)
timing 1 us CB CB BL
BL
9 3

CBLK_PSCBLK_PM CBLK_LPC
{(w0); (r0, w1); (r1, w0)} 3
WriteRead background
10 2 M0LK_OH
M0LK_YH M0LK_OH {(w0);
(r0)} M0LK_YH {(w1);
(r1)} 0 0 WL
Active SA Enable timing 1 us
VBLEQ 0.65 V VPP 4 V
M0LK_YH 1 1
timing 1 us VBLEQ 0.85 V
8 9
11
GIDL {(w1); (r1)}
1 1
(VNWLL) -0.65 V
GIDL (Gate
Induced Drain Leakage)
12 WL
4 LWLC_PP LWLC_SP
SWLC_DPSWLC_SP {(w0); (r0);
(w0); (r0)} WL
stress WL WL
WL
13 (Junction Leak)
CEL_JUC
{(w1); (r1)} Write Read
p-well VBB -1 V P-N

14 (Channel
Leak) 2 SUBVT1
SUBVT0 SUBVT1 {(w1);
(r1)} Write 1 Read 1
VNWLL -0.4 V (Turn-off)

15
2 TWR1PP TWR0PP
TWR1PP {(w1); (w0, w1);
(r1)} TWR0PP {(w0); (w1,
w0); (r0)} 1 0
0 1 TWR
6.5 ns
Soft
fail DRAM

DRAM fail 2~15
Soft fail
Soft fail

 Soft fail Soft fail

die DRAM

3.4
4.1
3

BI-DC BI-AC 2 stress

0
1-Bit SA
[4] SA 9
10 WL
Active SA Enable timing 1-Bit
Retention 256 ms
50%
DRAM
1-Bit
DRAM

DRAM
3:
Item

Others

WL
BL

Bit

SA

1-Bit

Fault
Coverage

M5-FCN
BI-DC
BI-AC
BUMP
M16-128
M12-HPM
M12-HSP
M12-HPP
M12-HSC
VPL1
VPL0
TRCD
TRP
SM1_HM
SM1_HP
SM0_LM
SM0_LP
CBLK_PS
CBLK_PM
CBLK_LPC
M0LK_OH
M0LK_YH
GIDL
LWLC_PP
LWLC_SP
SWLC_DP
SWLC_SP
CEL_JUC
SUBVT1
SUBVT0
TWR1PP
TWR0PP

1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0.5
0.5
0.5
0.5
0.5
1
1
1
1
1
1
1
1
1
1

0.45
0.00
0.00
0.24
0.53
0.87
0.92
0.87
0.87
0.18
0.16
0.32
0.24
0.35
0.32
0.24
0.13
0.44
0.42
0.41
0.16
0.31
0.40
0.13
0.41
0.34
0.40
0.13
0.16
0.15
0.23
0.14

97.1%
0.0%
0.0%
96.0%
97.5%
99.3%
99.6%
99.3%
99.3%
95.7%
95.6%
96.4%
96.0%
96.6%
96.4%
96.0%
95.4%
94.4%
94.3%
94.3%
93.0%
93.8%
96.9%
95.4%
96.9%
96.5%
96.9%
95.4%
95.6%
95.5%
95.9%
95.5%

4.

(%) =

A- B
100% ( 2 )
A

ATE (Automatic Test Equipment)

(2)

5 Retention
256 ms (83.3%)
M12-HPM M12-HSC

BUMP (5%) M16-128 (14.3%) TRP (2.5%)
CBLK_PS (2%) SM1_HM (1.2%) LWLC_SP
(0.8%) VPL1 (0.4%)SWLC_DP (0.4%)SUBVT1
(0.4%)
Test Time Reduction
0

5: DRAM

4.2
0

BI-DCBI-ACVPL0TRCDSM1_HP
SM0_LM SM0_LP M0LK_OH M0LK_YH
GIDLLWLC_PPSWLC_DPSUBVT0TWR1PP
TWR0PP
FT 4
M12-HPP M12-HSP
M12-HPMM12-HSC 5 Retention 256 ms

 background
M12-HPMM12-HSC
9 CBLK_PS
CBLK_PMCBLK_LPC
CBLK_LPC CEL_JUC

Retention 256 ms 4 CEL_JUC

4:

M5-FCN
BI-DC
BI-AC
BUMP
M16-128
M12-HPP
M12-HSP
M12-HPM
M12-HSC
VPL1
VPL0
TRP
TRCD
SM1_HM
SM1_HP
SM0_LM
SM0_LP
CBLK_PS
CBLK_PM
CBLK_LPC
M0LK_OH
M0LK_YH
GIDL
LWLC_PP
LWLC_SP
SWLC_DP
SWLC_SP
CEL_JUC
SUBVT1
SUBVT0
TWR1PP
TWR0PP

0%
0%
5.0%
14.3%
83.3%
6.8%
0%
0%
0.4%
0%
2.5%
0%
1.2%
0%
0%
0%
2.0%
0%
0%
0%
0%
0%
0%
0.8%
0%
0.4%
0%
0.4%
0%
0%
0%

X
X
X
X
X
V
V
V
V
X
X
X
X
V
V
V
V
V
V
V
V
V
X
V
V
V
V
V
V
V
V
V

X
X
X
X
X
V
V
V
V
X
X
X
X
X
X
X
X
V
V
V
X
X
X
X
X
X
X
V
X
X
X
X

X
X
X
X
X
X
X
V
V
X
X
X
X
X
X
X
X
X
X
V
X
X
X
X
X
X
X
V
X
X
X
X

6
2 228.37
189.88 17.1%

DRAM Yield
DRAM (Package) CP Yield
FT Yield
CP Yield = CP / CP
FT Yield = FT / CP
)
Overall Yield = CP Yield FT Yield
5 Yield

5.
DRAM

DRAM

17.1%

DRAM
5: Test Time Reduction

256M DRAM (wafer)

(sec) / die
CP Yield (%)
FT Yield (%)
Overall Yield (%)
(%)

50
228.37
88.13
96.57
85.11

50
189.88
88.12
96.52
85.05
17.1

6.
[1] M. Abadir and J.K. Reghbati, Functional Testing
of Semiconductor Random Access Memories,
ACM Computer Surveys, vol. 15, pp. 175-198,
1983.
[2] Zaid Al-Ars and Said Hamdioui, Space of DRAM
Fault Models and Corresponding Testing, EDAA,
pp. 1252-1257, 2006.
6:

4.3

M12-HPMM12-HSCCBLK_LPC CEL_JUC
4

[3] Said Hamdioui and Zaid Al-Ars, Impact of

Stresses on the Fault Coverage of Memory Tests,
in Proc. IEEE Intl Workshop on Memory
Technology, Design and Testing, pp. 27-32, 2005.
[4] Jen-Chieh and Shyr-Fen Kuo, A Systematic
Approach to Reducing Semiconductor Memory
Test Time in Mass Production, in Proc. IEEE Intl
Workshop on Memory Technology, Design and
Testing, pp. 1-6, 2005.