ADITYA CHOWDHURY

Profile :
I am currently pursuing my B.E Hons.(Electronics and Instrumentation) and M.Sc Hons.(Physics) dual degree from B.I.T.S, Pilani(Raj.). I am in the final semester of my 5 year dual degree program at the institute and I am going to graduate from the institute in May-2012.

Personal Details : Name : Date of Birth : Phone : E-Mail : Educational Qualifications : Degree Period
B.E(Electronics Instrumentation) M.Sc(Physics) Dual Senior Secondary Secondary & + 2007- 2012

Aditya Chowdhury
5th March, 1989 07877758900 aditya.chowdhury0503@gmail.com

University/Board
Birla Institute of Technology and Sciences, Pilani Central Board Education Central Board Education of of Secondary Secondary

Marks/Percentage
C.G.P.A(Cumulative Grade Point Average) 7.75 81.2 % 88.6%

2005-06 2003-04

Areas of Interest :
Digital V.L.S.I Design Analog & Mixed Signal V.L.S.I Design F.P.G.A Architecture Microprocessor Programming and Interfacing Digital Electronics Digital Image Processing

Relevant Graduate Courses :

Digital Electronics & Computer Architecture Analog & Digital V.L.S.I Design Analog Electronics Microelectronic Circuits Electronic Devices & Integrated Circuits Microprocessor Programming and Interfacing Image Processing Industrial Instrumentation & Control Electrical Sciences Circuits and Signals Digital Signal Processing Computer Programming

Projects :
1. Chip Level Design of HASH Encryption Algorithm SHA-512, as part of the Analog & Digital V.L.S.I Design Course- Digital Design Project(under Guidance of Prof. Anu Gupta, Electrical & Electronics Department, B.I.T.S Pilani)

The efficient implementation of the Secure Hash Algorithm(SHA)-512 using Verilog and the synthesis and design of the simulated algorithm using RTL Compiler & SOC Encounter tools, was acquired in this project and correct results were acquired for two testbenches. Moreover, the slack acquired during the synthesis was positive with a minimum positive slack of 28ps.The project also included Placement & Routing, design rule checks, and layout synthesis for the generated netlist. 2. On-Chip Placement of IPs and routing for an ASIC design using Place and Route tool, and performance analysis and Physical Verification, as part of Physical Design Flow in 65 nm technology, Project undertaken at ST Ericsson, Bangalore during PS-II internship The project involved performing placement and routing for modules by reading the input files, i.e. netlist, design constraints (SDC), clock description files and floorplan information, and performing standard cell placement, clock tree synthesis, crosstalk, hold and leakage Optimization, repeater insertion and routing on Cadence tool Encounter9.1. This is followed by the verification process, which involves Formal Verification, Physical Verification (DRC, LVS, Antenna checks) and multimode Static Timing Analysis (STA) to analyze timing violations in the best/worst corners. Design & Implementation of High Speed Adders on F.P.G.A Architecture, as a Lab Oriented Project under Prof. S.Gurunarayanan, Electronics & Instrumentation Department & Dean, Admissions, B.I.T.S Pilani In this project, we had simulated and analysed different Adder architectures in the F.P.G.A Simulation & Synthesis tool QUARTUS, & then implemented on the F.P.G.A. In order to display the output on the F.P.G.A, LEDs and the LCD Display on the kit were used and the comparison of different adder architectures based on their worst propagation delays, power dissipation, area etc. was done for 16, 32 and 64 bit input size. The simulation , synthesis and programming of the FPGA board Altera CYCLONE 2- UP3-2C6, was done using Altera QUARTUS tool.

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Design of a 3 bit FLASH ADC, as part of the Analog & Digital V.L.S.I Design CourseAnalog Design Project(under guidance of Prof. Anu Gupta, Electrical & Electronics Department, B.I.T.S Pilani) A 3-Bit Flash ADC(consisting of 8 comparators) was designed in the Virtuoso CADENCE tool. For this purpose, the MOS-level design of comparators as well as other gates required to design a Flash ADC were developed using CADENCE and the operating range of all the comparators and the gates were determined to construct a Flash ADC following certain given specifications, namely, 10MSamples/Sec, 5mW power dissipation, comparator with 50mV hysteresis etc. The performance of the ADC was analysed under temperature variations and the slack, hold time etc. of the ADC Circuit were determined for different inputs. C to VHDL/VERILOG Compiler Development, as part of the Compulsory Thesis Project under the supervision of Prof. Ashish Mishra, Electronics & Instrumentation Department, B.I.T.S Pilani The thesis currently being undertaken during my final semester at B.I.T.S Pilani involves learning the basics of compiler development and working on the Stanford University Intermediate Format(S.U.I.F) base to develop compiler passes to suit different FPGA architectures in order to convert ANSI-C to synthesizable, structural as well as behavioural VHDL code.

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Face Detection in Images using Colour Models, as part of an informal Computer Oriented Project under Dr. Raj Kumar Gupta, Physics Department, B.I.T.S Pilani, the work done was also presented and published in the proceedings of the 3rd International Conference on Digital Image Processing-2011, held at Chengdu, China under the supervision of IACSIT and IEEE. The development and implementation of an algorithm for the localization of facial region in a digital image consisting of multiple faces in some arbitrary background was carried out in the tool MATLAB. The algorithm utilizes the basic colour-segmentation methods where the skin and

hair regions are identified using the standard colour models. The work done in the project was published in the proceedings of, and presented by myself at the 3rd International Conference on Digital Image Processing, held at Chengdu, China from 15th-17th April. 7. Automation of Physical Layer Testing Suite, Project undertaken at ST Ericsson, Bangalore under the guidance of my mentor Mr. Srinivas Pola(Technical Lead) Project undertaken during the duration of the 5.5 month long internship at ST Ericsson, Bangalore, in which C++ and ST-Ericsson proprietary software were used to automate the testing of development code for physical layer of the mobile protocol stack. 8086 Microprocessor Based Light Dimmer System, as part of the Microprocessor Programming and Interfacing course(under guidance of Prof. S.Mohan, Group Leader, Computer Science Department, B.I.T.S Pilani) Programming and interfacing of a complete Light Intensity Manipulator system which is used to switch on and switch off a Lamp by uniformly varying the intensity of the light of the lamp. This project included the complete interfacing of the 8086 microprocessor to various other devices such as the 8255 P.P.I, 8254 timer, clock, triac etc. as well as writing the assembly level code. DSP Project on Error detection and Removal in Bitstream used in Digital Communication, as part of the Digital Signal Processing Course(under guidance of Prof. S.K.Sahoo, Electrical and Electronics Engineering Department, B.I.T.S Pilani)

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Professional Training : i) A one-month long training at B.H.E.L Electronics Division, Bangalore :- worked as an Electronics &
Instrumentation Engineer trainee. ii)Undergone training as a Project Intern at ST ERICSSON, Bangalore under the Practice School- II program conducted by B.I.T.S Pilani from July 2011-December 2011. As a project intern, my job was to conduct weekly integration tests for full stack as well as physical layer development codes released every week as well as work on my intern projects.

Computing Skills :
Languages : Verilog, VHDL, C, 8086 Assembly Language, LC-2 Assembly Level, TMS 320C54X Assembly Language, Core JAVA, Visual Basic Tools : Eldo SPICE, Quartus F.P.G.A Tool, Cadence Virtuoso Schematic & Layout Editor, Modelsim, RTL Compiler, SOC Encounter, MatLab, NI-Labview

Extracurricular Activities/ Achievements :

Senior Core Member of the social organisation, NIRMAAN from January 2008 till present. Project Leader for the project Gyan Bodh of NIRMAAN in B.I.T.S Pilani for the duration of August 2009-December 2009,as well as a member of the editorial team of the organisation. Joint Co-ordinator and Senior Core member of B.I.T.S Physics society from August 2009 till May 2010. Senior Core Member of the literature and art club of B.I.T.S Pilani, M.A.T.R.I.X from August 2008 till present Organiser of the Movie Quiz event for literary club M.A.T.R.I.X for the B.I.T.S Pilani annual Cultural Festival, Oasis 2009. General Body Member of the B.I.T.S Pilani student chapter of Association for Computing Machinery(A.C.M), BITS-ACM. Was amongst the top 500 students who qualified the 1st level of National Science Olympiad in 2002 and made it to the final national level and secured A.I.R-305.