Contributed Paper

Manuscript received January 19, 2010

Current version published 06 29 2010;
Electronic version published 07 06 2010. 0098 3063/10/$20.00 2010 IEEE
Spread Spectrum Clock Generation
for Reduced Electro-Magnetic Interference
in Consumer Electronics Devices
Jang-Woo Lee, Hong-Jung Kim, and Changsik Yoo, Member, IEEE
Abstract For better electro-magnetic interference (EMI)
reduction with minimum hardware increase, a sawtooth dual-
tone modulation profile has been applied to spread spectrum
clock generation (SSCG) phase locked loop (PLL). The SSCG
PLL implemented in a 0.18m CMOS process shows the
23.8dB EMI reduction. This result shows that proposed
modulation profile provides 3.5dB better EMI reduction with
39% increased hardware than the conventional triangular
modulation profile. For fair comparison of various
modulation profiles, a figure of merit (FoM) is introduced and
the proposed one shows the best FoM among various
modulation profiles.
1
.
Index Terms EMI reduction, spread spectrum clock
generation (SSCG), phase locked loop (PLL), sawtooth dual-
tone modulation profile.
I. INTRODUCTION
As the data rate and operating frequency increase in
consumer electronic devices, the electro-magnetic interference
(EMI) has become a critical issue. For EMI reduction several
methods can be employed such as differential signaling,
shielding, and spread spectrum clocking [1]-[2]. Among these
methods, the most effective method is the spread spectrum
clocking if the timing jitter does not increase by spreading the
spectrum [3]. In serial ATA (SATA) interface shown in Fig. 1
used for the connection of disk drive, it is specified the clock
frequency is spread by 5000ppm. To spread the spectrum of
clock signal, the clock frequency is modulated in a
predetermined manner by phase locked loop (PLL). Although
the Hershey-Kiss profile is known to be optimum for EMI
reduction, the triangular modulation profile shown in Fig. 2-
(a) is widely used because of its much simpler hardware.
However, the spread spectrum clock generation (SSCG) using
the triangular profile has limited EMI reduction [4-6]. For
better EMI reduction, the triangular modulation profile is
changed to have dual-tone as shown in Fig. 2-(b). Although
the triangular dual-tone modulation provides about 3.8dB
better EMI reduction than the conventional triangular
modulation, the hardware becomes much more complex
1
This work was supported by Hynix Semiconductor. The CAD tools were
supported by IDEC.
J.-W. Lee, H.-J. Kim, and C. Yoo are with the Integrated Circuits
Laboratory, Department of Electronics and Computer Engineering, Hanyang
University, Seoul 133-791, Korea (e-mail: csyoo@hanyang.ac.kr).
because one more waveform generator and one full adder are
required to implement the triangular dual-tone modulation
profile. In this paper, a sawtooth dual-tone modulation profile
is proposed which provides EMI reduction comparable to the
triangular dual-tone modulation profile with much simpler
hardware.
II. SAWTOOTH DUAL-TONE MODULATION PROFILE
If the clock spectrum is spread with two different
modulation frequencies, the EMI reduction becomes much
greater as is demonstrated with the triangular dual-tone
modulation profile [7]. The dual-tone modulation profile can
be represented by the equation;
( ) ( ) ( ) ( ) t f y f t f x f t f P
m nom m nom m
, 1 , ,
2 1
+ = o o o o
(1)
where x(f
m1
,t) and y(f
m2
,t) are the single-tone modulation
profiles with the modulation frequency f
m1
and f
m2
,
respectively, is the deviation from the nominal frequency
f
nom
, and and (1 -) are the factors for the weighted sum of
the dual-tones. Fig. 3 shows the spread spectrum clock
generation (SSCG) PLL with the dual-tone modulation
profile. The fractional division ratio is controlled by two
waveform generators which generate the single-tone profiles
x(f
m1
,t) and y(f
m2
,t). The full adder and third-order sigma-delta
modulator provides the final dual-tone modulation profile.
To realize the triangular dual-tone modulation profile, x(f
m1
,t)
and y(f
m2
,t) should be triangular waveforms which require
Fig. 1. Serial ATA connectivity
844 IEEE Transactions on Consumer Electronics, Vol. 56, No. 2, May 2010
up/down counters [4]. The hardware complexity of up/down
counter with large number of bits is very high. If x(f
m1
,t) and y(f
m2
,t)
are sawtooth waveforms as shown in Fig. 2-(c), only up counters
are required and therefore the proposed sawtooth dual-tone
modulation profile can be realized with much simpler hardware.
Although the sawtooth dual-ton modulation profile can greatly
simplify the hardware complexity, the timing jitter of the output
clock may increase due to the frequency jump at every sharp edge
of sawtooth waveforms. As is clear in Fig. 2-(c), the frequency is
linearly increased up to the maximum value and then
instantaneously decreased down to the minimum value. At this
instant, the change in the clock cycle time can be very large, which
results in larger cycle-to-cycle jitter. Fortunately, the weighted
summing of two sawtooth waveforms and low-pass filtering nature
of the PLL alleviates this problem. Because the two sawtooth
waveforms have their maximum and minimum values at different
timing instants, the frequency jump is smaller if they are added
together. The finite loop bandwidth of the PLL makes the change
in the output clock frequency less sharp than that of the modulation
profile, aiding to decrease the output timing jitter.
III. EXPERIMENT RESULTS
To verify the effectiveness of the proposed sawtooth dual-
tone modulation profile, a prototype has been implemented in
a 0.18 m CMOS technology. The chip microphotograph is
shown in Fig. 4. For fair comparison, three SSCG PLLs are
designed, each of which operates with the conventional
triangular, triangular dual-tone, and sawtooth dual-tone
modulation profiles, respectively. The SSCG PLLs generate
5,000ppm down spread clock with 1.5GHz nominal clock
frequency. The loop bandwidth of the PLLs is 170kHz. Fig. 5
shows the measured spectrum of the clock (a) without SSCG,
with (b) conventional triangular, (c) triangular dual-tone, and
(d) sawtooth dual-tone modulation profile. Table I. compares
the hardware complexity and performance of the three
modulation schemes. While the proposed sawtooth dual-tone
modulation profile provides similar EMI reduction to that of
dual-tone triangular modulation profile, the gate count of the
modulation profile generator of the proposed one is only half
of that of the triangular dual-tone modulation profile. The
peak to peak jitter increased due to the SSCG PLL with the
proposed sawtooth dual-tone modulation profile is
slightly larger than the others due to the frequency jump
at the sharp edge of sawtooth shaped frequency change.
Fig. 4. Chip microphotograph
Fig. 3. The block diagram of the SSCG PLL.
(a)
(b)
(c)
Fig. 2. Modulation profiles (a) Triangular modulation profile (b)
Triangular dual-tone modulation profile (c) Sawtooth dual-tone
modulation profile
J.-W. Lee et al.: Spread Spectrum Clock Generation for Reduced Electro-Magnetic Interference in Consumer Electronics Devices 845
For fair comparison of various modulation profiles, the
amount of EMI reduction, the number of gates of SSCG
generator, and the jitter have to be considered
simultaneously. Therefore, a figure-of-merit (FoM) of
modulation profile is introduced as ;
|
|
.
|

\
|
=
] [
] [ 1
log 20 ] [
ps PP
ps
N
EMIR
dB FoM
jitter gate
(2)
where EMIR is the amount of EMI reduction, N
gate
is the
normalized gate count of profile generator and PP
jitter
is the
peak to peak periodic jitter increased due to the SSCG. The
FoM of proposed modulation profile is better about 2.15 dB
than the others. The overall power consumption of the
proposed SSCG PLL is 61mW.
IV. CONCLUSION
In this paper, the sawtooth dual-tone modulation profile is
proposed and compared to the conventional triangular and
triangular dual-tone modulation profiles and a FoM is
TABLE I
COMPARISON OF VARIOUS MODULATION PROFILES FOR SSCG
Jitter
Modulation profile
Normalized gate count of profile
generator
EMI reduction
(RBW=1kHz)
[dB]
Peak to peak periodic jitter
increased due to SSCG [ps]
Random rms jitter
[ps]
Figure of Merit
[dB]
Triangular 1 20.3 6.2 8.0 24.75
Triangular dual-tone 2.77 24.2 5.5 8.1 24.74
Sawtooth dual-tone (proposed) 1.39 23.8 7.8 8.2 26.89
(a) (b)
(c) (d)
Fig. 5. Measured output spectrums of various modulation profiles : (a) without SSCG, (b) triangular modulation profile (c) triangular dual-tone
modulation profile (d) sawtooth dual-tone modulation profile.
846 IEEE Transactions on Consumer Electronics, Vol. 56, No. 2, May 2010
introduced for fair comparison of various modulation profiles.
Experimental result shows that the proposed sawtooth dual-
tone modulation profile provides the 23.81 dB EMI reduction
with very slight increase in timing jitter. The EMI reduction is
comparable to that of the triangular dual-tone modulation
profile while the gate count of the modulation profile
generator of the proposed one is only half of that of the
triangular dual-tone modulation profile. Thus, the FoM of
proposed modulation profile is better 2.15 dB than the other
modulation profiles.
REFERENCES
[1] Serial ATA Workgroup, SATA : High speed Serialized AT Attachment,
Revision 1.0, 26, May, 2004.
[2] Design for EMI, Application Note AP-589, Intel, February 1999.
[3] K. B. Hardin, J. T. Fessler and D. R. Bush, Spread Spectrum Clock
Generation for the Reduction of Radiated Emissions, IEEE
International Symposium on Electro-magnetic Compatibility, pp.227-
231, Aug. 1994.
[4] W. T. Chen, J. C. Hsu, H. W. Lune and C. C. Su, A spread spectrum
clock generator for SATA-II, Circuits and Systems, 2005. ISCAS 2005.
IEEE International Symposium on, pp23-26, May. 2005.
[5] H. R. Lee, O. Kim, G. Ahn and D. K. Jeong; A low-jitter 5000ppm
spread spectrum clock generator for multi-channel SATA transceiver in
0.18m CMOS, Solid-State Circuits Conference, 2005. Digest of
Technical Papers. ISSCC. 2005 IEEE International 10-10, pp162 - 163
Vol. 1, Feb. 2005.
[6] M. Kokubo, T. Kawamoto, T. Oshima, T. Noto, M. Suzuki, S. Suzuki, T.
Hayasaka, T. Takahashi and J. Kasai, Spread-spectrum clock generator
for serial ATA using fractional PLL controlled by modulator with
level shifter, Solid-State Circuits Conference, 2005. Digest of Technical
Papers. ISSCC. 2005 IEEE International 10-10, pp160 - 161 Vol. 1Feb.
2005.
[7] D. S. Kim and D. K. Jeong, A Spread Spectrum Clock Generation PLL
with Dual-tone Modulation Profile, Dig. Tech. Papers, IEEE VLSI
Circuits Symp. pp.96-99, Jun. 2005.
BIOGRAPHIES
Jang-woo Lee (S05) received the B.S. and M.S. degrees
in electrical and computer engineering from Hanyang
University, Seoul, Korea in 2005 and 2007 respectively.
He is currently working toward the Ph.D. degree at
Hanyang University. His research interests include a
PLL/DLL and high speed interface circuit design
Hong-jung Kim received the B.S. and M.S. degrees in
electrical and computer engineering from Hanyang
University, Seoul, Korea in 2007 and 2009 respectively.
He is currently working at Hynix Semiconductor. His
research interests include a PLL/DLL and high speed
interface circuit design
Changsik Yoo (S92-M00) received the B.S. (with the
highest honor), M.S. and Ph.D. degrees from Seoul
National University, Seoul, Korea, in 1992, 1994, and
1998, respectively, all in electronics engineering. From
1998 to 1999, he was with Integrated Systems Laboratory
(IIS), Swiss Federal Institute of Technology (ETH),
Zurich, Switzerland, as a Member of Research Staff
working on CMOS RF circuits. From 1999 to 2002, he was with Samsung
Electronics, Hwasung, Korea. Since 2002, he has been an associate professor
of Hanyang University, Seoul, Korea. He is the winner or co-winner of several
technical awards including Samsung Best Paper Bronze Award in 2006
International SoC Design Conference, Silver Award in 2006 IDEC Chip
Design Contest, Best Paper Award in 2006 Silicon RF IC Workshop, and
Golden Prize for research achievement in the next generation DRAM design
from Samsung Electronics in 2002. He serves as a member of technical
committee of ISSCC and ESSCIRC. His main research interests include
CMOS RF transceiver design, mixed mode CMOS circuit design, and high
speed interface circuit design
J.-W. Lee et al.: Spread Spectrum Clock Generation for Reduced Electro-Magnetic Interference in Consumer Electronics Devices 847